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arm64: dts: hisilicon: list all clocks required by snps-dw-apb-uart.yaml

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The snps,dw-apb-uart binding need to specify two clocks: "baudclk",
"apb_pclk". But only "apb_pclk" is specified now. Because the driver
preferentially matches the first clock. Otherwise, it matches the second
clock instead of both clocks. So both of them use the same clock don't
change the function.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
This commit is contained in:
Zhen Lei 2020-10-12 21:17:39 +08:00 committed by Wei Xu
parent 58dd4736b8
commit c4cbd0356c
1 changed files with 4 additions and 4 deletions
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8
arch/arm64/boot/dts/hisilicon/hip05.dtsi
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@ -300,8 +300,8 @@
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x0 0x80300000 0x0 0x10000>; reg = <0x0 0x80300000 0x0 0x10000>;
interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&refclk200mhz>; clocks = <&refclk200mhz>, <&refclk200mhz>;
clock-names = "apb_pclk"; clock-names = "baudclk", "apb_pclk";
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
status = "disabled"; status = "disabled";
@ -311,8 +311,8 @@
compatible = "snps,dw-apb-uart"; compatible = "snps,dw-apb-uart";
reg = <0x0 0x80310000 0x0 0x10000>; reg = <0x0 0x80310000 0x0 0x10000>;
interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&refclk200mhz>; clocks = <&refclk200mhz>, <&refclk200mhz>;
clock-names = "apb_pclk"; clock-names = "baudclk", "apb_pclk";
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
status = "disabled"; status = "disabled";