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thunderbolt: Clear registers properly when auto clear isn't in use
When `QUIRK_AUTO_CLEAR_INT` isn't set, interrupt masking should be
cleared by writing to Interrupt Mask Clear (IMR) and interrupt
status should be cleared properly at shutdown/init.
This fixes an error where interrupts are left enabled during resume
from hibernation with `CONFIG_USB4=y`.
Fixes: 468c49f447
("thunderbolt: Disable interrupt auto clear for rings")
Cc: stable@vger.kernel.org # v6.3
Reported-by: Takashi Iwai <tiwai@suse.de>
Link: https://bugzilla.kernel.org/show_bug.cgi?id=217343
Signed-off-by: Mario Limonciello <mario.limonciello@amd.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
This commit is contained in:
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@ -54,6 +54,21 @@ static int ring_interrupt_index(const struct tb_ring *ring)
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return bit;
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}
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static void nhi_mask_interrupt(struct tb_nhi *nhi, int mask, int ring)
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{
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if (nhi->quirks & QUIRK_AUTO_CLEAR_INT)
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return;
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iowrite32(mask, nhi->iobase + REG_RING_INTERRUPT_MASK_CLEAR_BASE + ring);
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}
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static void nhi_clear_interrupt(struct tb_nhi *nhi, int ring)
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{
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if (nhi->quirks & QUIRK_AUTO_CLEAR_INT)
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ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + ring);
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else
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iowrite32(~0, nhi->iobase + REG_RING_INT_CLEAR + ring);
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}
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/*
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* ring_interrupt_active() - activate/deactivate interrupts for a single ring
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*
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@ -61,8 +76,8 @@ static int ring_interrupt_index(const struct tb_ring *ring)
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*/
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static void ring_interrupt_active(struct tb_ring *ring, bool active)
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{
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int reg = REG_RING_INTERRUPT_BASE +
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ring_interrupt_index(ring) / 32 * 4;
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int index = ring_interrupt_index(ring) / 32 * 4;
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int reg = REG_RING_INTERRUPT_BASE + index;
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int interrupt_bit = ring_interrupt_index(ring) & 31;
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int mask = 1 << interrupt_bit;
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u32 old, new;
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@ -123,7 +138,11 @@ static void ring_interrupt_active(struct tb_ring *ring, bool active)
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"interrupt for %s %d is already %s\n",
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RING_TYPE(ring), ring->hop,
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active ? "enabled" : "disabled");
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iowrite32(new, ring->nhi->iobase + reg);
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if (active)
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iowrite32(new, ring->nhi->iobase + reg);
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else
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nhi_mask_interrupt(ring->nhi, mask, index);
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}
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/*
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@ -136,11 +155,11 @@ static void nhi_disable_interrupts(struct tb_nhi *nhi)
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int i = 0;
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/* disable interrupts */
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for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++)
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iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i);
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nhi_mask_interrupt(nhi, ~0, 4 * i);
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/* clear interrupt status bits */
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for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++)
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ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i);
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nhi_clear_interrupt(nhi, 4 * i);
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}
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/* ring helper methods */
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@ -93,6 +93,8 @@ struct ring_desc {
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#define REG_RING_INTERRUPT_BASE 0x38200
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#define RING_INTERRUPT_REG_COUNT(nhi) ((31 + 2 * nhi->hop_count) / 32)
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#define REG_RING_INTERRUPT_MASK_CLEAR_BASE 0x38208
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#define REG_INT_THROTTLING_RATE 0x38c00
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/* Interrupt Vector Allocation */
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