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[MIPS] SMTC: Safety net for i8259A interrupts.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
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@ -330,6 +330,18 @@ void __init arch_init_irq(void)
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(0x100 << MIPSCPU_INT_I8259A));
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setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
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&corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
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/*
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* Temporary hack to ensure that the subsidiary device
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* interrupts coing in via the i8259A, but associated
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* with low IRQ numbers, will restore the Status.IM
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* value associated with the i8259A.
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*/
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{
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int i;
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for (i = 0; i < 16; i++)
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irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
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}
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#else /* Not SMTC */
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setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
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setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);
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