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hwrng: starfive - Add TRNG driver for StarFive SoC
This adds driver support for the hardware random number generator in Starfive SoCs and adds StarFive TRNG entry to MAINTAINERS. Co-developed-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jenny Zhang <jenny.zhang@starfivetech.com> Signed-off-by: Jia Jie Ho <jiajie.ho@starfivetech.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
This commit is contained in:
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a482b02d6a
commit
c388f458bc
@ -19905,6 +19905,12 @@ F: Documentation/devicetree/bindings/reset/starfive,jh7100-reset.yaml
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F: drivers/reset/reset-starfive-jh7100.c
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F: include/dt-bindings/reset/starfive-jh7100.h
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STARFIVE TRNG DRIVER
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M: Jia Jie Ho <jiajie.ho@starfivetech.com>
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S: Supported
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F: Documentation/devicetree/bindings/rng/starfive*
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F: drivers/char/hw_random/starfive-trng.c
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STATIC BRANCH/CALL
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M: Peter Zijlstra <peterz@infradead.org>
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M: Josh Poimboeuf <jpoimboe@kernel.org>
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@ -549,6 +549,17 @@ config HW_RANDOM_CN10K
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To compile this driver as a module, choose M here.
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The module will be called cn10k_rng. If unsure, say Y.
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config HW_RANDOM_JH7110
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tristate "StarFive JH7110 Random Number Generator support"
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depends on SOC_STARFIVE
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depends on HW_RANDOM
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help
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This driver provides support for the True Random Number
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Generator in StarFive JH7110 SoCs.
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To compile this driver as a module, choose M here.
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The module will be called jh7110-trng.
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endif # HW_RANDOM
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config UML_RANDOM
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@ -47,3 +47,4 @@ obj-$(CONFIG_HW_RANDOM_XIPHERA) += xiphera-trng.o
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obj-$(CONFIG_HW_RANDOM_ARM_SMCCC_TRNG) += arm_smccc_trng.o
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obj-$(CONFIG_HW_RANDOM_CN10K) += cn10k-rng.o
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obj-$(CONFIG_HW_RANDOM_POLARFIRE_SOC) += mpfs-rng.o
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obj-$(CONFIG_HW_RANDOM_JH7110) += jh7110-trng.o
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393
drivers/char/hw_random/jh7110-trng.c
Normal file
393
drivers/char/hw_random/jh7110-trng.c
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@ -0,0 +1,393 @@
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// SPDX-License-Identifier: GPL-2.0
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/*
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* TRNG driver for the StarFive JH7110 SoC
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*
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* Copyright (C) 2022 StarFive Technology Co.
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*/
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#include <linux/clk.h>
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#include <linux/completion.h>
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#include <linux/delay.h>
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#include <linux/err.h>
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#include <linux/hw_random.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/iopoll.h>
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/pm_runtime.h>
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#include <linux/random.h>
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#include <linux/reset.h>
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/* trng register offset */
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#define STARFIVE_CTRL 0x00
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#define STARFIVE_STAT 0x04
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#define STARFIVE_MODE 0x08
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#define STARFIVE_SMODE 0x0C
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#define STARFIVE_IE 0x10
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#define STARFIVE_ISTAT 0x14
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#define STARFIVE_RAND0 0x20
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#define STARFIVE_RAND1 0x24
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#define STARFIVE_RAND2 0x28
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#define STARFIVE_RAND3 0x2C
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#define STARFIVE_RAND4 0x30
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#define STARFIVE_RAND5 0x34
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#define STARFIVE_RAND6 0x38
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#define STARFIVE_RAND7 0x3C
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#define STARFIVE_AUTO_RQSTS 0x60
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#define STARFIVE_AUTO_AGE 0x64
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/* CTRL CMD */
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#define STARFIVE_CTRL_EXEC_NOP 0x0
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#define STARFIVE_CTRL_GENE_RANDNUM 0x1
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#define STARFIVE_CTRL_EXEC_RANDRESEED 0x2
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/* STAT */
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#define STARFIVE_STAT_NONCE_MODE BIT(2)
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#define STARFIVE_STAT_R256 BIT(3)
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#define STARFIVE_STAT_MISSION_MODE BIT(8)
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#define STARFIVE_STAT_SEEDED BIT(9)
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#define STARFIVE_STAT_LAST_RESEED(x) ((x) << 16)
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#define STARFIVE_STAT_SRVC_RQST BIT(27)
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#define STARFIVE_STAT_RAND_GENERATING BIT(30)
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#define STARFIVE_STAT_RAND_SEEDING BIT(31)
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/* MODE */
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#define STARFIVE_MODE_R256 BIT(3)
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/* SMODE */
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#define STARFIVE_SMODE_NONCE_MODE BIT(2)
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#define STARFIVE_SMODE_MISSION_MODE BIT(8)
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#define STARFIVE_SMODE_MAX_REJECTS(x) ((x) << 16)
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/* IE */
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#define STARFIVE_IE_RAND_RDY_EN BIT(0)
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#define STARFIVE_IE_SEED_DONE_EN BIT(1)
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#define STARFIVE_IE_LFSR_LOCKUP_EN BIT(4)
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#define STARFIVE_IE_GLBL_EN BIT(31)
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#define STARFIVE_IE_ALL (STARFIVE_IE_GLBL_EN | \
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STARFIVE_IE_RAND_RDY_EN | \
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STARFIVE_IE_SEED_DONE_EN | \
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STARFIVE_IE_LFSR_LOCKUP_EN)
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/* ISTAT */
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#define STARFIVE_ISTAT_RAND_RDY BIT(0)
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#define STARFIVE_ISTAT_SEED_DONE BIT(1)
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#define STARFIVE_ISTAT_LFSR_LOCKUP BIT(4)
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#define STARFIVE_RAND_LEN sizeof(u32)
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#define to_trng(p) container_of(p, struct starfive_trng, rng)
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enum reseed {
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RANDOM_RESEED,
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NONCE_RESEED,
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};
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enum mode {
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PRNG_128BIT,
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PRNG_256BIT,
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};
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struct starfive_trng {
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struct device *dev;
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void __iomem *base;
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struct clk *hclk;
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struct clk *ahb;
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struct reset_control *rst;
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struct hwrng rng;
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struct completion random_done;
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struct completion reseed_done;
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u32 mode;
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u32 mission;
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u32 reseed;
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/* protects against concurrent write to ctrl register */
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spinlock_t write_lock;
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};
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static u16 autoreq;
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module_param(autoreq, ushort, 0);
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MODULE_PARM_DESC(autoreq, "Auto-reseeding after random number requests by host reaches specified counter:\n"
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" 0 - disable counter\n"
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" other - reload value for internal counter");
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static u16 autoage;
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module_param(autoage, ushort, 0);
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MODULE_PARM_DESC(autoage, "Auto-reseeding after specified timer countdowns to 0:\n"
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" 0 - disable timer\n"
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" other - reload value for internal timer");
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static inline int starfive_trng_wait_idle(struct starfive_trng *trng)
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{
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u32 stat;
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return readl_relaxed_poll_timeout(trng->base + STARFIVE_STAT, stat,
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!(stat & (STARFIVE_STAT_RAND_GENERATING |
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STARFIVE_STAT_RAND_SEEDING)),
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10, 100000);
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}
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static inline void starfive_trng_irq_mask_clear(struct starfive_trng *trng)
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{
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/* clear register: ISTAT */
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u32 data = readl(trng->base + STARFIVE_ISTAT);
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writel(data, trng->base + STARFIVE_ISTAT);
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}
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static int starfive_trng_cmd(struct starfive_trng *trng, u32 cmd, bool wait)
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{
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int wait_time = 1000;
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/* allow up to 40 us for wait == 0 */
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if (!wait)
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wait_time = 40;
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switch (cmd) {
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case STARFIVE_CTRL_GENE_RANDNUM:
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reinit_completion(&trng->random_done);
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spin_lock_irq(&trng->write_lock);
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writel(cmd, trng->base + STARFIVE_CTRL);
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spin_unlock_irq(&trng->write_lock);
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if (!wait_for_completion_timeout(&trng->random_done, usecs_to_jiffies(wait_time)))
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return -ETIMEDOUT;
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break;
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case STARFIVE_CTRL_EXEC_RANDRESEED:
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reinit_completion(&trng->reseed_done);
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spin_lock_irq(&trng->write_lock);
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writel(cmd, trng->base + STARFIVE_CTRL);
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spin_unlock_irq(&trng->write_lock);
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if (!wait_for_completion_timeout(&trng->reseed_done, usecs_to_jiffies(wait_time)))
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return -ETIMEDOUT;
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break;
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default:
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return -EINVAL;
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}
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return 0;
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}
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static int starfive_trng_init(struct hwrng *rng)
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{
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struct starfive_trng *trng = to_trng(rng);
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u32 mode, intr = 0;
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/* setup Auto Request/Age register */
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writel(autoage, trng->base + STARFIVE_AUTO_AGE);
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writel(autoreq, trng->base + STARFIVE_AUTO_RQSTS);
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/* clear register: ISTAT */
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starfive_trng_irq_mask_clear(trng);
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intr |= STARFIVE_IE_ALL;
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writel(intr, trng->base + STARFIVE_IE);
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mode = readl(trng->base + STARFIVE_MODE);
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switch (trng->mode) {
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case PRNG_128BIT:
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mode &= ~STARFIVE_MODE_R256;
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break;
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case PRNG_256BIT:
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mode |= STARFIVE_MODE_R256;
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break;
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default:
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mode |= STARFIVE_MODE_R256;
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break;
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}
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writel(mode, trng->base + STARFIVE_MODE);
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return starfive_trng_cmd(trng, STARFIVE_CTRL_EXEC_RANDRESEED, 1);
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}
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static irqreturn_t starfive_trng_irq(int irq, void *priv)
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{
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u32 status;
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struct starfive_trng *trng = (struct starfive_trng *)priv;
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status = readl(trng->base + STARFIVE_ISTAT);
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if (status & STARFIVE_ISTAT_RAND_RDY) {
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writel(STARFIVE_ISTAT_RAND_RDY, trng->base + STARFIVE_ISTAT);
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complete(&trng->random_done);
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}
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if (status & STARFIVE_ISTAT_SEED_DONE) {
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writel(STARFIVE_ISTAT_SEED_DONE, trng->base + STARFIVE_ISTAT);
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complete(&trng->reseed_done);
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}
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if (status & STARFIVE_ISTAT_LFSR_LOCKUP) {
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writel(STARFIVE_ISTAT_LFSR_LOCKUP, trng->base + STARFIVE_ISTAT);
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/* SEU occurred, reseeding required*/
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spin_lock(&trng->write_lock);
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writel(STARFIVE_CTRL_EXEC_RANDRESEED, trng->base + STARFIVE_CTRL);
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spin_unlock(&trng->write_lock);
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}
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return IRQ_HANDLED;
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}
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static void starfive_trng_cleanup(struct hwrng *rng)
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{
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struct starfive_trng *trng = to_trng(rng);
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writel(0, trng->base + STARFIVE_CTRL);
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reset_control_assert(trng->rst);
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clk_disable_unprepare(trng->hclk);
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clk_disable_unprepare(trng->ahb);
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}
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static int starfive_trng_read(struct hwrng *rng, void *buf, size_t max, bool wait)
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{
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struct starfive_trng *trng = to_trng(rng);
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int ret;
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pm_runtime_get_sync(trng->dev);
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if (trng->mode == PRNG_256BIT)
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max = min_t(size_t, max, (STARFIVE_RAND_LEN * 8));
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else
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max = min_t(size_t, max, (STARFIVE_RAND_LEN * 4));
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if (wait) {
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ret = starfive_trng_wait_idle(trng);
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if (ret)
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return -ETIMEDOUT;
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}
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ret = starfive_trng_cmd(trng, STARFIVE_CTRL_GENE_RANDNUM, wait);
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if (ret)
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return ret;
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memcpy_fromio(buf, trng->base + STARFIVE_RAND0, max);
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pm_runtime_put_sync_autosuspend(trng->dev);
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return max;
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}
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static int starfive_trng_probe(struct platform_device *pdev)
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{
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int ret;
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int irq;
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struct starfive_trng *trng;
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trng = devm_kzalloc(&pdev->dev, sizeof(*trng), GFP_KERNEL);
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if (!trng)
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return -ENOMEM;
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platform_set_drvdata(pdev, trng);
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trng->dev = &pdev->dev;
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trng->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(trng->base))
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return dev_err_probe(&pdev->dev, PTR_ERR(trng->base),
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"Error remapping memory for platform device.\n");
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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init_completion(&trng->random_done);
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init_completion(&trng->reseed_done);
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spin_lock_init(&trng->write_lock);
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ret = devm_request_irq(&pdev->dev, irq, starfive_trng_irq, 0, pdev->name,
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(void *)trng);
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if (ret)
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return dev_err_probe(&pdev->dev, irq,
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"Failed to register interrupt handler\n");
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trng->hclk = devm_clk_get(&pdev->dev, "hclk");
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if (IS_ERR(trng->hclk))
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return dev_err_probe(&pdev->dev, PTR_ERR(trng->hclk),
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"Error getting hardware reference clock\n");
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trng->ahb = devm_clk_get(&pdev->dev, "ahb");
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if (IS_ERR(trng->ahb))
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return dev_err_probe(&pdev->dev, PTR_ERR(trng->ahb),
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"Error getting ahb reference clock\n");
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trng->rst = devm_reset_control_get_shared(&pdev->dev, NULL);
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if (IS_ERR(trng->rst))
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return dev_err_probe(&pdev->dev, PTR_ERR(trng->rst),
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"Error getting hardware reset line\n");
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clk_prepare_enable(trng->hclk);
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clk_prepare_enable(trng->ahb);
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reset_control_deassert(trng->rst);
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trng->rng.name = dev_driver_string(&pdev->dev);
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trng->rng.init = starfive_trng_init;
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trng->rng.cleanup = starfive_trng_cleanup;
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trng->rng.read = starfive_trng_read;
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trng->mode = PRNG_256BIT;
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trng->mission = 1;
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trng->reseed = RANDOM_RESEED;
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pm_runtime_use_autosuspend(&pdev->dev);
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pm_runtime_set_autosuspend_delay(&pdev->dev, 100);
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pm_runtime_enable(&pdev->dev);
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ret = devm_hwrng_register(&pdev->dev, &trng->rng);
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if (ret) {
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pm_runtime_disable(&pdev->dev);
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reset_control_assert(trng->rst);
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clk_disable_unprepare(trng->ahb);
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clk_disable_unprepare(trng->hclk);
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return dev_err_probe(&pdev->dev, ret, "Failed to register hwrng\n");
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}
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return 0;
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}
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static int __maybe_unused starfive_trng_suspend(struct device *dev)
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{
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struct starfive_trng *trng = dev_get_drvdata(dev);
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clk_disable_unprepare(trng->hclk);
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clk_disable_unprepare(trng->ahb);
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return 0;
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}
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static int __maybe_unused starfive_trng_resume(struct device *dev)
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{
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struct starfive_trng *trng = dev_get_drvdata(dev);
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clk_prepare_enable(trng->hclk);
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clk_prepare_enable(trng->ahb);
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return 0;
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}
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static DEFINE_SIMPLE_DEV_PM_OPS(starfive_trng_pm_ops, starfive_trng_suspend,
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starfive_trng_resume);
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static const struct of_device_id trng_dt_ids[] __maybe_unused = {
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{ .compatible = "starfive,jh7110-trng" },
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{ }
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};
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MODULE_DEVICE_TABLE(of, trng_dt_ids);
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static struct platform_driver starfive_trng_driver = {
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.probe = starfive_trng_probe,
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.driver = {
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.name = "jh7110-trng",
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.pm = &starfive_trng_pm_ops,
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.of_match_table = of_match_ptr(trng_dt_ids),
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},
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};
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module_platform_driver(starfive_trng_driver);
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("StarFive True Random Number Generator");
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