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[SCSI] hpsa: get ioaccel mode 2 i/o working
Signed-off-by: Scott Teel <scott.teel@hp.com> Signed-off-by: Joe Handzik <Joseph.T.Handzik@hp.com> Signed-off-by: Mike Miller <michael.miller@canonical.com> Signed-off-by: Stephen M. Cameron <scameron@beardog.cce.hp.com> Signed-off-by: James Bottomley <JBottomley@Parallels.com>
This commit is contained in:
Scott Teel
James Bottomley
parent
b9af4937e6
commit
c349775e4c
@ -222,6 +222,9 @@ static void hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
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#define BOARD_READY 1
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static void hpsa_drain_commands(struct ctlr_info *h);
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static void hpsa_flush_cache(struct ctlr_info *h);
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static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
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struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
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u8 *scsi3addr);
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static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
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{
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@ -622,6 +625,32 @@ static inline u32 next_command(struct ctlr_info *h, u8 q)
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return a;
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}
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/*
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* There are some special bits in the bus address of the
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* command that we have to set for the controller to know
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* how to process the command:
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*
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* Normal performant mode:
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* bit 0: 1 means performant mode, 0 means simple mode.
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* bits 1-3 = block fetch table entry
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* bits 4-6 = command type (== 0)
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*
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* ioaccel1 mode:
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* bit 0 = "performant mode" bit.
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* bits 1-3 = block fetch table entry
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* bits 4-6 = command type (== 110)
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* (command type is needed because ioaccel1 mode
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* commands are submitted through the same register as normal
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* mode commands, so this is how the controller knows whether
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* the command is normal mode or ioaccel1 mode.)
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*
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* ioaccel2 mode:
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* bit 0 = "performant mode" bit.
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* bits 1-4 = block fetch table entry (note extra bit)
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* bits 4-6 = not needed, because ioaccel2 mode has
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* a separate special register for submitting commands.
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*/
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/* set_performant_mode: Modify the tag for cciss performant
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* set bit 0 for pull model, bits 3-1 for block fetch
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* register number
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@ -636,6 +665,41 @@ static void set_performant_mode(struct ctlr_info *h, struct CommandList *c)
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}
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}
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static void set_ioaccel1_performant_mode(struct ctlr_info *h,
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struct CommandList *c)
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{
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struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
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/* Tell the controller to post the reply to the queue for this
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* processor. This seems to give the best I/O throughput.
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*/
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cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
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/* Set the bits in the address sent down to include:
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* - performant mode bit (bit 0)
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* - pull count (bits 1-3)
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* - command type (bits 4-6)
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*/
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c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
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IOACCEL1_BUSADDR_CMDTYPE;
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}
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static void set_ioaccel2_performant_mode(struct ctlr_info *h,
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struct CommandList *c)
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{
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struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
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/* Tell the controller to post the reply to the queue for this
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* processor. This seems to give the best I/O throughput.
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*/
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cp->reply_queue = smp_processor_id() % h->nreply_queues;
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/* Set the bits in the address sent down to include:
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* - performant mode bit not used in ioaccel mode 2
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* - pull count (bits 0-3)
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* - command type isn't needed for ioaccel2
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*/
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c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
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}
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static int is_firmware_flash_cmd(u8 *cdb)
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{
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return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
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@ -670,7 +734,16 @@ static void enqueue_cmd_and_start_io(struct ctlr_info *h,
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{
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unsigned long flags;
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switch (c->cmd_type) {
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case CMD_IOACCEL1:
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set_ioaccel1_performant_mode(h, c);
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break;
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case CMD_IOACCEL2:
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set_ioaccel2_performant_mode(h, c);
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break;
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default:
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set_performant_mode(h, c);
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}
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dial_down_lockup_detection_during_fw_flash(h, c);
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spin_lock_irqsave(&h->lock, flags);
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addQ(&h->reqQ, c);
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@ -1228,6 +1301,123 @@ static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
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pci_unmap_single(h->pdev, temp64.val, chain_sg->Len, PCI_DMA_TODEVICE);
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}
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static void handle_ioaccel_mode2_error(struct ctlr_info *h,
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struct CommandList *c,
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struct scsi_cmnd *cmd,
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struct io_accel2_cmd *c2)
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{
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int data_len;
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switch (c2->error_data.serv_response) {
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case IOACCEL2_SERV_RESPONSE_COMPLETE:
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switch (c2->error_data.status) {
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case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
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break;
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case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
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dev_warn(&h->pdev->dev,
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"%s: task complete with check condition.\n",
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"HP SSD Smart Path");
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if (c2->error_data.data_present !=
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IOACCEL2_SENSE_DATA_PRESENT)
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break;
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/* copy the sense data */
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data_len = c2->error_data.sense_data_len;
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if (data_len > SCSI_SENSE_BUFFERSIZE)
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data_len = SCSI_SENSE_BUFFERSIZE;
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if (data_len > sizeof(c2->error_data.sense_data_buff))
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data_len =
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sizeof(c2->error_data.sense_data_buff);
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memcpy(cmd->sense_buffer,
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c2->error_data.sense_data_buff, data_len);
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cmd->result |= SAM_STAT_CHECK_CONDITION;
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break;
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case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
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dev_warn(&h->pdev->dev,
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"%s: task complete with BUSY status.\n",
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"HP SSD Smart Path");
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break;
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case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
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dev_warn(&h->pdev->dev,
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"%s: task complete with reservation conflict.\n",
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"HP SSD Smart Path");
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break;
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case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
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/* Make scsi midlayer do unlimited retries */
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cmd->result = DID_IMM_RETRY << 16;
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break;
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case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
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dev_warn(&h->pdev->dev,
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"%s: task complete with aborted status.\n",
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"HP SSD Smart Path");
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break;
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default:
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dev_warn(&h->pdev->dev,
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"%s: task complete with unrecognized status: 0x%02x\n",
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"HP SSD Smart Path", c2->error_data.status);
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break;
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}
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break;
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case IOACCEL2_SERV_RESPONSE_FAILURE:
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/* don't expect to get here. */
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dev_warn(&h->pdev->dev,
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"unexpected delivery or target failure, status = 0x%02x\n",
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c2->error_data.status);
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break;
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case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
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break;
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case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
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break;
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case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
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dev_warn(&h->pdev->dev, "task management function rejected.\n");
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break;
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case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
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dev_warn(&h->pdev->dev, "task management function invalid LUN\n");
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break;
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default:
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dev_warn(&h->pdev->dev,
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"%s: Unrecognized server response: 0x%02x\n",
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"HP SSD Smart Path", c2->error_data.serv_response);
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break;
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}
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}
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static void process_ioaccel2_completion(struct ctlr_info *h,
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struct CommandList *c, struct scsi_cmnd *cmd,
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struct hpsa_scsi_dev_t *dev)
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{
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struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
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/* check for good status */
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if (likely(c2->error_data.serv_response == 0 &&
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c2->error_data.status == 0)) {
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cmd_free(h, c);
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cmd->scsi_done(cmd);
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return;
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}
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/* Any RAID offload error results in retry which will use
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* the normal I/O path so the controller can handle whatever's
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* wrong.
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*/
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if (is_logical_dev_addr_mode(dev->scsi3addr) &&
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c2->error_data.serv_response ==
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IOACCEL2_SERV_RESPONSE_FAILURE) {
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if (c2->error_data.status !=
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IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
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dev_warn(&h->pdev->dev,
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"%s: Error 0x%02x, Retrying on standard path.\n",
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"HP SSD Smart Path", c2->error_data.status);
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dev->offload_enabled = 0;
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cmd->result = DID_SOFT_ERROR << 16;
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cmd_free(h, c);
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cmd->scsi_done(cmd);
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return;
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}
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handle_ioaccel_mode2_error(h, c, cmd, c2);
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cmd_free(h, c);
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cmd->scsi_done(cmd);
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}
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static void complete_scsi_command(struct CommandList *cp)
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{
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struct scsi_cmnd *cmd;
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@ -1252,6 +1442,10 @@ static void complete_scsi_command(struct CommandList *cp)
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cmd->result = (DID_OK << 16); /* host byte */
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cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
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if (cp->cmd_type == CMD_IOACCEL2)
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return process_ioaccel2_completion(h, cp, cmd, dev);
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cmd->result |= ei->ScsiStatus;
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/* copy the sense data whether we need to or not. */
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@ -2463,10 +2657,7 @@ static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
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return 0;
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}
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/*
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* Queue a command to the I/O accelerator path.
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*/
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static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
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static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
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struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
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u8 *scsi3addr)
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{
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@ -2538,6 +2729,7 @@ static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
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control |= IOACCEL1_CONTROL_NODATAXFER;
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}
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c->Header.SGList = use_sg;
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/* Fill out the command structure to submit */
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cp->dev_handle = ioaccel_handle & 0xFFFF;
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cp->transfer_len = total_len;
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@ -2546,19 +2738,7 @@ static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
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cp->control = control;
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memcpy(cp->CDB, cdb, cdb_len);
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memcpy(cp->CISS_LUN, scsi3addr, 8);
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/* Tell the controller to post the reply to the queue for this
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* processor. This seems to give the best I/O throughput.
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*/
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cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
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/* Set the bits in the address sent down to include:
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* - performant mode bit (bit 0)
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* - pull count (bits 1-3)
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* - command type (bits 4-6)
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*/
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c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[use_sg] << 1) |
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IOACCEL1_BUSADDR_CMDTYPE;
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/* Tag was already set at init time. */
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enqueue_cmd_and_start_io(h, c);
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return 0;
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}
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@ -2577,6 +2757,106 @@ static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
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cmd->cmnd, cmd->cmd_len, dev->scsi3addr);
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}
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static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
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struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
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u8 *scsi3addr)
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{
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struct scsi_cmnd *cmd = c->scsi_cmd;
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struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
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struct ioaccel2_sg_element *curr_sg;
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int use_sg, i;
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struct scatterlist *sg;
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u64 addr64;
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u32 len;
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u32 total_len = 0;
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if (scsi_sg_count(cmd) > h->ioaccel_maxsg)
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return IO_ACCEL_INELIGIBLE;
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if (fixup_ioaccel_cdb(cdb, &cdb_len))
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return IO_ACCEL_INELIGIBLE;
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c->cmd_type = CMD_IOACCEL2;
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/* Adjust the DMA address to point to the accelerated command buffer */
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c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
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(c->cmdindex * sizeof(*cp));
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BUG_ON(c->busaddr & 0x0000007F);
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memset(cp, 0, sizeof(*cp));
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cp->IU_type = IOACCEL2_IU_TYPE;
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use_sg = scsi_dma_map(cmd);
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if (use_sg < 0)
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return use_sg;
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if (use_sg) {
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BUG_ON(use_sg > IOACCEL2_MAXSGENTRIES);
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curr_sg = cp->sg;
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scsi_for_each_sg(cmd, sg, use_sg, i) {
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addr64 = (u64) sg_dma_address(sg);
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len = sg_dma_len(sg);
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total_len += len;
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curr_sg->address = cpu_to_le64(addr64);
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curr_sg->length = cpu_to_le32(len);
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curr_sg->reserved[0] = 0;
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curr_sg->reserved[1] = 0;
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curr_sg->reserved[2] = 0;
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curr_sg->chain_indicator = 0;
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curr_sg++;
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}
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switch (cmd->sc_data_direction) {
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case DMA_TO_DEVICE:
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cp->direction = IOACCEL2_DIR_DATA_OUT;
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break;
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case DMA_FROM_DEVICE:
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cp->direction = IOACCEL2_DIR_DATA_IN;
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break;
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case DMA_NONE:
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cp->direction = IOACCEL2_DIR_NO_DATA;
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break;
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default:
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dev_err(&h->pdev->dev, "unknown data direction: %d\n",
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cmd->sc_data_direction);
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BUG();
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break;
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}
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} else {
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cp->direction = IOACCEL2_DIR_NO_DATA;
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}
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cp->scsi_nexus = ioaccel_handle;
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cp->Tag.lower = (c->cmdindex << DIRECT_LOOKUP_SHIFT) |
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DIRECT_LOOKUP_BIT;
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memcpy(cp->cdb, cdb, sizeof(cp->cdb));
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memset(cp->cciss_lun, 0, sizeof(cp->cciss_lun));
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cp->cmd_priority_task_attr = 0;
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/* fill in sg elements */
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cp->sg_count = (u8) use_sg;
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cp->data_len = cpu_to_le32(total_len);
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cp->err_ptr = cpu_to_le64(c->busaddr +
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offsetof(struct io_accel2_cmd, error_data));
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cp->err_len = cpu_to_le32((u32) sizeof(cp->error_data));
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enqueue_cmd_and_start_io(h, c);
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return 0;
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}
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/*
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* Queue a command to the correct I/O accelerator path.
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*/
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static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
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struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
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u8 *scsi3addr)
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{
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if (h->transMethod & CFGTBL_Trans_io_accel1)
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return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
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cdb, cdb_len, scsi3addr);
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else
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return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
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cdb, cdb_len, scsi3addr);
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}
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/*
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* Attempt to perform offload RAID mapping for a logical volume I/O.
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*/
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@ -4251,7 +4531,8 @@ static inline void finish_cmd(struct CommandList *c)
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spin_unlock_irqrestore(&h->lock, flags);
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dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
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if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI))
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if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
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|| c->cmd_type == CMD_IOACCEL2))
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complete_scsi_command(c);
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else if (c->cmd_type == CMD_IOCTL_PEND)
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complete(c->waiting);
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@ -5974,6 +6255,12 @@ static void hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
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access = SA5_ioaccel_mode1_access;
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writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
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writel(4, &h->cfgtable->HostWrite.CoalIntCount);
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} else {
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if (trans_support & CFGTBL_Trans_io_accel2) {
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access = SA5_ioaccel_mode2_access;
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writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
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writel(4, &h->cfgtable->HostWrite.CoalIntCount);
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}
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}
|
||||
writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
|
||||
hpsa_wait_for_mode_change_ack(h);
|
||||
|
||||
@ -282,6 +282,18 @@ static void SA5_submit_command(struct ctlr_info *h,
|
||||
(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
|
||||
}
|
||||
|
||||
static void SA5_submit_command_ioaccel2(struct ctlr_info *h,
|
||||
struct CommandList *c)
|
||||
{
|
||||
dev_dbg(&h->pdev->dev, "Sending %x, tag = %x\n", c->busaddr,
|
||||
c->Header.Tag.lower);
|
||||
if (c->cmd_type == CMD_IOACCEL2)
|
||||
writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
|
||||
else
|
||||
writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
|
||||
(void) readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
|
||||
}
|
||||
|
||||
/*
|
||||
* This card is the opposite of the other cards.
|
||||
* 0 turns interrupts on...
|
||||
@ -475,6 +487,14 @@ static struct access_method SA5_ioaccel_mode1_access = {
|
||||
SA5_ioaccel_mode1_completed,
|
||||
};
|
||||
|
||||
static struct access_method SA5_ioaccel_mode2_access = {
|
||||
SA5_submit_command_ioaccel2,
|
||||
SA5_performant_intr_mask,
|
||||
SA5_fifo_full,
|
||||
SA5_performant_intr_pending,
|
||||
SA5_performant_completed,
|
||||
};
|
||||
|
||||
static struct access_method SA5_performant_access = {
|
||||
SA5_submit_command,
|
||||
SA5_performant_intr_mask,
|
||||
|
||||
@ -478,6 +478,7 @@ struct io_accel2_scsi_response {
|
||||
#define IOACCEL2_STATUS_SR_TASK_COMP_RES_CON 0x18
|
||||
#define IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL 0x28
|
||||
#define IOACCEL2_STATUS_SR_TASK_COMP_ABORTED 0x40
|
||||
#define IOACCEL2_STATUS_SR_IOACCEL_DISABLED 0x0E
|
||||
u8 data_present; /* low 2 bits */
|
||||
#define IOACCEL2_NO_DATAPRESENT 0x000
|
||||
#define IOACCEL2_RESPONSE_DATAPRESENT 0x001
|
||||
|
||||
Loading…
Reference in New Issue
Block a user