mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-24 12:44:11 +08:00
Merge branch 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux
Pull thermal management update from Zhang Rui:
"Specifics:
- fix a bug in Exynos thermal driver, which overwrites the hardware
trip point threshold when updating software trigger levels and
results in emergency shutdown. From: Tushar Behera.
- add thermal sensor support for Armada 375 and 38x SoCs. From
Ezequiel Garcia.
- add TMU (Thermal Management Unit) support for Exynos5260 and
Exynos5420 SoCs. From Naveen Krishna Chatradhi.
- add support for the additional digital temperature sensors in the
Intel SoCs like Bay Trail. From: Srinivas Pandruvada.
- a couple of cleanups and small fixes from Jingoo Han, Bartlomiej
Zolnierkiewicz, Geert Uytterhoeven, Jacob Pan, Paul Walmsley and
Lan,Tianyu"
* 'next' of git://git.kernel.org/pub/scm/linux/kernel/git/rzhang/linux: (21 commits)
thermal: spear: remove unnecessary OOM messages
thermal: exynos: remove unnecessary OOM messages
thermal: rcar: remove unnecessary OOM messages
thermal: armada: Support Armada 380 SoC
thermal: armada: Support Armada 375 SoC
thermal: armada: Allow to specify an 'inverted readout' sensor
thermal: armada: Pass the platform_device to init_sensor()
thermal: armada: Add generic infrastructure to handle the sensor
thermal: armada: Add infrastructure to support generic formulas
thermal: armada: Rename armada_thermal_ops struct
thermal/intel_powerclamp: add newer cpu ids
thermal: rcar: Use pm_runtime_put() i.s.o. pm_runtime_put_sync()
thermal: samsung: Only update available threshold limits
Thermal/int3403: Fix thermal hysteresis unit conversion
thermal: Intel SoC DTS thermal
thermal: samsung: Add TMU support for Exynos5260 SoCs
thermal: samsung: Add TMU support for Exynos5420 SoCs
thermal: samsung: change base_common to more meaningful base_second
thermal: samsung: replace inten_ bit fields with intclr_
thermal: offer Samsung thermal support only when ARCH_EXYNOS is defined
...
This commit is contained in:
Linus Torvalds
commit
c31c24b825
@ -1,11 +1,21 @@
|
||||
* Marvell Armada 370/XP thermal management
|
||||
* Marvell Armada 370/375/380/XP thermal management
|
||||
|
||||
Required properties:
|
||||
|
||||
- compatible: Should be set to one of the following:
|
||||
marvell,armada370-thermal
|
||||
marvell,armada375-thermal
|
||||
marvell,armada375-z1-thermal
|
||||
marvell,armada380-thermal
|
||||
marvell,armadaxp-thermal
|
||||
|
||||
Note: As the name suggests, "marvell,armada375-z1-thermal"
|
||||
applies for the SoC Z1 stepping only. On such stepping
|
||||
some quirks need to be done and the register offset differs
|
||||
from the one in the A0 stepping.
|
||||
The operating system may auto-detect the SoC stepping and
|
||||
update the compatible and register offsets at runtime.
|
||||
|
||||
- reg: Device's register space.
|
||||
Two entries are expected, see the examples below.
|
||||
The first one is required for the sensor register;
|
||||
|
||||
@ -6,16 +6,35 @@
|
||||
"samsung,exynos4412-tmu"
|
||||
"samsung,exynos4210-tmu"
|
||||
"samsung,exynos5250-tmu"
|
||||
"samsung,exynos5260-tmu"
|
||||
"samsung,exynos5420-tmu" for TMU channel 0, 1 on Exynos5420
|
||||
"samsung,exynos5420-tmu-ext-triminfo" for TMU channels 2, 3 and 4
|
||||
Exynos5420 (Must pass triminfo base and triminfo clock)
|
||||
"samsung,exynos5440-tmu"
|
||||
- interrupt-parent : The phandle for the interrupt controller
|
||||
- reg : Address range of the thermal registers. For soc's which has multiple
|
||||
instances of TMU and some registers are shared across all TMU's like
|
||||
interrupt related then 2 set of register has to supplied. First set
|
||||
belongs to each instance of TMU and second set belongs to common TMU
|
||||
registers.
|
||||
belongs to register set of TMU instance and second set belongs to
|
||||
registers shared with the TMU instance.
|
||||
|
||||
NOTE: On Exynos5420, the TRIMINFO register is misplaced for TMU
|
||||
channels 2, 3 and 4
|
||||
Use "samsung,exynos5420-tmu-ext-triminfo" in cases, there is a misplaced
|
||||
register, also provide clock to access that base.
|
||||
|
||||
TRIMINFO at 0x1006c000 contains data for TMU channel 3
|
||||
TRIMINFO at 0x100a0000 contains data for TMU channel 4
|
||||
TRIMINFO at 0x10068000 contains data for TMU channel 2
|
||||
|
||||
- interrupts : Should contain interrupt for thermal system
|
||||
- clocks : The main clock for TMU device
|
||||
- clocks : The main clocks for TMU device
|
||||
-- 1. operational clock for TMU channel
|
||||
-- 2. optional clock to access the shared registers of TMU channel
|
||||
- clock-names : Thermal system clock name
|
||||
-- "tmu_apbif" operational clock for current TMU channel
|
||||
-- "tmu_triminfo_apbif" clock to access the shared triminfo register
|
||||
for current TMU channel
|
||||
- vtmu-supply: This entry is optional and provides the regulator node supplying
|
||||
voltage to TMU. If needed this entry can be placed inside
|
||||
board/platform specific dts file.
|
||||
@ -43,6 +62,31 @@ Example 2):
|
||||
clock-names = "tmu_apbif";
|
||||
};
|
||||
|
||||
Example 3): (In case of Exynos5420 "with misplaced TRIMINFO register")
|
||||
tmu_cpu2: tmu@10068000 {
|
||||
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
||||
reg = <0x10068000 0x100>, <0x1006c000 0x4>;
|
||||
interrupts = <0 184 0>;
|
||||
clocks = <&clock 318>, <&clock 318>;
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
};
|
||||
|
||||
tmu_cpu3: tmu@1006c000 {
|
||||
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
||||
reg = <0x1006c000 0x100>, <0x100a0000 0x4>;
|
||||
interrupts = <0 185 0>;
|
||||
clocks = <&clock 318>, <&clock 319>;
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
};
|
||||
|
||||
tmu_gpu: tmu@100a0000 {
|
||||
compatible = "samsung,exynos5420-tmu-ext-triminfo";
|
||||
reg = <0x100a0000 0x100>, <0x10068000 0x4>;
|
||||
interrupts = <0 215 0>;
|
||||
clocks = <&clock 319>, <&clock 318>;
|
||||
clock-names = "tmu_apbif", "tmu_triminfo_apbif";
|
||||
};
|
||||
|
||||
Note: For multi-instance tmu each instance should have an alias correctly
|
||||
numbered in "aliases" node.
|
||||
|
||||
|
||||
@ -222,12 +222,24 @@ config ACPI_INT3403_THERMAL
|
||||
the Intel Thermal Daemon can use this information to allow the user
|
||||
to select his laptop to run without turning on the fans.
|
||||
|
||||
config INTEL_SOC_DTS_THERMAL
|
||||
tristate "Intel SoCs DTS thermal driver"
|
||||
depends on X86 && IOSF_MBI
|
||||
help
|
||||
Enable this to register Intel SoCs (e.g. Bay Trail) platform digital
|
||||
temperature sensor (DTS). These SoCs have two additional DTSs in
|
||||
addition to DTSs on CPU cores. Each DTS will be registered as a
|
||||
thermal zone. There are two trip points. One of the trip point can
|
||||
be set by user mode programs to get notifications via Linux thermal
|
||||
notification methods.The other trip is a critical trip point, which
|
||||
was set by the driver based on the TJ MAX temperature.
|
||||
|
||||
menu "Texas Instruments thermal drivers"
|
||||
source "drivers/thermal/ti-soc-thermal/Kconfig"
|
||||
endmenu
|
||||
|
||||
menu "Samsung thermal drivers"
|
||||
depends on PLAT_SAMSUNG
|
||||
depends on ARCH_EXYNOS
|
||||
source "drivers/thermal/samsung/Kconfig"
|
||||
endmenu
|
||||
|
||||
|
||||
@ -29,5 +29,6 @@ obj-$(CONFIG_IMX_THERMAL) += imx_thermal.o
|
||||
obj-$(CONFIG_DB8500_CPUFREQ_COOLING) += db8500_cpufreq_cooling.o
|
||||
obj-$(CONFIG_INTEL_POWERCLAMP) += intel_powerclamp.o
|
||||
obj-$(CONFIG_X86_PKG_TEMP_THERMAL) += x86_pkg_temp_thermal.o
|
||||
obj-$(CONFIG_INTEL_SOC_DTS_THERMAL) += intel_soc_dts_thermal.o
|
||||
obj-$(CONFIG_TI_SOC_THERMAL) += ti-soc-thermal/
|
||||
obj-$(CONFIG_ACPI_INT3403_THERMAL) += int3403_thermal.o
|
||||
|
||||
@ -24,10 +24,7 @@
|
||||
#include <linux/of_device.h>
|
||||
#include <linux/thermal.h>
|
||||
|
||||
#define THERMAL_VALID_OFFSET 9
|
||||
#define THERMAL_VALID_MASK 0x1
|
||||
#define THERMAL_TEMP_OFFSET 10
|
||||
#define THERMAL_TEMP_MASK 0x1ff
|
||||
|
||||
/* Thermal Manager Control and Status Register */
|
||||
#define PMU_TDC0_SW_RST_MASK (0x1 << 1)
|
||||
@ -38,24 +35,47 @@
|
||||
#define PMU_TDC0_OTF_CAL_MASK (0x1 << 30)
|
||||
#define PMU_TDC0_START_CAL_MASK (0x1 << 25)
|
||||
|
||||
struct armada_thermal_ops;
|
||||
#define A375_Z1_CAL_RESET_LSB 0x8011e214
|
||||
#define A375_Z1_CAL_RESET_MSB 0x30a88019
|
||||
#define A375_Z1_WORKAROUND_BIT BIT(9)
|
||||
|
||||
#define A375_UNIT_CONTROL_SHIFT 27
|
||||
#define A375_UNIT_CONTROL_MASK 0x7
|
||||
#define A375_READOUT_INVERT BIT(15)
|
||||
#define A375_HW_RESETn BIT(8)
|
||||
#define A380_HW_RESET BIT(8)
|
||||
|
||||
struct armada_thermal_data;
|
||||
|
||||
/* Marvell EBU Thermal Sensor Dev Structure */
|
||||
struct armada_thermal_priv {
|
||||
void __iomem *sensor;
|
||||
void __iomem *control;
|
||||
struct armada_thermal_ops *ops;
|
||||
struct armada_thermal_data *data;
|
||||
};
|
||||
|
||||
struct armada_thermal_ops {
|
||||
struct armada_thermal_data {
|
||||
/* Initialize the sensor */
|
||||
void (*init_sensor)(struct armada_thermal_priv *);
|
||||
void (*init_sensor)(struct platform_device *pdev,
|
||||
struct armada_thermal_priv *);
|
||||
|
||||
/* Test for a valid sensor value (optional) */
|
||||
bool (*is_valid)(struct armada_thermal_priv *);
|
||||
|
||||
/* Formula coeficients: temp = (b + m * reg) / div */
|
||||
unsigned long coef_b;
|
||||
unsigned long coef_m;
|
||||
unsigned long coef_div;
|
||||
bool inverted;
|
||||
|
||||
/* Register shift and mask to access the sensor temperature */
|
||||
unsigned int temp_shift;
|
||||
unsigned int temp_mask;
|
||||
unsigned int is_valid_shift;
|
||||
};
|
||||
|
||||
static void armadaxp_init_sensor(struct armada_thermal_priv *priv)
|
||||
static void armadaxp_init_sensor(struct platform_device *pdev,
|
||||
struct armada_thermal_priv *priv)
|
||||
{
|
||||
unsigned long reg;
|
||||
|
||||
@ -80,7 +100,8 @@ static void armadaxp_init_sensor(struct armada_thermal_priv *priv)
|
||||
writel(reg, priv->sensor);
|
||||
}
|
||||
|
||||
static void armada370_init_sensor(struct armada_thermal_priv *priv)
|
||||
static void armada370_init_sensor(struct platform_device *pdev,
|
||||
struct armada_thermal_priv *priv)
|
||||
{
|
||||
unsigned long reg;
|
||||
|
||||
@ -99,11 +120,54 @@ static void armada370_init_sensor(struct armada_thermal_priv *priv)
|
||||
mdelay(10);
|
||||
}
|
||||
|
||||
static void armada375_init_sensor(struct platform_device *pdev,
|
||||
struct armada_thermal_priv *priv)
|
||||
{
|
||||
unsigned long reg;
|
||||
bool quirk_needed =
|
||||
!!of_device_is_compatible(pdev->dev.of_node,
|
||||
"marvell,armada375-z1-thermal");
|
||||
|
||||
if (quirk_needed) {
|
||||
/* Ensure these registers have the default (reset) values */
|
||||
writel(A375_Z1_CAL_RESET_LSB, priv->control);
|
||||
writel(A375_Z1_CAL_RESET_MSB, priv->control + 0x4);
|
||||
}
|
||||
|
||||
reg = readl(priv->control + 4);
|
||||
reg &= ~(A375_UNIT_CONTROL_MASK << A375_UNIT_CONTROL_SHIFT);
|
||||
reg &= ~A375_READOUT_INVERT;
|
||||
reg &= ~A375_HW_RESETn;
|
||||
|
||||
if (quirk_needed)
|
||||
reg |= A375_Z1_WORKAROUND_BIT;
|
||||
|
||||
writel(reg, priv->control + 4);
|
||||
mdelay(20);
|
||||
|
||||
reg |= A375_HW_RESETn;
|
||||
writel(reg, priv->control + 4);
|
||||
mdelay(50);
|
||||
}
|
||||
|
||||
static void armada380_init_sensor(struct platform_device *pdev,
|
||||
struct armada_thermal_priv *priv)
|
||||
{
|
||||
unsigned long reg = readl_relaxed(priv->control);
|
||||
|
||||
/* Reset hardware once */
|
||||
if (!(reg & A380_HW_RESET)) {
|
||||
reg |= A380_HW_RESET;
|
||||
writel(reg, priv->control);
|
||||
mdelay(10);
|
||||
}
|
||||
}
|
||||
|
||||
static bool armada_is_valid(struct armada_thermal_priv *priv)
|
||||
{
|
||||
unsigned long reg = readl_relaxed(priv->sensor);
|
||||
|
||||
return (reg >> THERMAL_VALID_OFFSET) & THERMAL_VALID_MASK;
|
||||
return (reg >> priv->data->is_valid_shift) & THERMAL_VALID_MASK;
|
||||
}
|
||||
|
||||
static int armada_get_temp(struct thermal_zone_device *thermal,
|
||||
@ -111,17 +175,27 @@ static int armada_get_temp(struct thermal_zone_device *thermal,
|
||||
{
|
||||
struct armada_thermal_priv *priv = thermal->devdata;
|
||||
unsigned long reg;
|
||||
unsigned long m, b, div;
|
||||
|
||||
/* Valid check */
|
||||
if (priv->ops->is_valid && !priv->ops->is_valid(priv)) {
|
||||
if (priv->data->is_valid && !priv->data->is_valid(priv)) {
|
||||
dev_err(&thermal->device,
|
||||
"Temperature sensor reading not valid\n");
|
||||
return -EIO;
|
||||
}
|
||||
|
||||
reg = readl_relaxed(priv->sensor);
|
||||
reg = (reg >> THERMAL_TEMP_OFFSET) & THERMAL_TEMP_MASK;
|
||||
*temp = (3153000000UL - (10000000UL*reg)) / 13825;
|
||||
reg = (reg >> priv->data->temp_shift) & priv->data->temp_mask;
|
||||
|
||||
/* Get formula coeficients */
|
||||
b = priv->data->coef_b;
|
||||
m = priv->data->coef_m;
|
||||
div = priv->data->coef_div;
|
||||
|
||||
if (priv->data->inverted)
|
||||
*temp = ((m * reg) - b) / div;
|
||||
else
|
||||
*temp = (b - (m * reg)) / div;
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -129,23 +203,69 @@ static struct thermal_zone_device_ops ops = {
|
||||
.get_temp = armada_get_temp,
|
||||
};
|
||||
|
||||
static const struct armada_thermal_ops armadaxp_ops = {
|
||||
static const struct armada_thermal_data armadaxp_data = {
|
||||
.init_sensor = armadaxp_init_sensor,
|
||||
.temp_shift = 10,
|
||||
.temp_mask = 0x1ff,
|
||||
.coef_b = 3153000000UL,
|
||||
.coef_m = 10000000UL,
|
||||
.coef_div = 13825,
|
||||
};
|
||||
|
||||
static const struct armada_thermal_ops armada370_ops = {
|
||||
static const struct armada_thermal_data armada370_data = {
|
||||
.is_valid = armada_is_valid,
|
||||
.init_sensor = armada370_init_sensor,
|
||||
.is_valid_shift = 9,
|
||||
.temp_shift = 10,
|
||||
.temp_mask = 0x1ff,
|
||||
.coef_b = 3153000000UL,
|
||||
.coef_m = 10000000UL,
|
||||
.coef_div = 13825,
|
||||
};
|
||||
|
||||
static const struct armada_thermal_data armada375_data = {
|
||||
.is_valid = armada_is_valid,
|
||||
.init_sensor = armada375_init_sensor,
|
||||
.is_valid_shift = 10,
|
||||
.temp_shift = 0,
|
||||
.temp_mask = 0x1ff,
|
||||
.coef_b = 3171900000UL,
|
||||
.coef_m = 10000000UL,
|
||||
.coef_div = 13616,
|
||||
};
|
||||
|
||||
static const struct armada_thermal_data armada380_data = {
|
||||
.is_valid = armada_is_valid,
|
||||
.init_sensor = armada380_init_sensor,
|
||||
.is_valid_shift = 10,
|
||||
.temp_shift = 0,
|
||||
.temp_mask = 0x3ff,
|
||||
.coef_b = 1169498786UL,
|
||||
.coef_m = 2000000UL,
|
||||
.coef_div = 4289,
|
||||
.inverted = true,
|
||||
};
|
||||
|
||||
static const struct of_device_id armada_thermal_id_table[] = {
|
||||
{
|
||||
.compatible = "marvell,armadaxp-thermal",
|
||||
.data = &armadaxp_ops,
|
||||
.data = &armadaxp_data,
|
||||
},
|
||||
{
|
||||
.compatible = "marvell,armada370-thermal",
|
||||
.data = &armada370_ops,
|
||||
.data = &armada370_data,
|
||||
},
|
||||
{
|
||||
.compatible = "marvell,armada375-thermal",
|
||||
.data = &armada375_data,
|
||||
},
|
||||
{
|
||||
.compatible = "marvell,armada375-z1-thermal",
|
||||
.data = &armada375_data,
|
||||
},
|
||||
{
|
||||
.compatible = "marvell,armada380-thermal",
|
||||
.data = &armada380_data,
|
||||
},
|
||||
{
|
||||
/* sentinel */
|
||||
@ -178,8 +298,8 @@ static int armada_thermal_probe(struct platform_device *pdev)
|
||||
if (IS_ERR(priv->control))
|
||||
return PTR_ERR(priv->control);
|
||||
|
||||
priv->ops = (struct armada_thermal_ops *)match->data;
|
||||
priv->ops->init_sensor(priv);
|
||||
priv->data = (struct armada_thermal_data *)match->data;
|
||||
priv->data->init_sensor(pdev, priv);
|
||||
|
||||
thermal = thermal_zone_device_register("armada_thermal", 0, 0,
|
||||
priv, &ops, NULL, 0, 0);
|
||||
|
||||
@ -62,7 +62,13 @@ static int sys_get_trip_hyst(struct thermal_zone_device *tzone,
|
||||
if (ACPI_FAILURE(status))
|
||||
return -EIO;
|
||||
|
||||
*temp = DECI_KELVIN_TO_MILLI_CELSIUS(hyst, KELVIN_OFFSET);
|
||||
/*
|
||||
* Thermal hysteresis represents a temperature difference.
|
||||
* Kelvin and Celsius have same degree size. So the
|
||||
* conversion here between tenths of degree Kelvin unit
|
||||
* and Milli-Celsius unit is just to multiply 100.
|
||||
*/
|
||||
*temp = hyst * 100;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
@ -681,8 +681,10 @@ static const struct x86_cpu_id intel_powerclamp_ids[] = {
|
||||
{ X86_VENDOR_INTEL, 6, 0x2d},
|
||||
{ X86_VENDOR_INTEL, 6, 0x2e},
|
||||
{ X86_VENDOR_INTEL, 6, 0x2f},
|
||||
{ X86_VENDOR_INTEL, 6, 0x37},
|
||||
{ X86_VENDOR_INTEL, 6, 0x3a},
|
||||
{ X86_VENDOR_INTEL, 6, 0x3c},
|
||||
{ X86_VENDOR_INTEL, 6, 0x3d},
|
||||
{ X86_VENDOR_INTEL, 6, 0x3e},
|
||||
{ X86_VENDOR_INTEL, 6, 0x3f},
|
||||
{ X86_VENDOR_INTEL, 6, 0x45},
|
||||
|
||||
479
drivers/thermal/intel_soc_dts_thermal.c
Normal file
479
drivers/thermal/intel_soc_dts_thermal.c
Normal file
@ -0,0 +1,479 @@
|
||||
/*
|
||||
* intel_soc_dts_thermal.c
|
||||
* Copyright (c) 2014, Intel Corporation.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms and conditions of the GNU General Public License,
|
||||
* version 2, as published by the Free Software Foundation.
|
||||
*
|
||||
* This program is distributed in the hope it will be useful, but WITHOUT
|
||||
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
|
||||
* more details.
|
||||
*
|
||||
*/
|
||||
|
||||
#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
|
||||
|
||||
#include <linux/module.h>
|
||||
#include <linux/slab.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/thermal.h>
|
||||
#include <asm/cpu_device_id.h>
|
||||
#include <asm/iosf_mbi.h>
|
||||
|
||||
#define SOC_DTS_OFFSET_ENABLE 0xB0
|
||||
#define SOC_DTS_OFFSET_TEMP 0xB1
|
||||
|
||||
#define SOC_DTS_OFFSET_PTPS 0xB2
|
||||
#define SOC_DTS_OFFSET_PTTS 0xB3
|
||||
#define SOC_DTS_OFFSET_PTTSS 0xB4
|
||||
#define SOC_DTS_OFFSET_PTMC 0x80
|
||||
#define SOC_DTS_TE_AUX0 0xB5
|
||||
#define SOC_DTS_TE_AUX1 0xB6
|
||||
|
||||
#define SOC_DTS_AUX0_ENABLE_BIT BIT(0)
|
||||
#define SOC_DTS_AUX1_ENABLE_BIT BIT(1)
|
||||
#define SOC_DTS_CPU_MODULE0_ENABLE_BIT BIT(16)
|
||||
#define SOC_DTS_CPU_MODULE1_ENABLE_BIT BIT(17)
|
||||
#define SOC_DTS_TE_SCI_ENABLE BIT(9)
|
||||
#define SOC_DTS_TE_SMI_ENABLE BIT(10)
|
||||
#define SOC_DTS_TE_MSI_ENABLE BIT(11)
|
||||
#define SOC_DTS_TE_APICA_ENABLE BIT(14)
|
||||
#define SOC_DTS_PTMC_APIC_DEASSERT_BIT BIT(4)
|
||||
|
||||
/* DTS encoding for TJ MAX temperature */
|
||||
#define SOC_DTS_TJMAX_ENCODING 0x7F
|
||||
|
||||
/* IRQ 86 is a fixed APIC interrupt for BYT DTS Aux threshold notifications */
|
||||
#define BYT_SOC_DTS_APIC_IRQ 86
|
||||
|
||||
/* Only 2 out of 4 is allowed for OSPM */
|
||||
#define SOC_MAX_DTS_TRIPS 2
|
||||
|
||||
/* Mask for two trips in status bits */
|
||||
#define SOC_DTS_TRIP_MASK 0x03
|
||||
|
||||
/* DTS0 and DTS 1 */
|
||||
#define SOC_MAX_DTS_SENSORS 2
|
||||
|
||||
#define CRITICAL_OFFSET_FROM_TJ_MAX 5000
|
||||
|
||||
struct soc_sensor_entry {
|
||||
int id;
|
||||
u32 tj_max;
|
||||
u32 temp_mask;
|
||||
u32 temp_shift;
|
||||
u32 store_status;
|
||||
struct thermal_zone_device *tzone;
|
||||
};
|
||||
|
||||
static struct soc_sensor_entry *soc_dts[SOC_MAX_DTS_SENSORS];
|
||||
|
||||
static int crit_offset = CRITICAL_OFFSET_FROM_TJ_MAX;
|
||||
module_param(crit_offset, int, 0644);
|
||||
MODULE_PARM_DESC(crit_offset,
|
||||
"Critical Temperature offset from tj max in millidegree Celsius.");
|
||||
|
||||
static DEFINE_MUTEX(aux_update_mutex);
|
||||
static spinlock_t intr_notify_lock;
|
||||
static int soc_dts_thres_irq;
|
||||
|
||||
static int get_tj_max(u32 *tj_max)
|
||||
{
|
||||
u32 eax, edx;
|
||||
u32 val;
|
||||
int err;
|
||||
|
||||
err = rdmsr_safe(MSR_IA32_TEMPERATURE_TARGET, &eax, &edx);
|
||||
if (err)
|
||||
goto err_ret;
|
||||
else {
|
||||
val = (eax >> 16) & 0xff;
|
||||
if (val)
|
||||
*tj_max = val * 1000;
|
||||
else {
|
||||
err = -EINVAL;
|
||||
goto err_ret;
|
||||
}
|
||||
}
|
||||
|
||||
return 0;
|
||||
err_ret:
|
||||
*tj_max = 0;
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static int sys_get_trip_temp(struct thermal_zone_device *tzd,
|
||||
int trip, unsigned long *temp)
|
||||
{
|
||||
int status;
|
||||
u32 out;
|
||||
struct soc_sensor_entry *aux_entry;
|
||||
|
||||
aux_entry = tzd->devdata;
|
||||
|
||||
if (!trip) {
|
||||
/* Just return the critical temp */
|
||||
*temp = aux_entry->tj_max - crit_offset;
|
||||
return 0;
|
||||
}
|
||||
|
||||
mutex_lock(&aux_update_mutex);
|
||||
status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
|
||||
SOC_DTS_OFFSET_PTPS, &out);
|
||||
mutex_unlock(&aux_update_mutex);
|
||||
if (status)
|
||||
return status;
|
||||
|
||||
out = (out >> (trip * 8)) & SOC_DTS_TJMAX_ENCODING;
|
||||
|
||||
if (!out)
|
||||
*temp = 0;
|
||||
else
|
||||
*temp = aux_entry->tj_max - out * 1000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int update_trip_temp(struct soc_sensor_entry *aux_entry,
|
||||
int thres_index, unsigned long temp)
|
||||
{
|
||||
int status;
|
||||
u32 temp_out;
|
||||
u32 out;
|
||||
u32 store_ptps;
|
||||
u32 store_ptmc;
|
||||
u32 store_te_out;
|
||||
u32 te_out;
|
||||
|
||||
u32 int_enable_bit = SOC_DTS_TE_APICA_ENABLE |
|
||||
SOC_DTS_TE_MSI_ENABLE;
|
||||
|
||||
temp_out = (aux_entry->tj_max - temp) / 1000;
|
||||
|
||||
status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
|
||||
SOC_DTS_OFFSET_PTPS, &store_ptps);
|
||||
if (status)
|
||||
return status;
|
||||
|
||||
out = (store_ptps & ~(0xFF << (thres_index * 8)));
|
||||
out |= (temp_out & 0xFF) << (thres_index * 8);
|
||||
status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
|
||||
SOC_DTS_OFFSET_PTPS, out);
|
||||
if (status)
|
||||
return status;
|
||||
pr_debug("update_trip_temp PTPS = %x\n", out);
|
||||
status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
|
||||
SOC_DTS_OFFSET_PTMC, &out);
|
||||
if (status)
|
||||
goto err_restore_ptps;
|
||||
|
||||
store_ptmc = out;
|
||||
|
||||
status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
|
||||
SOC_DTS_TE_AUX0 + thres_index,
|
||||
&te_out);
|
||||
if (status)
|
||||
goto err_restore_ptmc;
|
||||
|
||||
store_te_out = te_out;
|
||||
|
||||
/* Enable for CPU module 0 and module 1 */
|
||||
out |= (SOC_DTS_CPU_MODULE0_ENABLE_BIT |
|
||||
SOC_DTS_CPU_MODULE1_ENABLE_BIT);
|
||||
if (temp) {
|
||||
if (thres_index)
|
||||
out |= SOC_DTS_AUX1_ENABLE_BIT;
|
||||
else
|
||||
out |= SOC_DTS_AUX0_ENABLE_BIT;
|
||||
te_out |= int_enable_bit;
|
||||
} else {
|
||||
if (thres_index)
|
||||
out &= ~SOC_DTS_AUX1_ENABLE_BIT;
|
||||
else
|
||||
out &= ~SOC_DTS_AUX0_ENABLE_BIT;
|
||||
te_out &= ~int_enable_bit;
|
||||
}
|
||||
status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
|
||||
SOC_DTS_OFFSET_PTMC, out);
|
||||
if (status)
|
||||
goto err_restore_te_out;
|
||||
|
||||
status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
|
||||
SOC_DTS_TE_AUX0 + thres_index,
|
||||
te_out);
|
||||
if (status)
|
||||
goto err_restore_te_out;
|
||||
|
||||
return 0;
|
||||
|
||||
err_restore_te_out:
|
||||
iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
|
||||
SOC_DTS_OFFSET_PTMC, store_te_out);
|
||||
err_restore_ptmc:
|
||||
iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
|
||||
SOC_DTS_OFFSET_PTMC, store_ptmc);
|
||||
err_restore_ptps:
|
||||
iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
|
||||
SOC_DTS_OFFSET_PTPS, store_ptps);
|
||||
/* Nothing we can do if restore fails */
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int sys_set_trip_temp(struct thermal_zone_device *tzd, int trip,
|
||||
unsigned long temp)
|
||||
{
|
||||
struct soc_sensor_entry *aux_entry = tzd->devdata;
|
||||
int status;
|
||||
|
||||
if (temp > (aux_entry->tj_max - crit_offset))
|
||||
return -EINVAL;
|
||||
|
||||
mutex_lock(&aux_update_mutex);
|
||||
status = update_trip_temp(tzd->devdata, trip, temp);
|
||||
mutex_unlock(&aux_update_mutex);
|
||||
|
||||
return status;
|
||||
}
|
||||
|
||||
static int sys_get_trip_type(struct thermal_zone_device *thermal,
|
||||
int trip, enum thermal_trip_type *type)
|
||||
{
|
||||
if (trip)
|
||||
*type = THERMAL_TRIP_PASSIVE;
|
||||
else
|
||||
*type = THERMAL_TRIP_CRITICAL;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int sys_get_curr_temp(struct thermal_zone_device *tzd,
|
||||
unsigned long *temp)
|
||||
{
|
||||
int status;
|
||||
u32 out;
|
||||
struct soc_sensor_entry *aux_entry;
|
||||
|
||||
aux_entry = tzd->devdata;
|
||||
|
||||
status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
|
||||
SOC_DTS_OFFSET_TEMP, &out);
|
||||
if (status)
|
||||
return status;
|
||||
|
||||
out = (out & aux_entry->temp_mask) >> aux_entry->temp_shift;
|
||||
out -= SOC_DTS_TJMAX_ENCODING;
|
||||
*temp = aux_entry->tj_max - out * 1000;
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct thermal_zone_device_ops tzone_ops = {
|
||||
.get_temp = sys_get_curr_temp,
|
||||
.get_trip_temp = sys_get_trip_temp,
|
||||
.get_trip_type = sys_get_trip_type,
|
||||
.set_trip_temp = sys_set_trip_temp,
|
||||
};
|
||||
|
||||
static void free_soc_dts(struct soc_sensor_entry *aux_entry)
|
||||
{
|
||||
if (aux_entry) {
|
||||
iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
|
||||
SOC_DTS_OFFSET_ENABLE, aux_entry->store_status);
|
||||
thermal_zone_device_unregister(aux_entry->tzone);
|
||||
kfree(aux_entry);
|
||||
}
|
||||
}
|
||||
|
||||
static int soc_dts_enable(int id)
|
||||
{
|
||||
u32 out;
|
||||
int ret;
|
||||
|
||||
ret = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
|
||||
SOC_DTS_OFFSET_ENABLE, &out);
|
||||
if (ret)
|
||||
return ret;
|
||||
|
||||
if (!(out & BIT(id))) {
|
||||
out |= BIT(id);
|
||||
ret = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
|
||||
SOC_DTS_OFFSET_ENABLE, out);
|
||||
if (ret)
|
||||
return ret;
|
||||
}
|
||||
|
||||
return ret;
|
||||
}
|
||||
|
||||
static struct soc_sensor_entry *alloc_soc_dts(int id, u32 tj_max)
|
||||
{
|
||||
struct soc_sensor_entry *aux_entry;
|
||||
char name[10];
|
||||
int err;
|
||||
|
||||
aux_entry = kzalloc(sizeof(*aux_entry), GFP_KERNEL);
|
||||
if (!aux_entry) {
|
||||
err = -ENOMEM;
|
||||
return ERR_PTR(-ENOMEM);
|
||||
}
|
||||
|
||||
/* Store status to restor on exit */
|
||||
err = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
|
||||
SOC_DTS_OFFSET_ENABLE,
|
||||
&aux_entry->store_status);
|
||||
if (err)
|
||||
goto err_ret;
|
||||
|
||||
aux_entry->id = id;
|
||||
aux_entry->tj_max = tj_max;
|
||||
aux_entry->temp_mask = 0x00FF << (id * 8);
|
||||
aux_entry->temp_shift = id * 8;
|
||||
snprintf(name, sizeof(name), "soc_dts%d", id);
|
||||
aux_entry->tzone = thermal_zone_device_register(name,
|
||||
SOC_MAX_DTS_TRIPS,
|
||||
0x02,
|
||||
aux_entry, &tzone_ops, NULL, 0, 0);
|
||||
if (IS_ERR(aux_entry->tzone)) {
|
||||
err = PTR_ERR(aux_entry->tzone);
|
||||
goto err_ret;
|
||||
}
|
||||
|
||||
err = soc_dts_enable(id);
|
||||
if (err)
|
||||
goto err_aux_status;
|
||||
|
||||
return aux_entry;
|
||||
|
||||
err_aux_status:
|
||||
thermal_zone_device_unregister(aux_entry->tzone);
|
||||
err_ret:
|
||||
kfree(aux_entry);
|
||||
return ERR_PTR(err);
|
||||
}
|
||||
|
||||
static void proc_thermal_interrupt(void)
|
||||
{
|
||||
u32 sticky_out;
|
||||
int status;
|
||||
u32 ptmc_out;
|
||||
|
||||
/* Clear APIC interrupt */
|
||||
status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
|
||||
SOC_DTS_OFFSET_PTMC, &ptmc_out);
|
||||
|
||||
ptmc_out |= SOC_DTS_PTMC_APIC_DEASSERT_BIT;
|
||||
status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
|
||||
SOC_DTS_OFFSET_PTMC, ptmc_out);
|
||||
|
||||
/* Read status here */
|
||||
status = iosf_mbi_read(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_READ,
|
||||
SOC_DTS_OFFSET_PTTSS, &sticky_out);
|
||||
pr_debug("status %d PTTSS %x\n", status, sticky_out);
|
||||
if (sticky_out & SOC_DTS_TRIP_MASK) {
|
||||
int i;
|
||||
/* reset sticky bit */
|
||||
status = iosf_mbi_write(BT_MBI_UNIT_PMC, BT_MBI_BUNIT_WRITE,
|
||||
SOC_DTS_OFFSET_PTTSS, sticky_out);
|
||||
for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
|
||||
pr_debug("TZD update for zone %d\n", i);
|
||||
thermal_zone_device_update(soc_dts[i]->tzone);
|
||||
}
|
||||
}
|
||||
|
||||
}
|
||||
|
||||
static irqreturn_t soc_irq_thread_fn(int irq, void *dev_data)
|
||||
{
|
||||
unsigned long flags;
|
||||
|
||||
spin_lock_irqsave(&intr_notify_lock, flags);
|
||||
proc_thermal_interrupt();
|
||||
spin_unlock_irqrestore(&intr_notify_lock, flags);
|
||||
pr_debug("proc_thermal_interrupt\n");
|
||||
|
||||
return IRQ_HANDLED;
|
||||
}
|
||||
|
||||
static const struct x86_cpu_id soc_thermal_ids[] = {
|
||||
{ X86_VENDOR_INTEL, X86_FAMILY_ANY, 0x37, 0, BYT_SOC_DTS_APIC_IRQ},
|
||||
{}
|
||||
};
|
||||
MODULE_DEVICE_TABLE(x86cpu, soc_thermal_ids);
|
||||
|
||||
static int __init intel_soc_thermal_init(void)
|
||||
{
|
||||
u32 tj_max;
|
||||
int err = 0;
|
||||
int i;
|
||||
const struct x86_cpu_id *match_cpu;
|
||||
|
||||
match_cpu = x86_match_cpu(soc_thermal_ids);
|
||||
if (!match_cpu)
|
||||
return -ENODEV;
|
||||
|
||||
if (get_tj_max(&tj_max))
|
||||
return -EINVAL;
|
||||
|
||||
for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
|
||||
soc_dts[i] = alloc_soc_dts(i, tj_max);
|
||||
if (IS_ERR(soc_dts[i])) {
|
||||
err = PTR_ERR(soc_dts[i]);
|
||||
goto err_free;
|
||||
}
|
||||
}
|
||||
|
||||
spin_lock_init(&intr_notify_lock);
|
||||
|
||||
soc_dts_thres_irq = (int)match_cpu->driver_data;
|
||||
|
||||
err = request_threaded_irq(soc_dts_thres_irq, NULL,
|
||||
soc_irq_thread_fn,
|
||||
IRQF_TRIGGER_RISING | IRQF_ONESHOT,
|
||||
"soc_dts", soc_dts);
|
||||
if (err) {
|
||||
pr_err("request_threaded_irq ret %d\n", err);
|
||||
goto err_free;
|
||||
}
|
||||
|
||||
for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i) {
|
||||
err = update_trip_temp(soc_dts[i], 0, tj_max - crit_offset);
|
||||
if (err)
|
||||
goto err_trip_temp;
|
||||
}
|
||||
|
||||
return 0;
|
||||
|
||||
err_trip_temp:
|
||||
i = SOC_MAX_DTS_SENSORS;
|
||||
free_irq(soc_dts_thres_irq, soc_dts);
|
||||
err_free:
|
||||
while (--i >= 0)
|
||||
free_soc_dts(soc_dts[i]);
|
||||
|
||||
return err;
|
||||
}
|
||||
|
||||
static void __exit intel_soc_thermal_exit(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i)
|
||||
update_trip_temp(soc_dts[i], 0, 0);
|
||||
|
||||
free_irq(soc_dts_thres_irq, soc_dts);
|
||||
|
||||
for (i = 0; i < SOC_MAX_DTS_SENSORS; ++i)
|
||||
free_soc_dts(soc_dts[i]);
|
||||
|
||||
}
|
||||
|
||||
module_init(intel_soc_thermal_init)
|
||||
module_exit(intel_soc_thermal_exit)
|
||||
|
||||
MODULE_DESCRIPTION("Intel SoC DTS Thermal Driver");
|
||||
MODULE_AUTHOR("Srinivas Pandruvada <srinivas.pandruvada@linux.intel.com>");
|
||||
MODULE_LICENSE("GPL v2");
|
||||
@ -374,10 +374,8 @@ static int rcar_thermal_probe(struct platform_device *pdev)
|
||||
int idle = IDLE_INTERVAL;
|
||||
|
||||
common = devm_kzalloc(dev, sizeof(*common), GFP_KERNEL);
|
||||
if (!common) {
|
||||
dev_err(dev, "Could not allocate common\n");
|
||||
if (!common)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
INIT_LIST_HEAD(&common->head);
|
||||
spin_lock_init(&common->lock);
|
||||
@ -423,7 +421,6 @@ static int rcar_thermal_probe(struct platform_device *pdev)
|
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv) {
|
||||
dev_err(dev, "Could not allocate priv\n");
|
||||
ret = -ENOMEM;
|
||||
goto error_unregister;
|
||||
}
|
||||
@ -470,7 +467,7 @@ error_unregister:
|
||||
rcar_thermal_irq_disable(priv);
|
||||
}
|
||||
|
||||
pm_runtime_put_sync(dev);
|
||||
pm_runtime_put(dev);
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
return ret;
|
||||
@ -488,7 +485,7 @@ static int rcar_thermal_remove(struct platform_device *pdev)
|
||||
rcar_thermal_irq_disable(priv);
|
||||
}
|
||||
|
||||
pm_runtime_put_sync(dev);
|
||||
pm_runtime_put(dev);
|
||||
pm_runtime_disable(dev);
|
||||
|
||||
return 0;
|
||||
|
||||
@ -41,12 +41,13 @@
|
||||
* @id: identifier of the one instance of the TMU controller.
|
||||
* @pdata: pointer to the tmu platform/configuration data
|
||||
* @base: base address of the single instance of the TMU controller.
|
||||
* @base_common: base address of the common registers of the TMU controller.
|
||||
* @base_second: base address of the common registers of the TMU controller.
|
||||
* @irq: irq number of the TMU controller.
|
||||
* @soc: id of the SOC type.
|
||||
* @irq_work: pointer to the irq work structure.
|
||||
* @lock: lock to implement synchronization.
|
||||
* @clk: pointer to the clock structure.
|
||||
* @clk_sec: pointer to the clock structure for accessing the base_second.
|
||||
* @temp_error1: fused value of the first point trim.
|
||||
* @temp_error2: fused value of the second point trim.
|
||||
* @regulator: pointer to the TMU regulator structure.
|
||||
@ -56,12 +57,12 @@ struct exynos_tmu_data {
|
||||
int id;
|
||||
struct exynos_tmu_platform_data *pdata;
|
||||
void __iomem *base;
|
||||
void __iomem *base_common;
|
||||
void __iomem *base_second;
|
||||
int irq;
|
||||
enum soc_type soc;
|
||||
struct work_struct irq_work;
|
||||
struct mutex lock;
|
||||
struct clk *clk;
|
||||
struct clk *clk, *clk_sec;
|
||||
u8 temp_error1, temp_error2;
|
||||
struct regulator *regulator;
|
||||
struct thermal_sensor_conf *reg_conf;
|
||||
@ -152,6 +153,8 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
|
||||
|
||||
mutex_lock(&data->lock);
|
||||
clk_enable(data->clk);
|
||||
if (!IS_ERR(data->clk_sec))
|
||||
clk_enable(data->clk_sec);
|
||||
|
||||
if (TMU_SUPPORTS(pdata, READY_STATUS)) {
|
||||
status = readb(data->base + reg->tmu_status);
|
||||
@ -186,7 +189,12 @@ static int exynos_tmu_initialize(struct platform_device *pdev)
|
||||
EXYNOS5440_EFUSE_SWAP_OFFSET + reg->triminfo_data);
|
||||
}
|
||||
} else {
|
||||
trim_info = readl(data->base + reg->triminfo_data);
|
||||
/* On exynos5420 the triminfo register is in the shared space */
|
||||
if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO)
|
||||
trim_info = readl(data->base_second +
|
||||
reg->triminfo_data);
|
||||
else
|
||||
trim_info = readl(data->base + reg->triminfo_data);
|
||||
}
|
||||
data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK;
|
||||
data->temp_error2 = ((trim_info >> reg->triminfo_85_shift) &
|
||||
@ -225,6 +233,8 @@ skip_calib_data:
|
||||
trigger_levs++;
|
||||
}
|
||||
|
||||
rising_threshold = readl(data->base + reg->threshold_th0);
|
||||
|
||||
if (data->soc == SOC_ARCH_EXYNOS4210) {
|
||||
/* Write temperature code for threshold */
|
||||
threshold_code = temp_to_code(data, pdata->threshold);
|
||||
@ -238,7 +248,7 @@ skip_calib_data:
|
||||
writeb(pdata->trigger_levels[i], data->base +
|
||||
reg->threshold_th0 + i * sizeof(reg->threshold_th0));
|
||||
|
||||
writel(reg->inten_rise_mask, data->base + reg->tmu_intclear);
|
||||
writel(reg->intclr_rise_mask, data->base + reg->tmu_intclear);
|
||||
} else {
|
||||
/* Write temperature code for rising and falling threshold */
|
||||
for (i = 0;
|
||||
@ -249,6 +259,7 @@ skip_calib_data:
|
||||
ret = threshold_code;
|
||||
goto out;
|
||||
}
|
||||
rising_threshold &= ~(0xff << 8 * i);
|
||||
rising_threshold |= threshold_code << 8 * i;
|
||||
if (pdata->threshold_falling) {
|
||||
threshold_code = temp_to_code(data,
|
||||
@ -265,8 +276,8 @@ skip_calib_data:
|
||||
writel(falling_threshold,
|
||||
data->base + reg->threshold_th1);
|
||||
|
||||
writel((reg->inten_rise_mask << reg->inten_rise_shift) |
|
||||
(reg->inten_fall_mask << reg->inten_fall_shift),
|
||||
writel((reg->intclr_rise_mask << reg->intclr_rise_shift) |
|
||||
(reg->intclr_fall_mask << reg->intclr_fall_shift),
|
||||
data->base + reg->tmu_intclear);
|
||||
|
||||
/* if last threshold limit is also present */
|
||||
@ -281,6 +292,7 @@ skip_calib_data:
|
||||
}
|
||||
if (i == EXYNOS_MAX_TRIGGER_PER_REG - 1) {
|
||||
/* 1-4 level to be assigned in th0 reg */
|
||||
rising_threshold &= ~(0xff << 8 * i);
|
||||
rising_threshold |= threshold_code << 8 * i;
|
||||
writel(rising_threshold,
|
||||
data->base + reg->threshold_th0);
|
||||
@ -298,10 +310,12 @@ skip_calib_data:
|
||||
}
|
||||
/*Clear the PMIN in the common TMU register*/
|
||||
if (reg->tmu_pmin && !data->id)
|
||||
writel(0, data->base_common + reg->tmu_pmin);
|
||||
writel(0, data->base_second + reg->tmu_pmin);
|
||||
out:
|
||||
clk_disable(data->clk);
|
||||
mutex_unlock(&data->lock);
|
||||
if (!IS_ERR(data->clk_sec))
|
||||
clk_disable(data->clk_sec);
|
||||
|
||||
return ret;
|
||||
}
|
||||
@ -453,12 +467,16 @@ static void exynos_tmu_work(struct work_struct *work)
|
||||
const struct exynos_tmu_registers *reg = pdata->registers;
|
||||
unsigned int val_irq, val_type;
|
||||
|
||||
if (!IS_ERR(data->clk_sec))
|
||||
clk_enable(data->clk_sec);
|
||||
/* Find which sensor generated this interrupt */
|
||||
if (reg->tmu_irqstatus) {
|
||||
val_type = readl(data->base_common + reg->tmu_irqstatus);
|
||||
val_type = readl(data->base_second + reg->tmu_irqstatus);
|
||||
if (!((val_type >> data->id) & 0x1))
|
||||
goto out;
|
||||
}
|
||||
if (!IS_ERR(data->clk_sec))
|
||||
clk_disable(data->clk_sec);
|
||||
|
||||
exynos_report_trigger(data->reg_conf);
|
||||
mutex_lock(&data->lock);
|
||||
@ -498,6 +516,18 @@ static const struct of_device_id exynos_tmu_match[] = {
|
||||
.compatible = "samsung,exynos5250-tmu",
|
||||
.data = (void *)EXYNOS5250_TMU_DRV_DATA,
|
||||
},
|
||||
{
|
||||
.compatible = "samsung,exynos5260-tmu",
|
||||
.data = (void *)EXYNOS5260_TMU_DRV_DATA,
|
||||
},
|
||||
{
|
||||
.compatible = "samsung,exynos5420-tmu",
|
||||
.data = (void *)EXYNOS5420_TMU_DRV_DATA,
|
||||
},
|
||||
{
|
||||
.compatible = "samsung,exynos5420-tmu-ext-triminfo",
|
||||
.data = (void *)EXYNOS5420_TMU_DRV_DATA,
|
||||
},
|
||||
{
|
||||
.compatible = "samsung,exynos5440-tmu",
|
||||
.data = (void *)EXYNOS5440_TMU_DRV_DATA,
|
||||
@ -580,7 +610,7 @@ static int exynos_map_dt_data(struct platform_device *pdev)
|
||||
* Check if the TMU shares some registers and then try to map the
|
||||
* memory of common registers.
|
||||
*/
|
||||
if (!TMU_SUPPORTS(pdata, SHARED_MEMORY))
|
||||
if (!TMU_SUPPORTS(pdata, ADDRESS_MULTIPLE))
|
||||
return 0;
|
||||
|
||||
if (of_address_to_resource(pdev->dev.of_node, 1, &res)) {
|
||||
@ -588,9 +618,9 @@ static int exynos_map_dt_data(struct platform_device *pdev)
|
||||
return -ENODEV;
|
||||
}
|
||||
|
||||
data->base_common = devm_ioremap(&pdev->dev, res.start,
|
||||
data->base_second = devm_ioremap(&pdev->dev, res.start,
|
||||
resource_size(&res));
|
||||
if (!data->base_common) {
|
||||
if (!data->base_second) {
|
||||
dev_err(&pdev->dev, "Failed to ioremap memory\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
@ -607,10 +637,8 @@ static int exynos_tmu_probe(struct platform_device *pdev)
|
||||
|
||||
data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data),
|
||||
GFP_KERNEL);
|
||||
if (!data) {
|
||||
dev_err(&pdev->dev, "Failed to allocate driver structure\n");
|
||||
if (!data)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
platform_set_drvdata(pdev, data);
|
||||
mutex_init(&data->lock);
|
||||
@ -629,13 +657,31 @@ static int exynos_tmu_probe(struct platform_device *pdev)
|
||||
return PTR_ERR(data->clk);
|
||||
}
|
||||
|
||||
data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif");
|
||||
if (IS_ERR(data->clk_sec)) {
|
||||
if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) {
|
||||
dev_err(&pdev->dev, "Failed to get triminfo clock\n");
|
||||
return PTR_ERR(data->clk_sec);
|
||||
}
|
||||
} else {
|
||||
ret = clk_prepare(data->clk_sec);
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to get clock\n");
|
||||
return ret;
|
||||
}
|
||||
}
|
||||
|
||||
ret = clk_prepare(data->clk);
|
||||
if (ret)
|
||||
return ret;
|
||||
if (ret) {
|
||||
dev_err(&pdev->dev, "Failed to get clock\n");
|
||||
goto err_clk_sec;
|
||||
}
|
||||
|
||||
if (pdata->type == SOC_ARCH_EXYNOS4210 ||
|
||||
pdata->type == SOC_ARCH_EXYNOS4412 ||
|
||||
pdata->type == SOC_ARCH_EXYNOS5250 ||
|
||||
pdata->type == SOC_ARCH_EXYNOS5260 ||
|
||||
pdata->type == SOC_ARCH_EXYNOS5420_TRIMINFO ||
|
||||
pdata->type == SOC_ARCH_EXYNOS5440)
|
||||
data->soc = pdata->type;
|
||||
else {
|
||||
@ -656,7 +702,6 @@ static int exynos_tmu_probe(struct platform_device *pdev)
|
||||
sensor_conf = devm_kzalloc(&pdev->dev,
|
||||
sizeof(struct thermal_sensor_conf), GFP_KERNEL);
|
||||
if (!sensor_conf) {
|
||||
dev_err(&pdev->dev, "Failed to allocate registration struct\n");
|
||||
ret = -ENOMEM;
|
||||
goto err_clk;
|
||||
}
|
||||
@ -704,6 +749,9 @@ static int exynos_tmu_probe(struct platform_device *pdev)
|
||||
return 0;
|
||||
err_clk:
|
||||
clk_unprepare(data->clk);
|
||||
err_clk_sec:
|
||||
if (!IS_ERR(data->clk_sec))
|
||||
clk_unprepare(data->clk_sec);
|
||||
return ret;
|
||||
}
|
||||
|
||||
@ -716,6 +764,8 @@ static int exynos_tmu_remove(struct platform_device *pdev)
|
||||
exynos_unregister_thermal(data->reg_conf);
|
||||
|
||||
clk_unprepare(data->clk);
|
||||
if (!IS_ERR(data->clk_sec))
|
||||
clk_unprepare(data->clk_sec);
|
||||
|
||||
if (!IS_ERR(data->regulator))
|
||||
regulator_disable(data->regulator);
|
||||
|
||||
@ -43,6 +43,8 @@ enum soc_type {
|
||||
SOC_ARCH_EXYNOS4210 = 1,
|
||||
SOC_ARCH_EXYNOS4412,
|
||||
SOC_ARCH_EXYNOS5250,
|
||||
SOC_ARCH_EXYNOS5260,
|
||||
SOC_ARCH_EXYNOS5420_TRIMINFO,
|
||||
SOC_ARCH_EXYNOS5440,
|
||||
};
|
||||
|
||||
@ -60,7 +62,7 @@ enum soc_type {
|
||||
* state(active/idle) can be checked.
|
||||
* TMU_SUPPORT_EMUL_TIME - This features allows to set next temp emulation
|
||||
* sample time.
|
||||
* TMU_SUPPORT_SHARED_MEMORY - This feature tells that the different TMU
|
||||
* TMU_SUPPORT_ADDRESS_MULTIPLE - This feature tells that the different TMU
|
||||
* sensors shares some common registers.
|
||||
* TMU_SUPPORT - macro to compare the above features with the supplied.
|
||||
*/
|
||||
@ -70,7 +72,7 @@ enum soc_type {
|
||||
#define TMU_SUPPORT_FALLING_TRIP BIT(3)
|
||||
#define TMU_SUPPORT_READY_STATUS BIT(4)
|
||||
#define TMU_SUPPORT_EMUL_TIME BIT(5)
|
||||
#define TMU_SUPPORT_SHARED_MEMORY BIT(6)
|
||||
#define TMU_SUPPORT_ADDRESS_MULTIPLE BIT(6)
|
||||
|
||||
#define TMU_SUPPORTS(a, b) (a->features & TMU_SUPPORT_ ## b)
|
||||
|
||||
@ -122,10 +124,6 @@ enum soc_type {
|
||||
* @threshold_th3_l0_shift: shift bits of level0 threshold temperature.
|
||||
* @tmu_inten: register containing the different threshold interrupt
|
||||
enable bits.
|
||||
* @inten_rise_shift: shift bits of all rising interrupt bits.
|
||||
* @inten_rise_mask: mask bits of all rising interrupt bits.
|
||||
* @inten_fall_shift: shift bits of all rising interrupt bits.
|
||||
* @inten_fall_mask: mask bits of all rising interrupt bits.
|
||||
* @inten_rise0_shift: shift bits of rising 0 interrupt bits.
|
||||
* @inten_rise1_shift: shift bits of rising 1 interrupt bits.
|
||||
* @inten_rise2_shift: shift bits of rising 2 interrupt bits.
|
||||
@ -136,6 +134,10 @@ enum soc_type {
|
||||
* @inten_fall3_shift: shift bits of falling 3 interrupt bits.
|
||||
* @tmu_intstat: Register containing the interrupt status values.
|
||||
* @tmu_intclear: Register for clearing the raised interrupt status.
|
||||
* @intclr_fall_shift: shift bits for interrupt clear fall 0
|
||||
* @intclr_rise_shift: shift bits of all rising interrupt bits.
|
||||
* @intclr_rise_mask: mask bits of all rising interrupt bits.
|
||||
* @intclr_fall_mask: mask bits of all rising interrupt bits.
|
||||
* @emul_con: TMU emulation controller register.
|
||||
* @emul_temp_shift: shift bits of emulation temperature.
|
||||
* @emul_time_shift: shift bits of emulation time.
|
||||
@ -149,6 +151,7 @@ struct exynos_tmu_registers {
|
||||
u32 triminfo_85_shift;
|
||||
|
||||
u32 triminfo_ctrl;
|
||||
u32 triminfo_ctrl1;
|
||||
u32 triminfo_reload_shift;
|
||||
|
||||
u32 tmu_ctrl;
|
||||
@ -191,10 +194,6 @@ struct exynos_tmu_registers {
|
||||
u32 threshold_th3_l0_shift;
|
||||
|
||||
u32 tmu_inten;
|
||||
u32 inten_rise_shift;
|
||||
u32 inten_rise_mask;
|
||||
u32 inten_fall_shift;
|
||||
u32 inten_fall_mask;
|
||||
u32 inten_rise0_shift;
|
||||
u32 inten_rise1_shift;
|
||||
u32 inten_rise2_shift;
|
||||
@ -207,6 +206,10 @@ struct exynos_tmu_registers {
|
||||
u32 tmu_intstat;
|
||||
|
||||
u32 tmu_intclear;
|
||||
u32 intclr_fall_shift;
|
||||
u32 intclr_rise_shift;
|
||||
u32 intclr_fall_mask;
|
||||
u32 intclr_rise_mask;
|
||||
|
||||
u32 emul_con;
|
||||
u32 emul_temp_shift;
|
||||
|
||||
@ -40,13 +40,13 @@ static const struct exynos_tmu_registers exynos4210_tmu_registers = {
|
||||
.threshold_temp = EXYNOS4210_TMU_REG_THRESHOLD_TEMP,
|
||||
.threshold_th0 = EXYNOS4210_TMU_REG_TRIG_LEVEL0,
|
||||
.tmu_inten = EXYNOS_TMU_REG_INTEN,
|
||||
.inten_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
|
||||
.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
|
||||
.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
|
||||
.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
|
||||
.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
|
||||
.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
|
||||
.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
|
||||
.intclr_rise_mask = EXYNOS4210_TMU_TRIG_LEVEL_MASK,
|
||||
};
|
||||
|
||||
struct exynos_tmu_init_data const exynos4210_default_tmu_data = {
|
||||
@ -112,10 +112,6 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
|
||||
.threshold_th0 = EXYNOS_THD_TEMP_RISE,
|
||||
.threshold_th1 = EXYNOS_THD_TEMP_FALL,
|
||||
.tmu_inten = EXYNOS_TMU_REG_INTEN,
|
||||
.inten_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
|
||||
.inten_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
|
||||
.inten_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
|
||||
.inten_fall_shift = EXYNOS_TMU_FALL_INT_SHIFT,
|
||||
.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
|
||||
.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
|
||||
.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
|
||||
@ -123,6 +119,10 @@ static const struct exynos_tmu_registers exynos4412_tmu_registers = {
|
||||
.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
|
||||
.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
|
||||
.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
|
||||
.intclr_fall_shift = EXYNOS_TMU_CLEAR_FALL_INT_SHIFT,
|
||||
.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
|
||||
.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
|
||||
.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
|
||||
.emul_con = EXYNOS_EMUL_CON,
|
||||
.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
|
||||
.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
|
||||
@ -194,6 +194,197 @@ struct exynos_tmu_init_data const exynos5250_default_tmu_data = {
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5260)
|
||||
static const struct exynos_tmu_registers exynos5260_tmu_registers = {
|
||||
.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
|
||||
.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
|
||||
.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
|
||||
.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
|
||||
.tmu_ctrl = EXYNOS_TMU_REG_CONTROL1,
|
||||
.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
|
||||
.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
|
||||
.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
|
||||
.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
|
||||
.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
|
||||
.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
|
||||
.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
|
||||
.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
|
||||
.tmu_status = EXYNOS_TMU_REG_STATUS,
|
||||
.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
|
||||
.threshold_th0 = EXYNOS_THD_TEMP_RISE,
|
||||
.threshold_th1 = EXYNOS_THD_TEMP_FALL,
|
||||
.tmu_inten = EXYNOS5260_TMU_REG_INTEN,
|
||||
.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
|
||||
.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
|
||||
.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
|
||||
.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
|
||||
.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
|
||||
.tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT,
|
||||
.tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR,
|
||||
.intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
|
||||
.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
|
||||
.intclr_rise_mask = EXYNOS5260_TMU_RISE_INT_MASK,
|
||||
.intclr_fall_mask = EXYNOS5260_TMU_FALL_INT_MASK,
|
||||
.emul_con = EXYNOS5260_EMUL_CON,
|
||||
.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
|
||||
.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
|
||||
.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
|
||||
};
|
||||
|
||||
#define __EXYNOS5260_TMU_DATA \
|
||||
.threshold_falling = 10, \
|
||||
.trigger_levels[0] = 85, \
|
||||
.trigger_levels[1] = 103, \
|
||||
.trigger_levels[2] = 110, \
|
||||
.trigger_levels[3] = 120, \
|
||||
.trigger_enable[0] = true, \
|
||||
.trigger_enable[1] = true, \
|
||||
.trigger_enable[2] = true, \
|
||||
.trigger_enable[3] = false, \
|
||||
.trigger_type[0] = THROTTLE_ACTIVE, \
|
||||
.trigger_type[1] = THROTTLE_ACTIVE, \
|
||||
.trigger_type[2] = SW_TRIP, \
|
||||
.trigger_type[3] = HW_TRIP, \
|
||||
.max_trigger_level = 4, \
|
||||
.gain = 8, \
|
||||
.reference_voltage = 16, \
|
||||
.noise_cancel_mode = 4, \
|
||||
.cal_type = TYPE_ONE_POINT_TRIMMING, \
|
||||
.efuse_value = 55, \
|
||||
.min_efuse_value = 40, \
|
||||
.max_efuse_value = 100, \
|
||||
.first_point_trim = 25, \
|
||||
.second_point_trim = 85, \
|
||||
.default_temp_offset = 50, \
|
||||
.freq_tab[0] = { \
|
||||
.freq_clip_max = 800 * 1000, \
|
||||
.temp_level = 85, \
|
||||
}, \
|
||||
.freq_tab[1] = { \
|
||||
.freq_clip_max = 200 * 1000, \
|
||||
.temp_level = 103, \
|
||||
}, \
|
||||
.freq_tab_count = 2, \
|
||||
.registers = &exynos5260_tmu_registers, \
|
||||
|
||||
#define EXYNOS5260_TMU_DATA \
|
||||
__EXYNOS5260_TMU_DATA \
|
||||
.type = SOC_ARCH_EXYNOS5260, \
|
||||
.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
|
||||
TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
|
||||
TMU_SUPPORT_EMUL_TIME)
|
||||
|
||||
struct exynos_tmu_init_data const exynos5260_default_tmu_data = {
|
||||
.tmu_data = {
|
||||
{ EXYNOS5260_TMU_DATA },
|
||||
{ EXYNOS5260_TMU_DATA },
|
||||
{ EXYNOS5260_TMU_DATA },
|
||||
{ EXYNOS5260_TMU_DATA },
|
||||
{ EXYNOS5260_TMU_DATA },
|
||||
},
|
||||
.tmu_count = 5,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5420)
|
||||
static const struct exynos_tmu_registers exynos5420_tmu_registers = {
|
||||
.triminfo_data = EXYNOS_TMU_REG_TRIMINFO,
|
||||
.triminfo_25_shift = EXYNOS_TRIMINFO_25_SHIFT,
|
||||
.triminfo_85_shift = EXYNOS_TRIMINFO_85_SHIFT,
|
||||
.tmu_ctrl = EXYNOS_TMU_REG_CONTROL,
|
||||
.buf_vref_sel_shift = EXYNOS_TMU_REF_VOLTAGE_SHIFT,
|
||||
.buf_vref_sel_mask = EXYNOS_TMU_REF_VOLTAGE_MASK,
|
||||
.therm_trip_mode_shift = EXYNOS_TMU_TRIP_MODE_SHIFT,
|
||||
.therm_trip_mode_mask = EXYNOS_TMU_TRIP_MODE_MASK,
|
||||
.therm_trip_en_shift = EXYNOS_TMU_THERM_TRIP_EN_SHIFT,
|
||||
.buf_slope_sel_shift = EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT,
|
||||
.buf_slope_sel_mask = EXYNOS_TMU_BUF_SLOPE_SEL_MASK,
|
||||
.core_en_shift = EXYNOS_TMU_CORE_EN_SHIFT,
|
||||
.tmu_status = EXYNOS_TMU_REG_STATUS,
|
||||
.tmu_cur_temp = EXYNOS_TMU_REG_CURRENT_TEMP,
|
||||
.threshold_th0 = EXYNOS_THD_TEMP_RISE,
|
||||
.threshold_th1 = EXYNOS_THD_TEMP_FALL,
|
||||
.tmu_inten = EXYNOS_TMU_REG_INTEN,
|
||||
.inten_rise0_shift = EXYNOS_TMU_INTEN_RISE0_SHIFT,
|
||||
.inten_rise1_shift = EXYNOS_TMU_INTEN_RISE1_SHIFT,
|
||||
.inten_rise2_shift = EXYNOS_TMU_INTEN_RISE2_SHIFT,
|
||||
/* INTEN_RISE3 Not availble in exynos5420 */
|
||||
.inten_rise3_shift = EXYNOS_TMU_INTEN_RISE3_SHIFT,
|
||||
.inten_fall0_shift = EXYNOS_TMU_INTEN_FALL0_SHIFT,
|
||||
.tmu_intstat = EXYNOS_TMU_REG_INTSTAT,
|
||||
.tmu_intclear = EXYNOS_TMU_REG_INTCLEAR,
|
||||
.intclr_fall_shift = EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT,
|
||||
.intclr_rise_shift = EXYNOS_TMU_RISE_INT_SHIFT,
|
||||
.intclr_rise_mask = EXYNOS_TMU_RISE_INT_MASK,
|
||||
.intclr_fall_mask = EXYNOS_TMU_FALL_INT_MASK,
|
||||
.emul_con = EXYNOS_EMUL_CON,
|
||||
.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
|
||||
.emul_time_shift = EXYNOS_EMUL_TIME_SHIFT,
|
||||
.emul_time_mask = EXYNOS_EMUL_TIME_MASK,
|
||||
};
|
||||
|
||||
#define __EXYNOS5420_TMU_DATA \
|
||||
.threshold_falling = 10, \
|
||||
.trigger_levels[0] = 85, \
|
||||
.trigger_levels[1] = 103, \
|
||||
.trigger_levels[2] = 110, \
|
||||
.trigger_levels[3] = 120, \
|
||||
.trigger_enable[0] = true, \
|
||||
.trigger_enable[1] = true, \
|
||||
.trigger_enable[2] = true, \
|
||||
.trigger_enable[3] = false, \
|
||||
.trigger_type[0] = THROTTLE_ACTIVE, \
|
||||
.trigger_type[1] = THROTTLE_ACTIVE, \
|
||||
.trigger_type[2] = SW_TRIP, \
|
||||
.trigger_type[3] = HW_TRIP, \
|
||||
.max_trigger_level = 4, \
|
||||
.gain = 8, \
|
||||
.reference_voltage = 16, \
|
||||
.noise_cancel_mode = 4, \
|
||||
.cal_type = TYPE_ONE_POINT_TRIMMING, \
|
||||
.efuse_value = 55, \
|
||||
.min_efuse_value = 40, \
|
||||
.max_efuse_value = 100, \
|
||||
.first_point_trim = 25, \
|
||||
.second_point_trim = 85, \
|
||||
.default_temp_offset = 50, \
|
||||
.freq_tab[0] = { \
|
||||
.freq_clip_max = 800 * 1000, \
|
||||
.temp_level = 85, \
|
||||
}, \
|
||||
.freq_tab[1] = { \
|
||||
.freq_clip_max = 200 * 1000, \
|
||||
.temp_level = 103, \
|
||||
}, \
|
||||
.freq_tab_count = 2, \
|
||||
.registers = &exynos5420_tmu_registers, \
|
||||
|
||||
#define EXYNOS5420_TMU_DATA \
|
||||
__EXYNOS5420_TMU_DATA \
|
||||
.type = SOC_ARCH_EXYNOS5250, \
|
||||
.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
|
||||
TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
|
||||
TMU_SUPPORT_EMUL_TIME)
|
||||
|
||||
#define EXYNOS5420_TMU_DATA_SHARED \
|
||||
__EXYNOS5420_TMU_DATA \
|
||||
.type = SOC_ARCH_EXYNOS5420_TRIMINFO, \
|
||||
.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_TRIM_RELOAD | \
|
||||
TMU_SUPPORT_FALLING_TRIP | TMU_SUPPORT_READY_STATUS | \
|
||||
TMU_SUPPORT_EMUL_TIME | TMU_SUPPORT_ADDRESS_MULTIPLE)
|
||||
|
||||
struct exynos_tmu_init_data const exynos5420_default_tmu_data = {
|
||||
.tmu_data = {
|
||||
{ EXYNOS5420_TMU_DATA },
|
||||
{ EXYNOS5420_TMU_DATA },
|
||||
{ EXYNOS5420_TMU_DATA_SHARED },
|
||||
{ EXYNOS5420_TMU_DATA_SHARED },
|
||||
{ EXYNOS5420_TMU_DATA_SHARED },
|
||||
},
|
||||
.tmu_count = 5,
|
||||
};
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5440)
|
||||
static const struct exynos_tmu_registers exynos5440_tmu_registers = {
|
||||
.triminfo_data = EXYNOS5440_TMU_S0_7_TRIM,
|
||||
@ -217,10 +408,6 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
|
||||
.threshold_th2 = EXYNOS5440_TMU_S0_7_TH2,
|
||||
.threshold_th3_l0_shift = EXYNOS5440_TMU_TH_RISE4_SHIFT,
|
||||
.tmu_inten = EXYNOS5440_TMU_S0_7_IRQEN,
|
||||
.inten_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
|
||||
.inten_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
|
||||
.inten_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
|
||||
.inten_fall_shift = EXYNOS5440_TMU_FALL_INT_SHIFT,
|
||||
.inten_rise0_shift = EXYNOS5440_TMU_INTEN_RISE0_SHIFT,
|
||||
.inten_rise1_shift = EXYNOS5440_TMU_INTEN_RISE1_SHIFT,
|
||||
.inten_rise2_shift = EXYNOS5440_TMU_INTEN_RISE2_SHIFT,
|
||||
@ -228,6 +415,10 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
|
||||
.inten_fall0_shift = EXYNOS5440_TMU_INTEN_FALL0_SHIFT,
|
||||
.tmu_intstat = EXYNOS5440_TMU_S0_7_IRQ,
|
||||
.tmu_intclear = EXYNOS5440_TMU_S0_7_IRQ,
|
||||
.intclr_fall_shift = EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT,
|
||||
.intclr_rise_shift = EXYNOS5440_TMU_RISE_INT_SHIFT,
|
||||
.intclr_rise_mask = EXYNOS5440_TMU_RISE_INT_MASK,
|
||||
.intclr_fall_mask = EXYNOS5440_TMU_FALL_INT_MASK,
|
||||
.tmu_irqstatus = EXYNOS5440_TMU_IRQ_STATUS,
|
||||
.emul_con = EXYNOS5440_TMU_S0_7_DEBUG,
|
||||
.emul_temp_shift = EXYNOS_EMUL_DATA_SHIFT,
|
||||
@ -255,7 +446,7 @@ static const struct exynos_tmu_registers exynos5440_tmu_registers = {
|
||||
.type = SOC_ARCH_EXYNOS5440, \
|
||||
.registers = &exynos5440_tmu_registers, \
|
||||
.features = (TMU_SUPPORT_EMULATION | TMU_SUPPORT_FALLING_TRIP | \
|
||||
TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_SHARED_MEMORY),
|
||||
TMU_SUPPORT_MULTI_INST | TMU_SUPPORT_ADDRESS_MULTIPLE),
|
||||
|
||||
struct exynos_tmu_init_data const exynos5440_default_tmu_data = {
|
||||
.tmu_data = {
|
||||
|
||||
@ -69,9 +69,11 @@
|
||||
#define EXYNOS_TMU_RISE_INT_MASK 0x111
|
||||
#define EXYNOS_TMU_RISE_INT_SHIFT 0
|
||||
#define EXYNOS_TMU_FALL_INT_MASK 0x111
|
||||
#define EXYNOS_TMU_FALL_INT_SHIFT 12
|
||||
#define EXYNOS_TMU_CLEAR_RISE_INT 0x111
|
||||
#define EXYNOS_TMU_CLEAR_FALL_INT (0x111 << 12)
|
||||
#define EXYNOS_TMU_CLEAR_FALL_INT_SHIFT 12
|
||||
#define EXYNOS5420_TMU_CLEAR_FALL_INT_SHIFT 16
|
||||
#define EXYNOS5440_TMU_CLEAR_FALL_INT_SHIFT 4
|
||||
#define EXYNOS_TMU_TRIP_MODE_SHIFT 13
|
||||
#define EXYNOS_TMU_TRIP_MODE_MASK 0x7
|
||||
#define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12
|
||||
@ -85,6 +87,7 @@
|
||||
#define EXYNOS_TMU_INTEN_FALL0_SHIFT 16
|
||||
#define EXYNOS_TMU_INTEN_FALL1_SHIFT 20
|
||||
#define EXYNOS_TMU_INTEN_FALL2_SHIFT 24
|
||||
#define EXYNOS_TMU_INTEN_FALL3_SHIFT 28
|
||||
|
||||
#define EXYNOS_EMUL_TIME 0x57F0
|
||||
#define EXYNOS_EMUL_TIME_MASK 0xffff
|
||||
@ -95,6 +98,17 @@
|
||||
|
||||
#define EXYNOS_MAX_TRIGGER_PER_REG 4
|
||||
|
||||
/* Exynos5260 specific */
|
||||
#define EXYNOS_TMU_REG_CONTROL1 0x24
|
||||
#define EXYNOS5260_TMU_REG_INTEN 0xC0
|
||||
#define EXYNOS5260_TMU_REG_INTSTAT 0xC4
|
||||
#define EXYNOS5260_TMU_REG_INTCLEAR 0xC8
|
||||
#define EXYNOS5260_TMU_CLEAR_RISE_INT 0x1111
|
||||
#define EXYNOS5260_TMU_CLEAR_FALL_INT (0x1111 << 16)
|
||||
#define EXYNOS5260_TMU_RISE_INT_MASK 0x1111
|
||||
#define EXYNOS5260_TMU_FALL_INT_MASK 0x1111
|
||||
#define EXYNOS5260_EMUL_CON 0x100
|
||||
|
||||
/* Exynos4412 specific */
|
||||
#define EXYNOS4412_MUX_ADDR_VALUE 6
|
||||
#define EXYNOS4412_MUX_ADDR_SHIFT 20
|
||||
@ -119,7 +133,6 @@
|
||||
#define EXYNOS5440_TMU_RISE_INT_MASK 0xf
|
||||
#define EXYNOS5440_TMU_RISE_INT_SHIFT 0
|
||||
#define EXYNOS5440_TMU_FALL_INT_MASK 0xf
|
||||
#define EXYNOS5440_TMU_FALL_INT_SHIFT 4
|
||||
#define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0
|
||||
#define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1
|
||||
#define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2
|
||||
@ -156,6 +169,20 @@ extern struct exynos_tmu_init_data const exynos5250_default_tmu_data;
|
||||
#define EXYNOS5250_TMU_DRV_DATA (NULL)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5260)
|
||||
extern struct exynos_tmu_init_data const exynos5260_default_tmu_data;
|
||||
#define EXYNOS5260_TMU_DRV_DATA (&exynos5260_default_tmu_data)
|
||||
#else
|
||||
#define EXYNOS5260_TMU_DRV_DATA (NULL)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5420)
|
||||
extern struct exynos_tmu_init_data const exynos5420_default_tmu_data;
|
||||
#define EXYNOS5420_TMU_DRV_DATA (&exynos5420_default_tmu_data)
|
||||
#else
|
||||
#define EXYNOS5420_TMU_DRV_DATA (NULL)
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_SOC_EXYNOS5440)
|
||||
extern struct exynos_tmu_init_data const exynos5440_default_tmu_data;
|
||||
#define EXYNOS5440_TMU_DRV_DATA (&exynos5440_default_tmu_data)
|
||||
|
||||
@ -113,10 +113,8 @@ static int spear_thermal_probe(struct platform_device *pdev)
|
||||
}
|
||||
|
||||
stdev = devm_kzalloc(&pdev->dev, sizeof(*stdev), GFP_KERNEL);
|
||||
if (!stdev) {
|
||||
dev_err(&pdev->dev, "kzalloc fail\n");
|
||||
if (!stdev)
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
/* Enable thermal sensor */
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
||||
|
||||
@ -1248,7 +1248,7 @@ int ti_bandgap_probe(struct platform_device *pdev)
|
||||
clk_rate = clk_round_rate(bgp->div_clk,
|
||||
bgp->conf->sensors[0].ts_data->max_freq);
|
||||
if (clk_rate < bgp->conf->sensors[0].ts_data->min_freq ||
|
||||
clk_rate == 0xffffffff) {
|
||||
clk_rate <= 0) {
|
||||
ret = -ENODEV;
|
||||
dev_err(&pdev->dev, "wrong clock rate (%d)\n", clk_rate);
|
||||
goto put_clks;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user