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ARM: dts: omap3: Migrate AES from hwmods to sysc-omap2

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Various OMAP3 boards have two AES blocks, but only one is currently
available, because the hwmods are only configured for one.

This patch migrates the hwmods for the AES engine to sysc-omap2
which allows the second AES crypto engine to become available.

  omap-aes 480a6000.aes1: OMAP AES hw accel rev: 2.6
  omap-aes 480a6000.aes1: will run requests pump with realtime priority
  omap-aes 480c5000.aes2: OMAP AES hw accel rev: 2.6
  omap-aes 480c5000.aes2: will run requests pump with realtime priority

Signed-off-by: Adam Ford <aford173@gmail.com>
[tony@atomide.com: updated to disable both aes_targets on hs boards]
Signed-off-by: Tony Lindgren <tony@atomide.com>
This commit is contained in:
Adam Ford 2020-06-17 05:58:40 -05:00 committed by Tony Lindgren
parent b3a9e3b962
commit c312f06631
5 changed files with 64 additions and 70 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
arch/arm/boot/dts/am3517.dtsi
View File

@ -10,6 +10,10 @@
#include "omap3.dtsi"
/* AM3517 doesn't appear to have the crypto engines defined in omap3.dtsi */
/delete-node/ &aes1_target;
/delete-node/ &aes2_target;
/ {
aliases {
serial3 = &uart4;

6
arch/arm/boot/dts/omap3-n900.dts
View File

@ -19,7 +19,11 @@
* but it is not widely used and to prevent kernel crash rather AES is disabled.
* There is also no runtime detection code if AES is disabled in L3 firewall...
*/
&aes {
&aes1_target {
status = "disabled";
};
&aes2_target {
status = "disabled";
};

6
arch/arm/boot/dts/omap3-tao3530.dtsi
View File

@ -8,7 +8,11 @@
#include "omap34xx.dtsi"
/* Secure omaps have some devices inaccessible depending on the firmware */
&aes {
&aes1_target {
status = "disabled";
};
&aes2_target {
status = "disabled";
};

57
arch/arm/boot/dts/omap3.dtsi
View File

@ -157,13 +157,56 @@
};
};
aes: aes@480c5000 {
compatible = "ti,omap3-aes";
ti,hwmods = "aes";
reg = <0x480c5000 0x50>;
interrupts = <0>;
dmas = <&sdma 65 &sdma 66>;
dma-names = "tx", "rx";
aes1_target: target-module@480a6000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x480a6044 0x4>,
<0x480a6048 0x4>,
<0x480a604c 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&aes1_ick>;
clock-names = "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x480a6000 0x2000>;
aes1: aes1@0 {
compatible = "ti,omap3-aes";
reg = <0 0x50>;
interrupts = <0>;
dmas = <&sdma 9 &sdma 10>;
dma-names = "tx", "rx";
};
};
aes2_target: target-module@480c5000 {
compatible = "ti,sysc-omap2", "ti,sysc";
reg = <0x480c5044 0x4>,
<0x480c5048 0x4>,
<0x480c504c 0x4>;
reg-names = "rev", "sysc", "syss";
ti,sysc-mask = <(SYSC_OMAP2_AUTOIDLE)>;
ti,sysc-sidle = <SYSC_IDLE_FORCE>,
<SYSC_IDLE_NO>,
<SYSC_IDLE_SMART>;
ti,syss-mask = <1>;
clocks = <&aes2_ick>;
clock-names = "ick";
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0x480c5000 0x2000>;
aes2: aes2@0 {
compatible = "ti,omap3-aes";
reg = <0 0x50>;
interrupts = <0>;
dmas = <&sdma 65 &sdma 66>;
dma-names = "tx", "rx";
};
};
prm: prm@48306000 {

61
arch/arm/mach-omap2/omap_hwmod_3xxx_data.c
View File

@ -2342,44 +2342,6 @@ static struct omap_hwmod_ocp_if omap3xxx_l4_core__sham = {
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/* l4_core -> AES */
static struct omap_hwmod_class_sysconfig omap3_aes_sysc = {
.rev_offs = 0x44,
.sysc_offs = 0x48,
.syss_offs = 0x4c,
.sysc_flags = (SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET |
SYSC_HAS_AUTOIDLE | SYSS_HAS_RESET_STATUS),
.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
.sysc_fields = &omap3xxx_aes_sysc_fields,
};
static struct omap_hwmod_class omap3xxx_aes_class = {
.name = "aes",
.sysc = &omap3_aes_sysc,
};
static struct omap_hwmod omap3xxx_aes_hwmod = {
.name = "aes",
.main_clk = "aes2_ick",
.prcm = {
.omap2 = {
.module_offs = CORE_MOD,
.idlest_reg_id = 1,
.idlest_idle_bit = OMAP3430_ST_AES2_SHIFT,
},
},
.class = &omap3xxx_aes_class,
};
static struct omap_hwmod_ocp_if omap3xxx_l4_core__aes = {
.master = &omap3xxx_l4_core_hwmod,
.slave = &omap3xxx_aes_hwmod,
.clk = "aes2_ick",
.user = OCP_USER_MPU | OCP_USER_SDMA,
};
/*
* 'ssi' class
* synchronous serial interface (multichannel and full-duplex serial if)
@ -2473,20 +2435,11 @@ static struct omap_hwmod_ocp_if *omap34xx_sham_hwmod_ocp_ifs[] __initdata = {
NULL,
};
static struct omap_hwmod_ocp_if *omap34xx_aes_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__aes,
NULL,
};
static struct omap_hwmod_ocp_if *omap36xx_sham_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__sham,
NULL
};
static struct omap_hwmod_ocp_if *omap36xx_aes_hwmod_ocp_ifs[] __initdata = {
&omap3xxx_l4_core__aes,
NULL
};
/*
* Apparently the SHA/MD5 and AES accelerator IP blocks are
@ -2501,11 +2454,6 @@ static struct omap_hwmod_ocp_if *am35xx_sham_hwmod_ocp_ifs[] __initdata = {
NULL
};
static struct omap_hwmod_ocp_if *am35xx_aes_hwmod_ocp_ifs[] __initdata = {
/* &omap3xxx_l4_core__aes, */
NULL,
};
/* 3430ES1-only hwmod links */
static struct omap_hwmod_ocp_if *omap3430es1_hwmod_ocp_ifs[] __initdata = {
&omap3430es1_dss__l3,
@ -2641,7 +2589,6 @@ int __init omap3xxx_hwmod_init(void)
{
int r;
struct omap_hwmod_ocp_if **h = NULL, **h_sham = NULL;
struct omap_hwmod_ocp_if **h_aes = NULL;
struct device_node *bus;
unsigned int rev;
@ -2664,16 +2611,13 @@ int __init omap3xxx_hwmod_init(void)
rev == OMAP3430_REV_ES3_1 || rev == OMAP3430_REV_ES3_1_2) {
h = omap34xx_hwmod_ocp_ifs;
h_sham = omap34xx_sham_hwmod_ocp_ifs;
h_aes = omap34xx_aes_hwmod_ocp_ifs;
} else if (rev == AM35XX_REV_ES1_0 || rev == AM35XX_REV_ES1_1) {
h = am35xx_hwmod_ocp_ifs;
h_sham = am35xx_sham_hwmod_ocp_ifs;
h_aes = am35xx_aes_hwmod_ocp_ifs;
} else if (rev == OMAP3630_REV_ES1_0 || rev == OMAP3630_REV_ES1_1 ||
rev == OMAP3630_REV_ES1_2) {
h = omap36xx_hwmod_ocp_ifs;
h_sham = omap36xx_sham_hwmod_ocp_ifs;
h_aes = omap36xx_aes_hwmod_ocp_ifs;
} else {
WARN(1, "OMAP3 hwmod family init: unknown chip type\n");
return -EINVAL;
@ -2696,11 +2640,6 @@ int __init omap3xxx_hwmod_init(void)
goto put_node;
}
if (h_aes && omap3xxx_hwmod_is_hs_ip_block_usable(bus, "aes")) {
r = omap_hwmod_register_links(h_aes);
if (r < 0)
goto put_node;
}
of_node_put(bus);
/*