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pinctrl: at91: correct a few typos
Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
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@ -118,7 +118,7 @@ struct at91_pin_group {
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};
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};
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/**
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/**
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* struct at91_pinctrl_mux_ops - describes an At91 mux ops group
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* struct at91_pinctrl_mux_ops - describes an AT91 mux ops group
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* on new IP with support for periph C and D the way to mux in
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* on new IP with support for periph C and D the way to mux in
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* periph A and B has changed
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* periph A and B has changed
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* So provide the right call back
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* So provide the right call back
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@ -1396,7 +1396,7 @@ static void gpio_irq_handler(unsigned irq, struct irq_desc *desc)
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chained_irq_enter(chip, desc);
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chained_irq_enter(chip, desc);
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for (;;) {
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for (;;) {
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/* Reading ISR acks pending (edge triggered) GPIO interrupts.
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/* Reading ISR acks pending (edge triggered) GPIO interrupts.
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* When there none are pending, we're finished unless we need
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* When there are none pending, we're finished unless we need
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* to process multiple banks (like ID_PIOCDE on sam9263).
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* to process multiple banks (like ID_PIOCDE on sam9263).
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*/
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*/
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isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
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isr = readl_relaxed(pio + PIO_ISR) & readl_relaxed(pio + PIO_IMR);
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@ -1505,7 +1505,7 @@ static int at91_gpio_of_irq_setup(struct device_node *node,
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prev = gpio_chips[at91_gpio->pioc_idx - 1];
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prev = gpio_chips[at91_gpio->pioc_idx - 1];
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/* The top level handler handles one bank of GPIOs, except
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/* The top level handler handles one bank of GPIOs, except
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* on some SoC it can handles up to three...
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* on some SoC it can handle up to three...
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* We only set up the handler for the first of the list.
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* We only set up the handler for the first of the list.
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*/
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*/
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if (prev && prev->next == at91_gpio)
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if (prev && prev->next == at91_gpio)
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