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phy: mediatek: xsphy: remove macros used to prepare bitfield value

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Prefer to make use of FIELD_PREP() macro to prepare bitfield value,
then no need local ones anymore.

Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lore.kernel.org/r/20220920090038.15133-4-chunfeng.yun@mediatek.com
Signed-off-by: Vinod Koul <vkoul@kernel.org>
This commit is contained in:
Chunfeng Yun 2022-09-20 17:00:23 +08:00 committed by Vinod Koul
parent 6b5ef19461
commit c221baa355
1 changed files with 17 additions and 29 deletions
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46
drivers/phy/mediatek/phy-mtk-xsphy.c
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@ -37,7 +37,6 @@
#define XSP_U2FREQ_FMCR0 ((SSUSB_SIFSLV_U2FREQ) + 0x00)
#define P2F_RG_FREQDET_EN BIT(24)
#define P2F_RG_CYCLECNT GENMASK(23, 0)
#define P2F_RG_CYCLECNT_VAL(x) ((P2F_RG_CYCLECNT) & (x))
#define XSP_U2FREQ_MMONR0 ((SSUSB_SIFSLV_U2FREQ) + 0x0c)
@ -50,16 +49,12 @@
#define XSP_USBPHYACR1 ((SSUSB_SIFSLV_U2PHY_COM) + 0x04)
#define P2A1_RG_INTR_CAL GENMASK(23, 19)
#define P2A1_RG_INTR_CAL_VAL(x) ((0x1f & (x)) << 19)
#define P2A1_RG_VRT_SEL GENMASK(14, 12)
#define P2A1_RG_VRT_SEL_VAL(x) ((0x7 & (x)) << 12)
#define P2A1_RG_TERM_SEL GENMASK(10, 8)
#define P2A1_RG_TERM_SEL_VAL(x) ((0x7 & (x)) << 8)
#define XSP_USBPHYACR5 ((SSUSB_SIFSLV_U2PHY_COM) + 0x014)
#define P2A5_RG_HSTX_SRCAL_EN BIT(15)
#define P2A5_RG_HSTX_SRCTRL GENMASK(14, 12)
#define P2A5_RG_HSTX_SRCTRL_VAL(x) ((0x7 & (x)) << 12)
#define XSP_USBPHYACR6 ((SSUSB_SIFSLV_U2PHY_COM) + 0x018)
#define P2A6_RG_BC11_SW_EN BIT(23)
@ -74,15 +69,12 @@
#define SSPXTP_PHYA_GLB_00 ((SSPXTP_SIFSLV_PHYA_GLB) + 0x00)
#define RG_XTP_GLB_BIAS_INTR_CTRL GENMASK(21, 16)
#define RG_XTP_GLB_BIAS_INTR_CTRL_VAL(x) ((0x3f & (x)) << 16)
#define SSPXTP_PHYA_LN_04 ((SSPXTP_SIFSLV_PHYA_LN) + 0x04)
#define RG_XTP_LN0_TX_IMPSEL GENMASK(4, 0)
#define RG_XTP_LN0_TX_IMPSEL_VAL(x) (0x1f & (x))
#define SSPXTP_PHYA_LN_14 ((SSPXTP_SIFSLV_PHYA_LN) + 0x014)
#define RG_XTP_LN0_RX_IMPSEL GENMASK(4, 0)
#define RG_XTP_LN0_RX_IMPSEL_VAL(x) (0x1f & (x))
#define XSP_REF_CLK 26 /* MHZ */
#define XSP_SLEW_RATE_COEF 17
@ -134,8 +126,8 @@ static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy,
mtk_phy_set_bits(pbase + XSP_U2FREQ_FMMONR1, P2F_RG_FRCK_EN);
/* set cycle count as 1024 */
mtk_phy_update_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT,
P2F_RG_CYCLECNT_VAL(XSP_FM_DET_CYCLE_CNT));
mtk_phy_update_field(pbase + XSP_U2FREQ_FMCR0, P2F_RG_CYCLECNT,
XSP_FM_DET_CYCLE_CNT);
/* enable frequency meter */
mtk_phy_set_bits(pbase + XSP_U2FREQ_FMCR0, P2F_RG_FREQDET_EN);
@ -166,8 +158,7 @@ static void u2_phy_slew_rate_calibrate(struct mtk_xsphy *xsphy,
xsphy->src_ref_clk, xsphy->src_coef);
/* set HS slew rate */
mtk_phy_update_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL,
P2A5_RG_HSTX_SRCTRL_VAL(calib_val));
mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL, calib_val);
/* disable USB ring oscillator */
mtk_phy_clear_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCAL_EN);
@ -280,20 +271,20 @@ static void u2_phy_props_set(struct mtk_xsphy *xsphy,
void __iomem *pbase = inst->port_base;
if (inst->efuse_intr)
mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL,
P2A1_RG_INTR_CAL_VAL(inst->efuse_intr));
mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_INTR_CAL,
inst->efuse_intr);
if (inst->eye_src)
mtk_phy_update_bits(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL,
P2A5_RG_HSTX_SRCTRL_VAL(inst->eye_src));
mtk_phy_update_field(pbase + XSP_USBPHYACR5, P2A5_RG_HSTX_SRCTRL,
inst->eye_src);
if (inst->eye_vrt)
mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL,
P2A1_RG_VRT_SEL_VAL(inst->eye_vrt));
mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_VRT_SEL,
inst->eye_vrt);
if (inst->eye_term)
mtk_phy_update_bits(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL,
P2A1_RG_TERM_SEL_VAL(inst->eye_term));
mtk_phy_update_field(pbase + XSP_USBPHYACR1, P2A1_RG_TERM_SEL,
inst->eye_term);
}
static void u3_phy_props_set(struct mtk_xsphy *xsphy,
@ -302,19 +293,16 @@ static void u3_phy_props_set(struct mtk_xsphy *xsphy,
void __iomem *pbase = inst->port_base;
if (inst->efuse_intr)
mtk_phy_update_bits(xsphy->glb_base + SSPXTP_PHYA_GLB_00,
RG_XTP_GLB_BIAS_INTR_CTRL,
RG_XTP_GLB_BIAS_INTR_CTRL_VAL(inst->efuse_intr));
mtk_phy_update_field(xsphy->glb_base + SSPXTP_PHYA_GLB_00,
RG_XTP_GLB_BIAS_INTR_CTRL, inst->efuse_intr);
if (inst->efuse_tx_imp)
mtk_phy_update_bits(pbase + SSPXTP_PHYA_LN_04,
RG_XTP_LN0_TX_IMPSEL,
RG_XTP_LN0_TX_IMPSEL_VAL(inst->efuse_tx_imp));
mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_04,
RG_XTP_LN0_TX_IMPSEL, inst->efuse_tx_imp);
if (inst->efuse_rx_imp)
mtk_phy_update_bits(pbase + SSPXTP_PHYA_LN_14,
RG_XTP_LN0_RX_IMPSEL,
RG_XTP_LN0_RX_IMPSEL_VAL(inst->efuse_rx_imp));
mtk_phy_update_field(pbase + SSPXTP_PHYA_LN_14,
RG_XTP_LN0_RX_IMPSEL, inst->efuse_rx_imp);
}
static int mtk_phy_init(struct phy *phy)