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habanalabs/gaudi2: read mmio razwi information
In gaudi2 there night be different routers for low b/w and high b/w transactions. But in the code that collects razwi information, we used the same router for high b/w and low b/w. Fixed it by reading the information also from low b/w routers. Signed-off-by: Dani Liberman <dliberman@habana.ai> Reviewed-by: Oded Gabbay <ogabbay@kernel.org> Signed-off-by: Oded Gabbay <ogabbay@kernel.org>
This commit is contained in:
Dani Liberman
Oded Gabbay
parent
ac5af9900f
commit
c21f9f3471
@ -1568,7 +1568,7 @@ enum rtr_id {
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DCORE3_RTR7,
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};
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static const u32 gaudi2_tpc_initiator_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1] = {
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static const u32 gaudi2_tpc_initiator_hbw_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1] = {
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DCORE0_RTR1, DCORE0_RTR1, DCORE0_RTR2, DCORE0_RTR2, DCORE0_RTR3, DCORE0_RTR3,
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DCORE1_RTR6, DCORE1_RTR6, DCORE1_RTR5, DCORE1_RTR5, DCORE1_RTR4, DCORE1_RTR4,
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DCORE2_RTR3, DCORE2_RTR3, DCORE2_RTR2, DCORE2_RTR2, DCORE2_RTR1, DCORE2_RTR1,
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@ -1576,12 +1576,30 @@ static const u32 gaudi2_tpc_initiator_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORE
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DCORE0_RTR0
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};
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static const u32 gaudi2_dec_initiator_rtr_id[NUMBER_OF_DEC] = {
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static const u32 gaudi2_tpc_initiator_lbw_rtr_id[NUM_OF_TPC_PER_DCORE * NUM_OF_DCORES + 1] = {
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DCORE0_RTR1, DCORE0_RTR1, DCORE0_RTR1, DCORE0_RTR1, DCORE0_RTR2, DCORE0_RTR2,
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DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR6, DCORE1_RTR6, DCORE1_RTR5, DCORE1_RTR5,
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DCORE2_RTR2, DCORE2_RTR2, DCORE2_RTR1, DCORE2_RTR1, DCORE2_RTR0, DCORE2_RTR0,
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DCORE3_RTR5, DCORE3_RTR5, DCORE3_RTR6, DCORE3_RTR6, DCORE3_RTR7, DCORE3_RTR7,
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DCORE0_RTR0
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};
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static const u32 gaudi2_dec_initiator_hbw_rtr_id[NUMBER_OF_DEC] = {
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DCORE0_RTR0, DCORE0_RTR0, DCORE1_RTR7, DCORE1_RTR7, DCORE2_RTR0, DCORE2_RTR0,
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DCORE3_RTR7, DCORE3_RTR7, DCORE0_RTR0, DCORE0_RTR0
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};
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static const u32 gaudi2_nic_initiator_rtr_id[NIC_NUMBER_OF_MACROS] = {
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static const u32 gaudi2_dec_initiator_lbw_rtr_id[NUMBER_OF_DEC] = {
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DCORE0_RTR1, DCORE0_RTR1, DCORE1_RTR6, DCORE1_RTR6, DCORE2_RTR1, DCORE2_RTR1,
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DCORE3_RTR6, DCORE3_RTR6, DCORE0_RTR0, DCORE0_RTR0
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};
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static const u32 gaudi2_nic_initiator_hbw_rtr_id[NIC_NUMBER_OF_MACROS] = {
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DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE2_RTR0,
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DCORE2_RTR0, DCORE2_RTR0, DCORE2_RTR0, DCORE3_RTR7, DCORE3_RTR7, DCORE3_RTR7
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};
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static const u32 gaudi2_nic_initiator_lbw_rtr_id[NIC_NUMBER_OF_MACROS] = {
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DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE1_RTR7, DCORE2_RTR0,
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DCORE2_RTR0, DCORE2_RTR0, DCORE2_RTR0, DCORE3_RTR7, DCORE3_RTR7, DCORE3_RTR7
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};
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@ -1595,14 +1613,22 @@ static const struct sft_info gaudi2_edma_initiator_sft_id[NUM_OF_EDMA_PER_DCORE
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{0, 0}, {1, 0}, {0, 1}, {1, 1}, {1, 2}, {1, 3}, {0, 2}, {0, 3},
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};
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static const u32 gaudi2_pdma_initiator_rtr_id[NUM_OF_PDMA] = {
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static const u32 gaudi2_pdma_initiator_hbw_rtr_id[NUM_OF_PDMA] = {
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DCORE0_RTR0, DCORE0_RTR0
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};
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static const u32 gaudi2_rot_initiator_rtr_id[NUM_OF_ROT] = {
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static const u32 gaudi2_pdma_initiator_lbw_rtr_id[NUM_OF_PDMA] = {
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DCORE0_RTR2, DCORE0_RTR2
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};
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static const u32 gaudi2_rot_initiator_hbw_rtr_id[NUM_OF_ROT] = {
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DCORE2_RTR0, DCORE3_RTR7
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};
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static const u32 gaudi2_rot_initiator_lbw_rtr_id[NUM_OF_ROT] = {
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DCORE2_RTR2, DCORE3_RTR5
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};
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struct mme_initiators_rtr_id {
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u32 wap0;
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u32 wap1;
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@ -7185,50 +7211,60 @@ static void gaudi2_ack_module_razwi_event_handler(struct hl_device *hdev,
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u8 module_sub_idx, u64 *event_mask)
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{
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bool via_sft = false;
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u32 rtr_id, dcore_id, dcore_rtr_id, sft_id, eng_id;
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u64 rtr_mstr_if_base_addr;
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u32 hbw_rtr_id, lbw_rtr_id, dcore_id, dcore_rtr_id, sft_id, eng_id;
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u64 hbw_rtr_mstr_if_base_addr, lbw_rtr_mstr_if_base_addr;
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u32 hbw_shrd_aw = 0, hbw_shrd_ar = 0;
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u32 lbw_shrd_aw = 0, lbw_shrd_ar = 0;
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char initiator_name[64];
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switch (module) {
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case RAZWI_TPC:
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rtr_id = gaudi2_tpc_initiator_rtr_id[module_idx];
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hbw_rtr_id = gaudi2_tpc_initiator_hbw_rtr_id[module_idx];
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/* TODO : remove this check and depend only on tpc routers table
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* when SW-118828 is resolved
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*/
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if (!hdev->asic_prop.fw_security_enabled &&
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((module_idx == 0) || (module_idx == 1)))
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lbw_rtr_id = DCORE0_RTR0;
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else
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lbw_rtr_id = gaudi2_tpc_initiator_lbw_rtr_id[module_idx];
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sprintf(initiator_name, "TPC_%u", module_idx);
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break;
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case RAZWI_MME:
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sprintf(initiator_name, "MME_%u", module_idx);
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switch (module_sub_idx) {
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case MME_WAP0:
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rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].wap0;
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hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].wap0;
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break;
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case MME_WAP1:
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rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].wap1;
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hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].wap1;
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break;
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case MME_WRITE:
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rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].write;
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hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].write;
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break;
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case MME_READ:
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rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].read;
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hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].read;
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break;
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case MME_SBTE0:
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rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte0;
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hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte0;
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break;
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case MME_SBTE1:
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rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte1;
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hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte1;
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break;
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case MME_SBTE2:
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rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte2;
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hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte2;
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break;
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case MME_SBTE3:
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rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte3;
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hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte3;
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break;
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case MME_SBTE4:
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rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte4;
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hbw_rtr_id = gaudi2_mme_initiator_rtr_id[module_idx].sbte4;
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break;
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default:
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return;
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}
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lbw_rtr_id = hbw_rtr_id;
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break;
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case RAZWI_EDMA:
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sft_id = gaudi2_edma_initiator_sft_id[module_idx].interface_id;
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@ -7237,19 +7273,23 @@ static void gaudi2_ack_module_razwi_event_handler(struct hl_device *hdev,
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sprintf(initiator_name, "EDMA_%u", module_idx);
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break;
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case RAZWI_PDMA:
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rtr_id = gaudi2_pdma_initiator_rtr_id[module_idx];
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hbw_rtr_id = gaudi2_pdma_initiator_hbw_rtr_id[module_idx];
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lbw_rtr_id = gaudi2_pdma_initiator_lbw_rtr_id[module_idx];
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sprintf(initiator_name, "PDMA_%u", module_idx);
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break;
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case RAZWI_NIC:
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rtr_id = gaudi2_nic_initiator_rtr_id[module_idx];
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hbw_rtr_id = gaudi2_nic_initiator_hbw_rtr_id[module_idx];
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lbw_rtr_id = gaudi2_nic_initiator_lbw_rtr_id[module_idx];
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sprintf(initiator_name, "NIC_%u", module_idx);
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break;
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case RAZWI_DEC:
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rtr_id = gaudi2_dec_initiator_rtr_id[module_idx];
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hbw_rtr_id = gaudi2_dec_initiator_hbw_rtr_id[module_idx];
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lbw_rtr_id = gaudi2_dec_initiator_lbw_rtr_id[module_idx];
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sprintf(initiator_name, "DEC_%u", module_idx);
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break;
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case RAZWI_ROT:
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rtr_id = gaudi2_rot_initiator_rtr_id[module_idx];
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hbw_rtr_id = gaudi2_rot_initiator_hbw_rtr_id[module_idx];
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lbw_rtr_id = gaudi2_rot_initiator_lbw_rtr_id[module_idx];
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sprintf(initiator_name, "ROT_%u", module_idx);
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break;
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default:
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@ -7258,22 +7298,25 @@ static void gaudi2_ack_module_razwi_event_handler(struct hl_device *hdev,
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/* Find router mstr_if register base */
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if (via_sft) {
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rtr_mstr_if_base_addr = mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE +
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hbw_rtr_mstr_if_base_addr = mmSFT0_HBW_RTR_IF0_RTR_CTRL_BASE +
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dcore_id * SFT_DCORE_OFFSET +
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sft_id * SFT_IF_OFFSET +
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RTR_MSTR_IF_OFFSET;
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lbw_rtr_mstr_if_base_addr = hbw_rtr_mstr_if_base_addr;
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} else {
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dcore_id = rtr_id / NUM_OF_RTR_PER_DCORE;
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dcore_rtr_id = rtr_id % NUM_OF_RTR_PER_DCORE;
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rtr_mstr_if_base_addr = mmDCORE0_RTR0_CTRL_BASE +
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dcore_id = hbw_rtr_id / NUM_OF_RTR_PER_DCORE;
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dcore_rtr_id = hbw_rtr_id % NUM_OF_RTR_PER_DCORE;
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hbw_rtr_mstr_if_base_addr = mmDCORE0_RTR0_CTRL_BASE +
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dcore_id * DCORE_OFFSET +
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dcore_rtr_id * DCORE_RTR_OFFSET +
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RTR_MSTR_IF_OFFSET;
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lbw_rtr_mstr_if_base_addr = hbw_rtr_mstr_if_base_addr +
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(((s32)lbw_rtr_id - hbw_rtr_id) * DCORE_RTR_OFFSET);
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}
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/* Find out event cause by reading "RAZWI_HAPPENED" registers */
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hbw_shrd_aw = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HAPPENED);
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hbw_shrd_ar = RREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HAPPENED);
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hbw_shrd_aw = RREG32(hbw_rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HAPPENED);
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hbw_shrd_ar = RREG32(hbw_rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HAPPENED);
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if (via_sft) {
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/* SFT has separate MSTR_IF for LBW, only there we can
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@ -7287,41 +7330,41 @@ static void gaudi2_ack_module_razwi_event_handler(struct hl_device *hdev,
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lbw_shrd_aw = RREG32(base + RR_SHRD_LBW_AW_RAZWI_HAPPENED);
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lbw_shrd_ar = RREG32(base + RR_SHRD_LBW_AR_RAZWI_HAPPENED);
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} else {
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lbw_shrd_aw = RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_HAPPENED);
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lbw_shrd_ar = RREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_HAPPENED);
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lbw_shrd_aw = RREG32(lbw_rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_HAPPENED);
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lbw_shrd_ar = RREG32(lbw_rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_HAPPENED);
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}
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eng_id = gaudi2_razwi_calc_engine_id(hdev, module, module_idx);
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if (hbw_shrd_aw) {
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gaudi2_razwi_rr_hbw_shared_printf_info(hdev, rtr_mstr_if_base_addr, true,
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gaudi2_razwi_rr_hbw_shared_printf_info(hdev, hbw_rtr_mstr_if_base_addr, true,
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initiator_name, eng_id, event_mask);
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/* Clear event indication */
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WREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HAPPENED, hbw_shrd_aw);
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WREG32(hbw_rtr_mstr_if_base_addr + RR_SHRD_HBW_AW_RAZWI_HAPPENED, hbw_shrd_aw);
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}
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if (hbw_shrd_ar) {
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gaudi2_razwi_rr_hbw_shared_printf_info(hdev, rtr_mstr_if_base_addr, false,
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gaudi2_razwi_rr_hbw_shared_printf_info(hdev, hbw_rtr_mstr_if_base_addr, false,
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initiator_name, eng_id, event_mask);
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/* Clear event indication */
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WREG32(rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HAPPENED, hbw_shrd_ar);
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WREG32(hbw_rtr_mstr_if_base_addr + RR_SHRD_HBW_AR_RAZWI_HAPPENED, hbw_shrd_ar);
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}
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if (lbw_shrd_aw) {
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gaudi2_razwi_rr_lbw_shared_printf_info(hdev, rtr_mstr_if_base_addr, true,
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gaudi2_razwi_rr_lbw_shared_printf_info(hdev, lbw_rtr_mstr_if_base_addr, true,
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initiator_name, eng_id, event_mask);
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/* Clear event indication */
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WREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_HAPPENED, lbw_shrd_aw);
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WREG32(lbw_rtr_mstr_if_base_addr + RR_SHRD_LBW_AW_RAZWI_HAPPENED, lbw_shrd_aw);
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}
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if (lbw_shrd_ar) {
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gaudi2_razwi_rr_lbw_shared_printf_info(hdev, rtr_mstr_if_base_addr, false,
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gaudi2_razwi_rr_lbw_shared_printf_info(hdev, lbw_rtr_mstr_if_base_addr, false,
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initiator_name, eng_id, event_mask);
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/* Clear event indication */
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WREG32(rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_HAPPENED, lbw_shrd_ar);
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WREG32(lbw_rtr_mstr_if_base_addr + RR_SHRD_LBW_AR_RAZWI_HAPPENED, lbw_shrd_ar);
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}
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}
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