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perf tool ibs: Sync AMD IBS header file
IBS support has been enhanced with two new features in upcoming uarch: 1. DataSrc extension 2. L3 miss filtering. Additional set of bits has been introduced in IBS registers to exploit these features. New bits are already defining in arch/x86/ header. Sync it with tools header file. Also rename existing ibs_op_data field 'data_src' to 'data_src_lo'. Signed-off-by: Ravi Bangoria <ravi.bangoria@amd.com> Acked-by: Namhyung Kim <namhyung@kernel.org> Cc: Ananth Narayan <ananth.narayan@amd.com> Cc: Andi Kleen <ak@linux.intel.com> Cc: Borislav Petkov <bp@alien8.de> Cc: Ian Rogers <irogers@google.com> Cc: Ingo Molnar <mingo@redhat.com> Cc: James Clark <james.clark@arm.com> Cc: Jiri Olsa <jolsa@kernel.org> Cc: Kan Liang <kan.liang@linux.intel.com> Cc: Kim Phillips <kim.phillips@amd.com> Cc: Leo Yan <leo.yan@linaro.org> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Robert Richter <rrichter@amd.com> Cc: Sandipan Das <sandipan.das@amd.com> Cc: Santosh Shukla <santosh.shukla@amd.com> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: like.xu.linux@gmail.com Cc: x86@kernel.org Link: https://lore.kernel.org/r/20220604044519.594-8-ravi.bangoria@amd.com Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
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@ -29,7 +29,10 @@ union ibs_fetch_ctl {
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rand_en:1, /* 57: random tagging enable */
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fetch_l2_miss:1,/* 58: L2 miss for sampled fetch
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* (needs IbsFetchComp) */
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reserved:5; /* 59-63: reserved */
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l3_miss_only:1, /* 59: Collect L3 miss samples only */
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fetch_oc_miss:1,/* 60: Op cache miss for the sampled fetch */
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fetch_l3_miss:1,/* 61: L3 cache miss for the sampled fetch */
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reserved:2; /* 62-63: reserved */
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};
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};
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@ -38,14 +41,14 @@ union ibs_op_ctl {
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__u64 val;
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struct {
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__u64 opmaxcnt:16, /* 0-15: periodic op max. count */
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reserved0:1, /* 16: reserved */
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l3_miss_only:1, /* 16: Collect L3 miss samples only */
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op_en:1, /* 17: op sampling enable */
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op_val:1, /* 18: op sample valid */
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cnt_ctl:1, /* 19: periodic op counter control */
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opmaxcnt_ext:7, /* 20-26: upper 7 bits of periodic op maximum count */
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reserved1:5, /* 27-31: reserved */
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reserved0:5, /* 27-31: reserved */
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opcurcnt:27, /* 32-58: periodic op counter current count */
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reserved2:5; /* 59-63: reserved */
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reserved1:5; /* 59-63: reserved */
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};
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};
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@ -71,11 +74,12 @@ union ibs_op_data {
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union ibs_op_data2 {
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__u64 val;
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struct {
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__u64 data_src:3, /* 0-2: data source */
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__u64 data_src_lo:3, /* 0-2: data source low */
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reserved0:1, /* 3: reserved */
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rmt_node:1, /* 4: destination node */
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cache_hit_st:1, /* 5: cache hit state */
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reserved1:57; /* 5-63: reserved */
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data_src_hi:2, /* 6-7: data source high */
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reserved1:56; /* 8-63: reserved */
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};
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};
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@ -98,9 +98,9 @@ static void pr_ibs_op_data2(union ibs_op_data2 reg)
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};
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printf("ibs_op_data2:\t%016llx %sRmtNode %d%s\n", reg.val,
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reg.data_src == 2 ? (reg.cache_hit_st ? "CacheHitSt 1=O-State "
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reg.data_src_lo == 2 ? (reg.cache_hit_st ? "CacheHitSt 1=O-State "
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: "CacheHitSt 0=M-state ") : "",
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reg.rmt_node, data_src_str[reg.data_src]);
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reg.rmt_node, data_src_str[reg.data_src_lo]);
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}
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static void pr_ibs_op_data3(union ibs_op_data3 reg)
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