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perf/x86: Fix format definition of SNB-EP uncore QPI box
The event control register of SNB-EP uncore QPI box has a one bit extension at bit position 21. Reported-by: Stephane Eranian <eranian@google.com> Signed-off-by: Yan, Zheng <zheng.z.yan@intel.com> Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Link: http://lkml.kernel.org/r/1343097850-4348-1-git-send-email-zheng.z.yan@intel.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -18,6 +18,7 @@ static struct event_constraint constraint_empty =
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EVENT_CONSTRAINT(0, 0, 0);
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EVENT_CONSTRAINT(0, 0, 0);
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DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
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DEFINE_UNCORE_FORMAT_ATTR(event, event, "config:0-7");
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DEFINE_UNCORE_FORMAT_ATTR(event_ext, event, "config:0-7,21");
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DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
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DEFINE_UNCORE_FORMAT_ATTR(umask, umask, "config:8-15");
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DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
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DEFINE_UNCORE_FORMAT_ATTR(edge, edge, "config:18");
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DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
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DEFINE_UNCORE_FORMAT_ATTR(tid_en, tid_en, "config:19");
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@ -293,6 +294,15 @@ static struct attribute *snbep_uncore_pcu_formats_attr[] = {
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NULL,
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NULL,
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};
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};
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static struct attribute *snbep_uncore_qpi_formats_attr[] = {
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&format_attr_event_ext.attr,
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&format_attr_umask.attr,
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&format_attr_edge.attr,
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&format_attr_inv.attr,
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&format_attr_thresh8.attr,
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NULL,
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};
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static struct uncore_event_desc snbep_uncore_imc_events[] = {
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static struct uncore_event_desc snbep_uncore_imc_events[] = {
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INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
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INTEL_UNCORE_EVENT_DESC(clockticks, "event=0xff,umask=0x00"),
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INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"),
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INTEL_UNCORE_EVENT_DESC(cas_count_read, "event=0x04,umask=0x03"),
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@ -328,6 +338,11 @@ static struct attribute_group snbep_uncore_pcu_format_group = {
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.attrs = snbep_uncore_pcu_formats_attr,
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.attrs = snbep_uncore_pcu_formats_attr,
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};
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};
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static struct attribute_group snbep_uncore_qpi_format_group = {
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.name = "format",
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.attrs = snbep_uncore_qpi_formats_attr,
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};
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static struct intel_uncore_ops snbep_uncore_msr_ops = {
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static struct intel_uncore_ops snbep_uncore_msr_ops = {
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.init_box = snbep_uncore_msr_init_box,
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.init_box = snbep_uncore_msr_init_box,
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.disable_box = snbep_uncore_msr_disable_box,
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.disable_box = snbep_uncore_msr_disable_box,
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@ -499,8 +514,13 @@ static struct intel_uncore_type snbep_uncore_qpi = {
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.num_counters = 4,
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.num_counters = 4,
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.num_boxes = 2,
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.num_boxes = 2,
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.perf_ctr_bits = 48,
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.perf_ctr_bits = 48,
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.perf_ctr = SNBEP_PCI_PMON_CTR0,
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.event_ctl = SNBEP_PCI_PMON_CTL0,
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.event_mask = SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK,
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.box_ctl = SNBEP_PCI_PMON_BOX_CTL,
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.ops = &snbep_uncore_pci_ops,
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.event_descs = snbep_uncore_qpi_events,
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.event_descs = snbep_uncore_qpi_events,
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SNBEP_UNCORE_PCI_COMMON_INIT(),
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.format_group = &snbep_uncore_qpi_format_group,
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};
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};
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@ -113,6 +113,10 @@
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SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
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SNBEP_PCU_MSR_PMON_CTL_OCC_INVERT | \
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SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
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SNBEP_PCU_MSR_PMON_CTL_OCC_EDGE_DET)
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#define SNBEP_QPI_PCI_PMON_RAW_EVENT_MASK \
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(SNBEP_PMON_RAW_EVENT_MASK | \
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SNBEP_PMON_CTL_EV_SEL_EXT)
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/* SNB-EP pci control register */
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/* SNB-EP pci control register */
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#define SNBEP_PCI_PMON_BOX_CTL 0xf4
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#define SNBEP_PCI_PMON_BOX_CTL 0xf4
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#define SNBEP_PCI_PMON_CTL0 0xd8
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#define SNBEP_PCI_PMON_CTL0 0xd8
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