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powerpc/powernv: Implement MSI support for p5ioc2 PCIe
This implements support for MSIs on p5ioc2 PHBs. We only support MSIs on the PCIe PHBs, not the PCI-X ones as the later hasn't been properly verified in HW. Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
This commit is contained in:
Benjamin Herrenschmidt
parent
61305a96fa
commit
c1a2562ac5
@ -19,6 +19,7 @@
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/msi.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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@ -39,6 +40,51 @@
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*/
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#define P5IOC2_TCE_MEMORY 0x01000000
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#ifdef CONFIG_PCI_MSI
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static int pnv_pci_p5ioc2_msi_setup(struct pnv_phb *phb, struct pci_dev *dev,
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unsigned int hwirq, unsigned int is_64,
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struct msi_msg *msg)
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{
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if (WARN_ON(!is_64))
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return -ENXIO;
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msg->data = hwirq - phb->msi_base;
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msg->address_hi = 0x10000000;
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msg->address_lo = 0;
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return 0;
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}
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static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb)
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{
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unsigned int bmap_size;
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const __be32 *prop = of_get_property(phb->hose->dn,
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"ibm,opal-msi-ranges", NULL);
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if (!prop)
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return;
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/* Don't do MSI's on p5ioc2 PCI-X are they are not properly
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* verified in HW
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*/
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if (of_device_is_compatible(phb->hose->dn, "ibm,p5ioc2-pcix"))
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return;
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phb->msi_base = be32_to_cpup(prop);
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phb->msi_count = be32_to_cpup(prop + 1);
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bmap_size = BITS_TO_LONGS(phb->msi_count) * sizeof(unsigned long);
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phb->msi_map = zalloc_maybe_bootmem(bmap_size, GFP_KERNEL);
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if (!phb->msi_map) {
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pr_err("PCI %d: Failed to allocate MSI bitmap !\n",
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phb->hose->global_number);
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return;
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}
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phb->msi_setup = pnv_pci_p5ioc2_msi_setup;
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phb->msi32_support = 0;
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pr_info(" Allocated bitmap for %d MSIs (base IRQ 0x%x)\n",
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phb->msi_count, phb->msi_base);
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}
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#else
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static void pnv_pci_init_p5ioc2_msis(struct pnv_phb *phb) { }
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#endif /* CONFIG_PCI_MSI */
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static void __devinit pnv_pci_p5ioc2_dma_dev_setup(struct pnv_phb *phb,
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struct pci_dev *pdev)
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{
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@ -117,6 +163,9 @@ static void __init pnv_pci_init_p5ioc2_phb(struct device_node *np,
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phb->hose->ops = &pnv_pci_ops;
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/* Setup MSI support */
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pnv_pci_init_p5ioc2_msis(phb);
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/* Setup TCEs */
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phb->dma_dev_setup = pnv_pci_p5ioc2_dma_dev_setup;
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pnv_pci_setup_iommu_table(&phb->p5ioc2.iommu_table,
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@ -19,6 +19,7 @@
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#include <linux/bootmem.h>
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#include <linux/irq.h>
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#include <linux/io.h>
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#include <linux/msi.h>
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#include <asm/sections.h>
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#include <asm/io.h>
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@ -38,6 +39,108 @@
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#define cfg_dbg(fmt...) do { } while(0)
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//#define cfg_dbg(fmt...) printk(fmt)
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#ifdef CONFIG_PCI_MSI
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static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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return (phb && phb->msi_map) ? 0 : -ENODEV;
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}
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static unsigned int pnv_get_one_msi(struct pnv_phb *phb)
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{
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unsigned int id;
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spin_lock(&phb->lock);
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id = find_next_zero_bit(phb->msi_map, phb->msi_count, phb->msi_next);
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if (id >= phb->msi_count && phb->msi_next)
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id = find_next_zero_bit(phb->msi_map, phb->msi_count, 0);
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if (id >= phb->msi_count) {
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spin_unlock(&phb->lock);
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return 0;
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}
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__set_bit(id, phb->msi_map);
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spin_unlock(&phb->lock);
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return id + phb->msi_base;
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}
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static void pnv_put_msi(struct pnv_phb *phb, unsigned int hwirq)
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{
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unsigned int id;
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if (WARN_ON(hwirq < phb->msi_base ||
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hwirq >= (phb->msi_base + phb->msi_count)))
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return;
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id = hwirq - phb->msi_base;
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spin_lock(&phb->lock);
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__clear_bit(id, phb->msi_map);
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spin_unlock(&phb->lock);
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}
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static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct msi_desc *entry;
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struct msi_msg msg;
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unsigned int hwirq, virq;
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int rc;
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if (WARN_ON(!phb))
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return -ENODEV;
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list_for_each_entry(entry, &pdev->msi_list, list) {
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if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
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pr_warn("%s: Supports only 64-bit MSIs\n",
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pci_name(pdev));
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return -ENXIO;
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}
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hwirq = pnv_get_one_msi(phb);
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if (!hwirq) {
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pr_warn("%s: Failed to find a free MSI\n",
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pci_name(pdev));
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return -ENOSPC;
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}
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virq = irq_create_mapping(NULL, hwirq);
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if (virq == NO_IRQ) {
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pr_warn("%s: Failed to map MSI to linux irq\n",
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pci_name(pdev));
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pnv_put_msi(phb, hwirq);
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return -ENOMEM;
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}
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rc = phb->msi_setup(phb, pdev, hwirq, entry->msi_attrib.is_64,
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&msg);
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if (rc) {
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pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
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irq_dispose_mapping(virq);
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pnv_put_msi(phb, hwirq);
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return rc;
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}
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irq_set_msi_desc(virq, entry);
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write_msi_msg(virq, &msg);
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}
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return 0;
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}
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static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
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{
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struct pci_controller *hose = pci_bus_to_host(pdev->bus);
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struct pnv_phb *phb = hose->private_data;
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struct msi_desc *entry;
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if (WARN_ON(!phb))
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return;
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list_for_each_entry(entry, &pdev->msi_list, list) {
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if (entry->irq == NO_IRQ)
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continue;
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irq_set_msi_desc(entry->irq, NULL);
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pnv_put_msi(phb, virq_to_hw(entry->irq));
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irq_dispose_mapping(entry->irq);
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}
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}
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#endif /* CONFIG_PCI_MSI */
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static void pnv_pci_config_check_eeh(struct pnv_phb *phb, struct pci_bus *bus,
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u32 bdfn)
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@ -283,4 +386,10 @@ void __init pnv_pci_init(void)
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ppc_md.tce_free = pnv_tce_free;
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set_pci_dma_ops(&dma_iommu_ops);
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/* Configure MSIs */
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#ifdef CONFIG_PCI_MSI
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ppc_md.msi_check_device = pnv_msi_check_device;
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ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
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ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
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#endif
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}
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@ -16,6 +16,16 @@ struct pnv_phb {
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void __iomem *regs;
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spinlock_t lock;
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#ifdef CONFIG_PCI_MSI
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unsigned long *msi_map;
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unsigned int msi_base;
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unsigned int msi_count;
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unsigned int msi_next;
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unsigned int msi32_support;
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#endif
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int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
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unsigned int hwirq, unsigned int is_64,
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struct msi_msg *msg);
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void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
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void (*fixup_phb)(struct pci_controller *hose);
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u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
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