korg/linux
0
0
Fork 0
mirror of https://mirrors.bfsu.edu.cn/git/linux.git synced 2024-12-02 16:44:10 +08:00
Code Issues Packages Projects Releases Wiki Activity

arm: dts: mt7623: add PCIe related nodes

Browse Source 
This patch adds some device nodes for the PCIe function block and updates
related pinmux.

Moreover, we add interrupt-map properties in both parent and children as
the chip only has one IRQ per slot that is connected to all INTx and get
propagated through the bridges and it also represents the root ports own
interrupts.

Signed-off-by: Ryder Lee <ryder.lee@mediatek.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
This commit is contained in:
Ryder Lee 2018-02-14 11:27:34 +08:00 committed by Matthias Brugger
parent 58b369679e
commit c10a98c4f6
2 changed files with 135 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

105
arch/arm/boot/dts/mt7623.dtsi
View File

@ -679,6 +679,111 @@
#reset-cells = <1>; #reset-cells = <1>;
}; };
pcie: pcie@1a140000 {
compatible = "mediatek,mt7623-pcie";
device_type = "pci";
reg = <0 0x1a140000 0 0x1000>, /* PCIe shared registers */
<0 0x1a142000 0 0x1000>, /* Port0 registers */
<0 0x1a143000 0 0x1000>, /* Port1 registers */
<0 0x1a144000 0 0x1000>; /* Port2 registers */
reg-names = "subsys", "port0", "port1", "port2";
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0xf800 0 0 0>;
interrupt-map = <0x0000 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>,
<0x0800 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>,
<0x1000 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
<&hifsys CLK_HIFSYS_PCIE0>,
<&hifsys CLK_HIFSYS_PCIE1>,
<&hifsys CLK_HIFSYS_PCIE2>;
clock-names = "free_ck", "sys_ck0", "sys_ck1", "sys_ck2";
resets = <&hifsys MT2701_HIFSYS_PCIE0_RST>,
<&hifsys MT2701_HIFSYS_PCIE1_RST>,
<&hifsys MT2701_HIFSYS_PCIE2_RST>;
reset-names = "pcie-rst0", "pcie-rst1", "pcie-rst2";
phys = <&pcie0_port PHY_TYPE_PCIE>,
<&pcie1_port PHY_TYPE_PCIE>,
<&u3port1 PHY_TYPE_PCIE>;
phy-names = "pcie-phy0", "pcie-phy1", "pcie-phy2";
power-domains = <&scpsys MT2701_POWER_DOMAIN_HIF>;
bus-range = <0x00 0xff>;
status = "disabled";
ranges = <0x81000000 0 0x1a160000 0 0x1a160000 0 0x00010000
0x83000000 0 0x60000000 0 0x60000000 0 0x10000000>;
pcie@0,0 {
reg = <0x0000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 193 IRQ_TYPE_LEVEL_LOW>;
ranges;
num-lanes = <1>;
status = "disabled";
};
pcie@1,0 {
reg = <0x0800 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 194 IRQ_TYPE_LEVEL_LOW>;
ranges;
num-lanes = <1>;
status = "disabled";
};
pcie@2,0 {
reg = <0x1000 0 0 0 0>;
#address-cells = <3>;
#size-cells = <2>;
#interrupt-cells = <1>;
interrupt-map-mask = <0 0 0 0>;
interrupt-map = <0 0 0 0 &sysirq GIC_SPI 195 IRQ_TYPE_LEVEL_LOW>;
ranges;
num-lanes = <1>;
status = "disabled";
};
};
pcie0_phy: pcie-phy@1a149000 {
compatible = "mediatek,generic-tphy-v1";
reg = <0 0x1a149000 0 0x0700>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
pcie0_port: pcie-phy@1a149900 {
reg = <0 0x1a149900 0 0x0700>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
};
pcie1_phy: pcie-phy@1a14a000 {
compatible = "mediatek,generic-tphy-v1";
reg = <0 0x1a14a000 0 0x0700>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
status = "disabled";
pcie1_port: pcie-phy@1a14a900 {
reg = <0 0x1a14a900 0 0x0700>;
clocks = <&clk26m>;
clock-names = "ref";
#phy-cells = <1>;
status = "okay";
};
};
usb1: usb@1a1c0000 { usb1: usb@1a1c0000 {
compatible = "mediatek,mt7623-xhci", compatible = "mediatek,mt7623-xhci",
"mediatek,mt8173-xhci"; "mediatek,mt8173-xhci";

30
arch/arm/boot/dts/mt7623n-bananapi-bpi-r2.dts
View File

@ -235,6 +235,28 @@
vqmmc-supply = <&reg_3p3v>; vqmmc-supply = <&reg_3p3v>;
}; };
&pcie {
pinctrl-names = "default";
pinctrl-0 = <&pcie_default>;
status = "okay";
pcie@0,0 {
status = "okay";
};
pcie@1,0 {
status = "okay";
};
};
&pcie0_phy {
status = "okay";
};
&pcie1_phy {
status = "okay";
};
&pio { &pio {
cir_pins_a:cir@0 { cir_pins_a:cir@0 {
pins-cir { pins-cir {
@ -402,6 +424,14 @@
}; };
}; };
pcie_default: pcie_pin_default {
pins_cmd_dat {
pinmux = <MT7623_PIN_208_AUD_EXT_CK1_FUNC_PCIE0_PERST_N>,
<MT7623_PIN_209_AUD_EXT_CK2_FUNC_PCIE1_PERST_N>;
bias-disable;
};
};
pwm_pins_a: pwm@0 { pwm_pins_a: pwm@0 {
pins-pwm { pins-pwm {
pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>, pinmux = <MT7623_PIN_203_PWM0_FUNC_PWM0>,