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ARM: SoC fixes for v5.19, part 2

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Another set of minor patches for Arm DTS files and soc specific drivers:
 
  - More reference counting bug fixes for DT nodes, and other
    trivial code fixes
 
  - Multiple code fixes for the Arm SCMI firmware driver to improve
    compatibility with firmware implementations.
 
  - A patch series for at91 to address power management issues from
    using the wrong DT compatible properties.
 
  - A series of patches to fix pad settings for NXP imx8mp to leave the
    configuration untouched from the boot loader
 
  - Additional DT fixes for qualcomm and NXP platforms
 
  - A boot time fix for stm32mp15 DT
 
  - Konrad Dybcio becomes an additional reviewer for the Qualcomm
    platforms
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Merge tag 'soc-fixes-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC fixes from Arnd Bergmann:
 "Another set of minor patches for Arm DTS files and soc specific
  drivers:

   - More reference counting bug fixes for DT nodes, and other trivial
     code fixes

   - Multiple code fixes for the Arm SCMI firmware driver to improve
     compatibility with firmware implementations.

   - A patch series for at91 to address power management issues from
     using the wrong DT compatible properties.

   - A series of patches to fix pad settings for NXP imx8mp to leave the
     configuration untouched from the boot loader

   - Additional DT fixes for qualcomm and NXP platforms

   - A boot time fix for stm32mp15 DT

   - Konrad Dybcio becomes an additional reviewer for the Qualcomm
     platforms"

* tag 'soc-fixes-5.19-2' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (42 commits)
  soc: qcom: smem: use correct format characters
  ARM: dts: stm32: add missing usbh clock and fix clk order on stm32mp15
  ARM: dts: stm32: delete fixed clock node on STM32MP15-SCMI
  ARM: dts: stm32: DSI should use LSE SCMI clock on DK1/ED1 STM32 board
  ARM: dts: stm32: use the correct clock source for CEC on stm32mp151
  ARM: dts: stm32: fix pwr regulators references to use scmi
  soc: ixp4xx/npe: Fix unused match warning
  ARM: at91: pm: Mark at91_pm_secure_init as __init
  ARM: at91: fix soc detection for SAM9X60 SiPs
  ARM: dts: at91: sama5d2_icp: fix eeprom compatibles
  ARM: dts: at91: sam9x60ek: fix eeprom compatible and size
  ARM: at91: pm: use proper compatibles for sama7g5's rtc and rtt
  ARM: at91: pm: use proper compatibles for sam9x60's rtc and rtt
  ARM: at91: pm: use proper compatible for sama5d2's rtc
  arm64: dts: qcom: msm8992-*: Fix vdd_lvs1_2-supply typo
  firmware: arm_scmi: Remove usage of the deprecated ida_simple_xxx API
  firmware: arm_scmi: Fix response size warning for OPTEE transport
  arm64: dts: imx8mp-icore-mx8mp-edim2.2: correct pad settings
  arm64: dts: imx8mp-phyboard-pollux-rdk: correct i2c2 & mmc settings
  arm64: dts: imx8mp-phyboard-pollux-rdk: correct eqos pad settings
  ...
This commit is contained in:
Linus Torvalds 2022-07-04 10:41:59 -07:00
commit c1084b6c56
33 changed files with 300 additions and 188 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
MAINTAINERS
View File

@ -2540,6 +2540,7 @@ W: http://www.armlinux.org.uk/
ARM/QUALCOMM SUPPORT ARM/QUALCOMM SUPPORT
M: Andy Gross <agross@kernel.org> M: Andy Gross <agross@kernel.org>
M: Bjorn Andersson <bjorn.andersson@linaro.org> M: Bjorn Andersson <bjorn.andersson@linaro.org>
R: Konrad Dybcio <konrad.dybcio@somainline.org>
L: linux-arm-msm@vger.kernel.org L: linux-arm-msm@vger.kernel.org
S: Maintained S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git T: git git://git.kernel.org/pub/scm/linux/kernel/git/qcom/linux.git

3
arch/arm/boot/dts/at91-sam9x60ek.dts
View File

@ -233,10 +233,9 @@
status = "okay"; status = "okay";
eeprom@53 { eeprom@53 {
compatible = "atmel,24c32"; compatible = "atmel,24c02";
reg = <0x53>; reg = <0x53>;
pagesize = <16>; pagesize = <16>;
size = <128>;
status = "okay"; status = "okay";
}; };
}; };

6
arch/arm/boot/dts/at91-sama5d2_icp.dts
View File

@ -329,21 +329,21 @@
status = "okay"; status = "okay";
eeprom@50 { eeprom@50 {
compatible = "atmel,24c32"; compatible = "atmel,24c02";
reg = <0x50>; reg = <0x50>;
pagesize = <16>; pagesize = <16>;
status = "okay"; status = "okay";
}; };
eeprom@52 { eeprom@52 {
compatible = "atmel,24c32"; compatible = "atmel,24c02";
reg = <0x52>; reg = <0x52>;
pagesize = <16>; pagesize = <16>;
status = "disabled"; status = "disabled";
}; };
eeprom@53 { eeprom@53 {
compatible = "atmel,24c32"; compatible = "atmel,24c02";
reg = <0x53>; reg = <0x53>;
pagesize = <16>; pagesize = <16>;
status = "disabled"; status = "disabled";

4
arch/arm/boot/dts/imx7d-smegw01.dts
View File

@ -216,10 +216,8 @@
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_usdhc2>; pinctrl-0 = <&pinctrl_usdhc2>;
bus-width = <4>; bus-width = <4>;
no-1-8-v;
non-removable; non-removable;
cap-sd-highspeed;
sd-uhs-ddr50;
mmc-ddr-1_8v;
vmmc-supply = <&reg_wifi>; vmmc-supply = <&reg_wifi>;
enable-sdio-wakeup; enable-sdio-wakeup;
status = "okay"; status = "okay";

58
arch/arm/boot/dts/stm32mp15-scmi.dtsi
View File

@ -27,6 +27,37 @@
reg = <0x16>; reg = <0x16>;
#reset-cells = <1>; #reset-cells = <1>;
}; };
scmi_voltd: protocol@17 {
reg = <0x17>;
scmi_reguls: regulators {
#address-cells = <1>;
#size-cells = <0>;
scmi_reg11: reg11@0 {
reg = <0>;
regulator-name = "reg11";
regulator-min-microvolt = <1100000>;
regulator-max-microvolt = <1100000>;
};
scmi_reg18: reg18@1 {
voltd-name = "reg18";
reg = <1>;
regulator-name = "reg18";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <1800000>;
};
scmi_usb33: usb33@2 {
reg = <2>;
regulator-name = "usb33";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
};
};
};
}; };
}; };
@ -45,3 +76,30 @@
}; };
}; };
}; };
&reg11 {
status = "disabled";
};
&reg18 {
status = "disabled";
};
&usb33 {
status = "disabled";
};
&usbotg_hs {
usb33d-supply = <&scmi_usb33>;
};
&usbphyc {
vdda1v1-supply = <&scmi_reg11>;
vdda1v8-supply = <&scmi_reg18>;
};
/delete-node/ &clk_hse;
/delete-node/ &clk_hsi;
/delete-node/ &clk_lse;
/delete-node/ &clk_lsi;
/delete-node/ &clk_csi;

6
arch/arm/boot/dts/stm32mp151.dtsi
View File

@ -565,7 +565,7 @@
compatible = "st,stm32-cec"; compatible = "st,stm32-cec";
reg = <0x40016000 0x400>; reg = <0x40016000 0x400>;
interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&rcc CEC_K>, <&clk_lse>; clocks = <&rcc CEC_K>, <&rcc CEC>;
clock-names = "cec", "hdmi-cec"; clock-names = "cec", "hdmi-cec";
status = "disabled"; status = "disabled";
}; };
@ -1474,7 +1474,7 @@
usbh_ohci: usb@5800c000 { usbh_ohci: usb@5800c000 {
compatible = "generic-ohci"; compatible = "generic-ohci";
reg = <0x5800c000 0x1000>; reg = <0x5800c000 0x1000>;
clocks = <&rcc USBH>, <&usbphyc>; clocks = <&usbphyc>, <&rcc USBH>;
resets = <&rcc USBH_R>; resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled"; status = "disabled";
@ -1483,7 +1483,7 @@
usbh_ehci: usb@5800d000 { usbh_ehci: usb@5800d000 {
compatible = "generic-ehci"; compatible = "generic-ehci";
reg = <0x5800d000 0x1000>; reg = <0x5800d000 0x1000>;
clocks = <&rcc USBH>; clocks = <&usbphyc>, <&rcc USBH>;
resets = <&rcc USBH_R>; resets = <&rcc USBH_R>;
interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
companion = <&usbh_ohci>; companion = <&usbh_ohci>;

4
arch/arm/boot/dts/stm32mp157a-dk1-scmi.dts
View File

@ -29,6 +29,10 @@
clocks = <&scmi_clk CK_SCMI_MPU>; clocks = <&scmi_clk CK_SCMI_MPU>;
}; };
&dsi {
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz { &gpioz {
clocks = <&scmi_clk CK_SCMI_GPIOZ>; clocks = <&scmi_clk CK_SCMI_GPIOZ>;
}; };

1
arch/arm/boot/dts/stm32mp157c-dk2-scmi.dts
View File

@ -35,6 +35,7 @@
}; };
&dsi { &dsi {
phy-dsi-supply = <&scmi_reg18>;
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
}; };

4
arch/arm/boot/dts/stm32mp157c-ed1-scmi.dts
View File

@ -34,6 +34,10 @@
resets = <&scmi_reset RST_SCMI_CRYP1>; resets = <&scmi_reset RST_SCMI_CRYP1>;
}; };
&dsi {
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
};
&gpioz { &gpioz {
clocks = <&scmi_clk CK_SCMI_GPIOZ>; clocks = <&scmi_clk CK_SCMI_GPIOZ>;
}; };

1
arch/arm/boot/dts/stm32mp157c-ev1-scmi.dts
View File

@ -36,6 +36,7 @@
}; };
&dsi { &dsi {
phy-dsi-supply = <&scmi_reg18>;
clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; clocks = <&rcc DSI_K>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>;
}; };

1
arch/arm/configs/mxs_defconfig
View File

@ -93,6 +93,7 @@ CONFIG_REGULATOR_FIXED_VOLTAGE=y
CONFIG_DRM=y CONFIG_DRM=y
CONFIG_DRM_PANEL_SEIKO_43WVF1G=y CONFIG_DRM_PANEL_SEIKO_43WVF1G=y
CONFIG_DRM_MXSFB=y CONFIG_DRM_MXSFB=y
CONFIG_FB=y
CONFIG_FB_MODE_HELPERS=y CONFIG_FB_MODE_HELPERS=y
CONFIG_LCD_CLASS_DEVICE=y CONFIG_LCD_CLASS_DEVICE=y
CONFIG_BACKLIGHT_CLASS_DEVICE=y CONFIG_BACKLIGHT_CLASS_DEVICE=y

12
arch/arm/mach-at91/pm.c
View File

@ -202,7 +202,7 @@ static const struct wakeup_source_info ws_info[] = {
static const struct of_device_id sama5d2_ws_ids[] = { static const struct of_device_id sama5d2_ws_ids[] = {
{ .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] }, { .compatible = "atmel,sama5d2-gem", .data = &ws_info[0] },
{ .compatible = "atmel,at91rm9200-rtc", .data = &ws_info[1] }, { .compatible = "atmel,sama5d2-rtc", .data = &ws_info[1] },
{ .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] }, { .compatible = "atmel,sama5d3-udc", .data = &ws_info[2] },
{ .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
{ .compatible = "usb-ohci", .data = &ws_info[2] }, { .compatible = "usb-ohci", .data = &ws_info[2] },
@ -213,24 +213,24 @@ static const struct of_device_id sama5d2_ws_ids[] = {
}; };
static const struct of_device_id sam9x60_ws_ids[] = { static const struct of_device_id sam9x60_ws_ids[] = {
{ .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, { .compatible = "microchip,sam9x60-rtc", .data = &ws_info[1] },
{ .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] }, { .compatible = "atmel,at91rm9200-ohci", .data = &ws_info[2] },
{ .compatible = "usb-ohci", .data = &ws_info[2] }, { .compatible = "usb-ohci", .data = &ws_info[2] },
{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
{ .compatible = "usb-ehci", .data = &ws_info[2] }, { .compatible = "usb-ehci", .data = &ws_info[2] },
{ .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, { .compatible = "microchip,sam9x60-rtt", .data = &ws_info[4] },
{ .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] }, { .compatible = "cdns,sam9x60-macb", .data = &ws_info[5] },
{ /* sentinel */ } { /* sentinel */ }
}; };
static const struct of_device_id sama7g5_ws_ids[] = { static const struct of_device_id sama7g5_ws_ids[] = {
{ .compatible = "atmel,at91sam9x5-rtc", .data = &ws_info[1] }, { .compatible = "microchip,sama7g5-rtc", .data = &ws_info[1] },
{ .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] }, { .compatible = "microchip,sama7g5-ohci", .data = &ws_info[2] },
{ .compatible = "usb-ohci", .data = &ws_info[2] }, { .compatible = "usb-ohci", .data = &ws_info[2] },
{ .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] }, { .compatible = "atmel,at91sam9g45-ehci", .data = &ws_info[2] },
{ .compatible = "usb-ehci", .data = &ws_info[2] }, { .compatible = "usb-ehci", .data = &ws_info[2] },
{ .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] }, { .compatible = "microchip,sama7g5-sdhci", .data = &ws_info[3] },
{ .compatible = "atmel,at91sam9260-rtt", .data = &ws_info[4] }, { .compatible = "microchip,sama7g5-rtt", .data = &ws_info[4] },
{ /* sentinel */ } { /* sentinel */ }
}; };
@ -1079,7 +1079,7 @@ securam_fail:
return ret; return ret;
} }
static void at91_pm_secure_init(void) static void __init at91_pm_secure_init(void)
{ {
int suspend_mode; int suspend_mode;
struct arm_smccc_res res; struct arm_smccc_res res;

2
arch/arm/mach-meson/platsmp.c
View File

@ -71,6 +71,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible,
} }
sram_base = of_iomap(node, 0); sram_base = of_iomap(node, 0);
of_node_put(node);
if (!sram_base) { if (!sram_base) {
pr_err("Couldn't map SRAM registers\n"); pr_err("Couldn't map SRAM registers\n");
return; return;
@ -91,6 +92,7 @@ static void __init meson_smp_prepare_cpus(const char *scu_compatible,
} }
scu_base = of_iomap(node, 0); scu_base = of_iomap(node, 0);
of_node_put(node);
if (!scu_base) { if (!scu_base) {
pr_err("Couldn't map SCU registers\n"); pr_err("Couldn't map SCU registers\n");
return; return;

88
arch/arm64/boot/dts/freescale/imx8mp-evk.dts
View File

@ -395,41 +395,41 @@
&iomuxc { &iomuxc {
pinctrl_eqos: eqosgrp { pinctrl_eqos: eqosgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x19 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10
>; >;
}; };
pinctrl_fec: fecgrp { pinctrl_fec: fecgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x3 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2
MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x3 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x19 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10
>; >;
}; };
@ -461,28 +461,28 @@
pinctrl_gpio_led: gpioledgrp { pinctrl_gpio_led: gpioledgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x19 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 0x140
>; >;
}; };
pinctrl_i2c1: i2c1grp { pinctrl_i2c1: i2c1grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>; >;
}; };
pinctrl_i2c3: i2c3grp { pinctrl_i2c3: i2c3grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>; >;
}; };
pinctrl_i2c5: i2c5grp { pinctrl_i2c5: i2c5grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c3 MX8MP_IOMUXC_SPDIF_RX__I2C5_SDA 0x400001c2
MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c3 MX8MP_IOMUXC_SPDIF_TX__I2C5_SCL 0x400001c2
>; >;
}; };
@ -500,20 +500,20 @@
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>; >;
}; };
pinctrl_uart2: uart2grp { pinctrl_uart2: uart2grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x140
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x140
>; >;
}; };
pinctrl_usb1_vbus: usb1grp { pinctrl_usb1_vbus: usb1grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x19 MX8MP_IOMUXC_GPIO1_IO14__USB2_OTG_PWR 0x10
>; >;
}; };
@ -525,7 +525,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>; >;
}; };
@ -537,7 +537,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>; >;
}; };
@ -549,7 +549,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>; >;
}; };

40
arch/arm64/boot/dts/freescale/imx8mp-icore-mx8mp-edimm2.2.dts
View File

@ -110,28 +110,28 @@
&iomuxc { &iomuxc {
pinctrl_eqos: eqosgrp { pinctrl_eqos: eqosgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x19 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x10
>; >;
}; };
pinctrl_uart2: uart2grp { pinctrl_uart2: uart2grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x49 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX 0x40
MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x49 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX 0x40
>; >;
}; };
@ -151,7 +151,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>; >;
}; };
@ -163,13 +163,13 @@
pinctrl_reg_usb1: regusb1grp { pinctrl_reg_usb1: regusb1grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x19 MX8MP_IOMUXC_GPIO1_IO14__GPIO1_IO14 0x10
>; >;
}; };
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>; >;
}; };
}; };

48
arch/arm64/boot/dts/freescale/imx8mp-phyboard-pollux-rdk.dts
View File

@ -116,48 +116,48 @@
&iomuxc { &iomuxc {
pinctrl_eqos: eqosgrp { pinctrl_eqos: eqosgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x10
>; >;
}; };
pinctrl_i2c2: i2c2grp { pinctrl_i2c2: i2c2grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>; >;
}; };
pinctrl_i2c2_gpio: i2c2gpiogrp { pinctrl_i2c2_gpio: i2c2gpiogrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e3 MX8MP_IOMUXC_I2C2_SCL__GPIO5_IO16 0x1e2
MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e3 MX8MP_IOMUXC_I2C2_SDA__GPIO5_IO17 0x1e2
>; >;
}; };
pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x41 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40
>; >;
}; };
pinctrl_uart1: uart1grp { pinctrl_uart1: uart1grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x49 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x40
MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x49 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x40
>; >;
}; };
@ -175,7 +175,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>; >;
}; };
@ -187,7 +187,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>; >;
}; };
@ -199,7 +199,7 @@
MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6
MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6
MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6
MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0
>; >;
}; };
}; };

116
arch/arm64/boot/dts/freescale/imx8mp-venice-gw74xx.dts
View File

@ -622,15 +622,15 @@
pinctrl_hog: hoggrp { pinctrl_hog: hoggrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000041 /* DIO0 */ MX8MP_IOMUXC_GPIO1_IO09__GPIO1_IO09 0x40000040 /* DIO0 */
MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000041 /* DIO1 */ MX8MP_IOMUXC_GPIO1_IO11__GPIO1_IO11 0x40000040 /* DIO1 */
MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000041 /* M2SKT_OFF# */ MX8MP_IOMUXC_NAND_DQS__GPIO3_IO14 0x40000040 /* M2SKT_OFF# */
MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000159 /* PCIE1_WDIS# */ MX8MP_IOMUXC_SD2_DATA2__GPIO2_IO17 0x40000150 /* PCIE1_WDIS# */
MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000159 /* PCIE2_WDIS# */ MX8MP_IOMUXC_SD2_DATA3__GPIO2_IO18 0x40000150 /* PCIE2_WDIS# */
MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000159 /* PCIE3_WDIS# */ MX8MP_IOMUXC_SD2_CMD__GPIO2_IO14 0x40000150 /* PCIE3_WDIS# */
MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000041 /* M2SKT_RST# */ MX8MP_IOMUXC_NAND_DATA00__GPIO3_IO06 0x40000040 /* M2SKT_RST# */
MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000159 /* M2SKT_WDIS# */ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x40000150 /* M2SKT_WDIS# */
MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000159 /* M2SKT_GDIS# */ MX8MP_IOMUXC_NAND_ALE__GPIO3_IO00 0x40000150 /* M2SKT_GDIS# */
MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */ MX8MP_IOMUXC_SAI3_TXD__GPIO5_IO01 0x40000104 /* UART_TERM */
MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */ MX8MP_IOMUXC_SAI3_TXFS__GPIO4_IO31 0x40000104 /* UART_RS485 */
MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */ MX8MP_IOMUXC_SAI3_TXC__GPIO5_IO00 0x40000104 /* UART_HALF */
@ -639,47 +639,47 @@
pinctrl_accel: accelgrp { pinctrl_accel: accelgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x159 MX8MP_IOMUXC_GPIO1_IO07__GPIO1_IO07 0x150
>; >;
}; };
pinctrl_eqos: eqosgrp { pinctrl_eqos: eqosgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x3 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2
MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x3 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2
MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x91 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90
MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x91 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90
MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x91 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90
MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x91 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90
MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x91 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90
MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x91 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x1f MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16
MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x1f MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16
MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x1f MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16
MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x1f MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16
MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x1f MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16
MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x141 /* RST# */ MX8MP_IOMUXC_SAI3_RXD__GPIO4_IO30 0x140 /* RST# */
MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x159 /* IRQ# */ MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x150 /* IRQ# */
>; >;
}; };
pinctrl_fec: fecgrp { pinctrl_fec: fecgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x91 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90
MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x1f MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x1f MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x1f MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x1f MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x1f MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x1f MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16
MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x141 MX8MP_IOMUXC_SAI1_RXFS__ENET1_1588_EVENT0_IN 0x140
MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x141 MX8MP_IOMUXC_SAI1_RXC__ENET1_1588_EVENT0_OUT 0x140
>; >;
}; };
@ -692,61 +692,61 @@
pinctrl_gsc: gscgrp { pinctrl_gsc: gscgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x159 MX8MP_IOMUXC_SAI1_MCLK__GPIO4_IO20 0x150
>; >;
}; };
pinctrl_i2c1: i2c1grp { pinctrl_i2c1: i2c1grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c2
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c2
>; >;
}; };
pinctrl_i2c2: i2c2grp { pinctrl_i2c2: i2c2grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c3 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL 0x400001c2
MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c3 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA 0x400001c2
>; >;
}; };
pinctrl_i2c3: i2c3grp { pinctrl_i2c3: i2c3grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c3 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL 0x400001c2
MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c3 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA 0x400001c2
>; >;
}; };
pinctrl_i2c4: i2c4grp { pinctrl_i2c4: i2c4grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c3 MX8MP_IOMUXC_I2C4_SCL__I2C4_SCL 0x400001c2
MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c3 MX8MP_IOMUXC_I2C4_SDA__I2C4_SDA 0x400001c2
>; >;
}; };
pinctrl_ksz: kszgrp { pinctrl_ksz: kszgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x159 /* IRQ# */ MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x150 /* IRQ# */
MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x141 /* RST# */ MX8MP_IOMUXC_SAI3_MCLK__GPIO5_IO02 0x140 /* RST# */
>; >;
}; };
pinctrl_gpio_leds: ledgrp { pinctrl_gpio_leds: ledgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x19 MX8MP_IOMUXC_SD2_DATA0__GPIO2_IO15 0x10
MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x19 MX8MP_IOMUXC_SD2_DATA1__GPIO2_IO16 0x10
>; >;
}; };
pinctrl_pmic: pmicgrp { pinctrl_pmic: pmicgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x141 MX8MP_IOMUXC_NAND_DATA01__GPIO3_IO07 0x140
>; >;
}; };
pinctrl_pps: ppsgrp { pinctrl_pps: ppsgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x141 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x140
>; >;
}; };
@ -758,13 +758,13 @@
pinctrl_reg_usb2: regusb2grp { pinctrl_reg_usb2: regusb2grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x141 MX8MP_IOMUXC_GPIO1_IO06__GPIO1_IO06 0x140
>; >;
}; };
pinctrl_reg_wifi: regwifigrp { pinctrl_reg_wifi: regwifigrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x119 MX8MP_IOMUXC_NAND_DATA03__GPIO3_IO09 0x110
>; >;
}; };
@ -811,7 +811,7 @@
pinctrl_uart3_gpio: uart3gpiogrp { pinctrl_uart3_gpio: uart3gpiogrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x119 MX8MP_IOMUXC_NAND_DATA02__GPIO3_IO08 0x110
>; >;
}; };

2
arch/arm64/boot/dts/freescale/imx8mp.dtsi
View File

@ -595,7 +595,7 @@
pgc_ispdwp: power-domain@18 { pgc_ispdwp: power-domain@18 {
#power-domain-cells = <0>; #power-domain-cells = <0>;
reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>; reg = <IMX8MP_POWER_DOMAIN_MEDIAMIX_ISPDWP>;
clocks = <&clk IMX8MP_CLK_MEDIA_ISP_DIV>; clocks = <&clk IMX8MP_CLK_MEDIA_ISP_ROOT>;
}; };
}; };
}; };

2
arch/arm64/boot/dts/qcom/msm8992-lg-bullhead.dtsi
View File

@ -74,7 +74,7 @@
vdd_l17_29-supply = <&vph_pwr>; vdd_l17_29-supply = <&vph_pwr>;
vdd_l20_21-supply = <&vph_pwr>; vdd_l20_21-supply = <&vph_pwr>;
vdd_l25-supply = <&pm8994_s5>; vdd_l25-supply = <&pm8994_s5>;
vdd_lvs1_2 = <&pm8994_s4>; vdd_lvs1_2-supply = <&pm8994_s4>;
/* S1, S2, S6 and S12 are managed by RPMPD */ /* S1, S2, S6 and S12 are managed by RPMPD */

2
arch/arm64/boot/dts/qcom/msm8992-xiaomi-libra.dts
View File

@ -171,7 +171,7 @@
vdd_l17_29-supply = <&vph_pwr>; vdd_l17_29-supply = <&vph_pwr>;
vdd_l20_21-supply = <&vph_pwr>; vdd_l20_21-supply = <&vph_pwr>;
vdd_l25-supply = <&pm8994_s5>; vdd_l25-supply = <&pm8994_s5>;
vdd_lvs1_2 = <&pm8994_s4>; vdd_lvs1_2-supply = <&pm8994_s4>;
/* S1, S2, S6 and S12 are managed by RPMPD */ /* S1, S2, S6 and S12 are managed by RPMPD */

4
arch/arm64/boot/dts/qcom/msm8994.dtsi
View File

@ -100,7 +100,7 @@
CPU6: cpu@102 { CPU6: cpu@102 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x0 0x101>; reg = <0x0 0x102>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
}; };
@ -108,7 +108,7 @@
CPU7: cpu@103 { CPU7: cpu@103 {
device_type = "cpu"; device_type = "cpu";
compatible = "arm,cortex-a57"; compatible = "arm,cortex-a57";
reg = <0x0 0x101>; reg = <0x0 0x103>;
enable-method = "psci"; enable-method = "psci";
next-level-cache = <&L2_1>; next-level-cache = <&L2_1>;
}; };

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-homestar.dtsi
View File

@ -5,7 +5,7 @@
* Copyright 2021 Google LLC. * Copyright 2021 Google LLC.
*/ */
#include "sc7180-trogdor.dtsi" /* This file must be included after sc7180-trogdor.dtsi */
/ { / {
/* BOARD-SPECIFIC TOP LEVEL NODES */ /* BOARD-SPECIFIC TOP LEVEL NODES */

2
arch/arm64/boot/dts/qcom/sc7180-trogdor-lazor.dtsi
View File

@ -5,7 +5,7 @@
* Copyright 2020 Google LLC. * Copyright 2020 Google LLC.
*/ */
#include "sc7180-trogdor.dtsi" /* This file must be included after sc7180-trogdor.dtsi */
&ap_sar_sensor { &ap_sar_sensor {
semtech,cs0-ground; semtech,cs0-ground;

2
arch/arm64/boot/dts/qcom/sdm845.dtsi
View File

@ -4244,7 +4244,7 @@
power-domains = <&dispcc MDSS_GDSC>; power-domains = <&dispcc MDSS_GDSC>;
clocks = <&gcc GCC_DISP_AHB_CLK>, clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
<&dispcc DISP_CC_MDSS_MDP_CLK>; <&dispcc DISP_CC_MDSS_MDP_CLK>;
clock-names = "iface", "core"; clock-names = "iface", "core";

14
arch/arm64/boot/dts/qcom/sm8450.dtsi
View File

@ -2853,6 +2853,16 @@
reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */ reg = <0x0 0x17100000 0x0 0x10000>, /* GICD */
<0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */ <0x0 0x17180000 0x0 0x200000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
#address-cells = <2>;
#size-cells = <2>;
ranges;
gic_its: msi-controller@17140000 {
compatible = "arm,gic-v3-its";
reg = <0x0 0x17140000 0x0 0x20000>;
msi-controller;
#msi-cells = <1>;
};
}; };
timer@17420000 { timer@17420000 {
@ -3037,8 +3047,8 @@
iommus = <&apps_smmu 0xe0 0x0>; iommus = <&apps_smmu 0xe0 0x0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>, interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>; <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
interconnect-names = "ufs-ddr", "cpu-ufs"; interconnect-names = "ufs-ddr", "cpu-ufs";
clock-names = clock-names =
"core_clk", "core_clk",

6
drivers/firmware/arm_scmi/bus.c
View File

@ -181,7 +181,7 @@ scmi_device_create(struct device_node *np, struct device *parent, int protocol,
return NULL; return NULL;
} }
id = ida_simple_get(&scmi_bus_id, 1, 0, GFP_KERNEL); id = ida_alloc_min(&scmi_bus_id, 1, GFP_KERNEL);
if (id < 0) { if (id < 0) {
kfree_const(scmi_dev->name); kfree_const(scmi_dev->name);
kfree(scmi_dev); kfree(scmi_dev);
@ -204,7 +204,7 @@ scmi_device_create(struct device_node *np, struct device *parent, int protocol,
put_dev: put_dev:
kfree_const(scmi_dev->name); kfree_const(scmi_dev->name);
put_device(&scmi_dev->dev); put_device(&scmi_dev->dev);
ida_simple_remove(&scmi_bus_id, id); ida_free(&scmi_bus_id, id);
return NULL; return NULL;
} }
@ -212,7 +212,7 @@ void scmi_device_destroy(struct scmi_device *scmi_dev)
{ {
kfree_const(scmi_dev->name); kfree_const(scmi_dev->name);
scmi_handle_put(scmi_dev->handle); scmi_handle_put(scmi_dev->handle);
ida_simple_remove(&scmi_bus_id, scmi_dev->id); ida_free(&scmi_bus_id, scmi_dev->id);
device_unregister(&scmi_dev->dev); device_unregister(&scmi_dev->dev);
} }

26
drivers/firmware/arm_scmi/clock.c
View File

@ -194,6 +194,7 @@ static int rate_cmp_func(const void *_r1, const void *_r2)
} }
struct scmi_clk_ipriv { struct scmi_clk_ipriv {
struct device *dev;
u32 clk_id; u32 clk_id;
struct scmi_clock_info *clk; struct scmi_clock_info *clk;
}; };
@ -223,6 +224,29 @@ iter_clk_describe_update_state(struct scmi_iterator_state *st,
st->num_returned = NUM_RETURNED(flags); st->num_returned = NUM_RETURNED(flags);
p->clk->rate_discrete = RATE_DISCRETE(flags); p->clk->rate_discrete = RATE_DISCRETE(flags);
/* Warn about out of spec replies ... */
if (!p->clk->rate_discrete &&
(st->num_returned != 3 || st->num_remaining != 0)) {
dev_warn(p->dev,
"Out-of-spec CLOCK_DESCRIBE_RATES reply for %s - returned:%d remaining:%d rx_len:%zd\n",
p->clk->name, st->num_returned, st->num_remaining,
st->rx_len);
/*
* A known quirk: a triplet is returned but num_returned != 3
* Check for a safe payload size and fix.
*/
if (st->num_returned != 3 && st->num_remaining == 0 &&
st->rx_len == sizeof(*r) + sizeof(__le32) * 2 * 3) {
st->num_returned = 3;
st->num_remaining = 0;
} else {
dev_err(p->dev,
"Cannot fix out-of-spec reply !\n");
return -EPROTO;
}
}
return 0; return 0;
} }
@ -255,7 +279,6 @@ iter_clk_describe_process_response(const struct scmi_protocol_handle *ph,
*rate = RATE_TO_U64(r->rate[st->loop_idx]); *rate = RATE_TO_U64(r->rate[st->loop_idx]);
p->clk->list.num_rates++; p->clk->list.num_rates++;
//XXX dev_dbg(ph->dev, "Rate %llu Hz\n", *rate);
} }
return ret; return ret;
@ -275,6 +298,7 @@ scmi_clock_describe_rates_get(const struct scmi_protocol_handle *ph, u32 clk_id,
struct scmi_clk_ipriv cpriv = { struct scmi_clk_ipriv cpriv = {
.clk_id = clk_id, .clk_id = clk_id,
.clk = clk, .clk = clk,
.dev = ph->dev,
}; };
iter = ph->hops->iter_response_init(ph, &ops, SCMI_MAX_NUM_RATES, iter = ph->hops->iter_response_init(ph, &ops, SCMI_MAX_NUM_RATES,

1
drivers/firmware/arm_scmi/driver.c
View File

@ -1223,6 +1223,7 @@ static int scmi_iterator_run(void *iter)
if (ret) if (ret)
break; break;
st->rx_len = i->t->rx.len;
ret = iops->update_state(st, i->resp, i->priv); ret = iops->update_state(st, i->resp, i->priv);
if (ret) if (ret)
break; break;

7
drivers/firmware/arm_scmi/optee.c
View File

@ -117,6 +117,7 @@ struct scmi_optee_channel {
u32 channel_id; u32 channel_id;
u32 tee_session; u32 tee_session;
u32 caps; u32 caps;
u32 rx_len;
struct mutex mu; struct mutex mu;
struct scmi_chan_info *cinfo; struct scmi_chan_info *cinfo;
union { union {
@ -302,6 +303,9 @@ static int invoke_process_msg_channel(struct scmi_optee_channel *channel, size_t
return -EIO; return -EIO;
} }
/* Save response size */
channel->rx_len = param[2].u.memref.size;
return 0; return 0;
} }
@ -353,6 +357,7 @@ static int setup_dynamic_shmem(struct device *dev, struct scmi_optee_channel *ch
shbuf = tee_shm_get_va(channel->tee_shm, 0); shbuf = tee_shm_get_va(channel->tee_shm, 0);
memset(shbuf, 0, msg_size); memset(shbuf, 0, msg_size);
channel->req.msg = shbuf; channel->req.msg = shbuf;
channel->rx_len = msg_size;
return 0; return 0;
} }
@ -508,7 +513,7 @@ static void scmi_optee_fetch_response(struct scmi_chan_info *cinfo,
struct scmi_optee_channel *channel = cinfo->transport_info; struct scmi_optee_channel *channel = cinfo->transport_info;
if (channel->tee_shm) if (channel->tee_shm)
msg_fetch_response(channel->req.msg, SCMI_OPTEE_MAX_MSG_SIZE, xfer); msg_fetch_response(channel->req.msg, channel->rx_len, xfer);
else else
shmem_fetch_response(channel->req.shmem, xfer); shmem_fetch_response(channel->req.shmem, xfer);
} }

3
drivers/firmware/arm_scmi/protocols.h
View File

@ -179,6 +179,8 @@ struct scmi_protocol_handle {
* @max_resources: Maximum acceptable number of items, configured by the caller * @max_resources: Maximum acceptable number of items, configured by the caller
* depending on the underlying resources that it is querying. * depending on the underlying resources that it is querying.
* @loop_idx: The iterator loop index in the current multi-part reply. * @loop_idx: The iterator loop index in the current multi-part reply.
* @rx_len: Size in bytes of the currenly processed message; it can be used by
* the user of the iterator to verify a reply size.
* @priv: Optional pointer to some additional state-related private data setup * @priv: Optional pointer to some additional state-related private data setup
* by the caller during the iterations. * by the caller during the iterations.
*/ */
@ -188,6 +190,7 @@ struct scmi_iterator_state {
unsigned int num_remaining; unsigned int num_remaining;
unsigned int max_resources; unsigned int max_resources;
unsigned int loop_idx; unsigned int loop_idx;
size_t rx_len;
void *priv; void *priv;
}; };

12
drivers/soc/atmel/soc.c
View File

@ -91,14 +91,14 @@ static const struct at91_soc socs[] __initconst = {
AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK, AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH,
"sam9x60", "sam9x60"), "sam9x60", "sam9x60"),
AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D5M_EXID_MATCH, AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, AT91_CIDR_VERSION_MASK, SAM9X60_D5M_EXID_MATCH,
"sam9x60 64MiB DDR2 SiP", "sam9x60"), "sam9x60 64MiB DDR2 SiP", "sam9x60"),
AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D1G_EXID_MATCH, AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, AT91_CIDR_VERSION_MASK, SAM9X60_D1G_EXID_MATCH,
"sam9x60 128MiB DDR2 SiP", "sam9x60"), "sam9x60 128MiB DDR2 SiP", "sam9x60"),
AT91_SOC(SAM9X60_CIDR_MATCH, SAM9X60_D6K_EXID_MATCH, AT91_SOC(SAM9X60_CIDR_MATCH, AT91_CIDR_MATCH_MASK,
AT91_CIDR_VERSION_MASK, SAM9X60_EXID_MATCH, AT91_CIDR_VERSION_MASK, SAM9X60_D6K_EXID_MATCH,
"sam9x60 8MiB SDRAM SiP", "sam9x60"), "sam9x60 8MiB SDRAM SiP", "sam9x60"),
#endif #endif
#ifdef CONFIG_SOC_SAMA5 #ifdef CONFIG_SOC_SAMA5

2
drivers/soc/ixp4xx/ixp4xx-npe.c
View File

@ -758,7 +758,7 @@ static const struct of_device_id ixp4xx_npe_of_match[] = {
static struct platform_driver ixp4xx_npe_driver = { static struct platform_driver ixp4xx_npe_driver = {
.driver = { .driver = {
.name = "ixp4xx-npe", .name = "ixp4xx-npe",
.of_match_table = of_match_ptr(ixp4xx_npe_of_match), .of_match_table = ixp4xx_npe_of_match,
}, },
.probe = ixp4xx_npe_probe, .probe = ixp4xx_npe_probe,
.remove = ixp4xx_npe_remove, .remove = ixp4xx_npe_remove,

6
drivers/soc/qcom/smem.c
View File

@ -926,7 +926,7 @@ qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host)
struct smem_partition_header *header; struct smem_partition_header *header;
struct smem_ptable_entry *entry; struct smem_ptable_entry *entry;
struct smem_ptable *ptable; struct smem_ptable *ptable;
unsigned int remote_host; u16 remote_host;
u16 host0, host1; u16 host0, host1;
int i; int i;
@ -951,12 +951,12 @@ qcom_smem_enumerate_partitions(struct qcom_smem *smem, u16 local_host)
continue; continue;
if (remote_host >= SMEM_HOST_COUNT) { if (remote_host >= SMEM_HOST_COUNT) {
dev_err(smem->dev, "bad host %hu\n", remote_host); dev_err(smem->dev, "bad host %u\n", remote_host);
return -EINVAL; return -EINVAL;
} }
if (smem->partitions[remote_host].virt_base) { if (smem->partitions[remote_host].virt_base) {
dev_err(smem->dev, "duplicate host %hu\n", remote_host); dev_err(smem->dev, "duplicate host %u\n", remote_host);
return -EINVAL; return -EINVAL;
} }