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ARM: dts: exynos: Add audio power domain to Exynos5250
Audio power domain includes following hardware modules: Pin controller for GPZ bank, AudioSS clock controller and three Exynos I2S controller. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
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@ -136,6 +136,13 @@
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clock-names = "oscclk", "clk0", "clk1";
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};
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pd_mau: power-domain@100440C0 {
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compatible = "samsung,exynos4210-pd";
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reg = <0x100440C0 0x20>;
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#power-domain-cells = <0>;
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label = "MAU";
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};
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clock: clock-controller@10010000 {
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compatible = "samsung,exynos5250-clock";
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reg = <0x10010000 0x30000>;
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@ -149,6 +156,7 @@
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clocks = <&clock CLK_FIN_PLL>, <&clock CLK_FOUT_EPLL>,
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<&clock CLK_SCLK_AUDIO0>, <&clock CLK_DIV_PCM0>;
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clock-names = "pll_ref", "pll_in", "sclk_audio", "sclk_pcm_in";
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power-domains = <&pd_mau>;
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};
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timer {
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@ -223,6 +231,7 @@
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compatible = "samsung,exynos5250-pinctrl";
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reg = <0x03860000 0x1000>;
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interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
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power-domains = <&pd_mau>;
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};
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pmu_system_controller: system-controller@10040000 {
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@ -486,6 +495,7 @@
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samsung,idma-addr = <0x03000000>;
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pinctrl-names = "default";
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pinctrl-0 = <&i2s0_bus>;
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power-domains = <&pd_mau>;
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};
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i2s1: i2s@12D60000 {
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@ -499,6 +509,7 @@
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clock-names = "iis", "i2s_opclk0";
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pinctrl-names = "default";
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pinctrl-0 = <&i2s1_bus>;
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power-domains = <&pd_mau>;
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};
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i2s2: i2s@12D70000 {
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@ -512,6 +523,7 @@
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clock-names = "iis", "i2s_opclk0";
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pinctrl-names = "default";
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pinctrl-0 = <&i2s2_bus>;
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power-domains = <&pd_mau>;
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};
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usb_dwc3 {
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