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NTB: switchtec: Add NTB hardware register definitions
There are two additional regions: ctrl and dbmsg. The first is for generic NTB control and memory windows. The second is for doorbells and message registers. This patch also adds a number of related constants for using these registers. Signed-off-by: Logan Gunthorpe <logang@deltatee.com> Reviewed-by: Stephen Bates <sbates@raithlin.com> Reviewed-by: Kurt Schwemmer <kurt.schwemmer@microsemi.com> Signed-off-by: Jon Mason <jdmason@kudzu.us>
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@ -156,6 +156,12 @@ struct flash_info_regs {
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struct partition_info vendor[8];
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};
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enum {
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SWITCHTEC_NTB_REG_INFO_OFFSET = 0x0000,
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SWITCHTEC_NTB_REG_CTRL_OFFSET = 0x4000,
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SWITCHTEC_NTB_REG_DBMSG_OFFSET = 0x64000,
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};
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struct ntb_info_regs {
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u8 partition_count;
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u8 partition_id;
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@ -190,6 +196,84 @@ struct part_cfg_regs {
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u32 reserved4[159];
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} __packed;
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enum {
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NTB_CTRL_PART_OP_LOCK = 0x1,
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NTB_CTRL_PART_OP_CFG = 0x2,
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NTB_CTRL_PART_OP_RESET = 0x3,
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NTB_CTRL_PART_STATUS_NORMAL = 0x1,
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NTB_CTRL_PART_STATUS_LOCKED = 0x2,
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NTB_CTRL_PART_STATUS_LOCKING = 0x3,
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NTB_CTRL_PART_STATUS_CONFIGURING = 0x4,
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NTB_CTRL_PART_STATUS_RESETTING = 0x5,
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NTB_CTRL_BAR_VALID = 1 << 0,
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NTB_CTRL_BAR_DIR_WIN_EN = 1 << 4,
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NTB_CTRL_BAR_LUT_WIN_EN = 1 << 5,
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NTB_CTRL_REQ_ID_EN = 1 << 0,
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NTB_CTRL_LUT_EN = 1 << 0,
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NTB_PART_CTRL_ID_PROT_DIS = 1 << 0,
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};
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struct ntb_ctrl_regs {
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u32 partition_status;
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u32 partition_op;
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u32 partition_ctrl;
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u32 bar_setup;
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u32 bar_error;
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u16 lut_table_entries;
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u16 lut_table_offset;
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u32 lut_error;
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u16 req_id_table_size;
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u16 req_id_table_offset;
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u32 req_id_error;
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u32 reserved1[7];
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struct {
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u32 ctl;
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u32 win_size;
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u64 xlate_addr;
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} bar_entry[6];
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u32 reserved2[216];
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u32 req_id_table[256];
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u32 reserved3[512];
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u64 lut_entry[512];
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} __packed;
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#define NTB_DBMSG_IMSG_STATUS BIT_ULL(32)
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#define NTB_DBMSG_IMSG_MASK BIT_ULL(40)
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struct ntb_dbmsg_regs {
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u32 reserved1[1024];
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u64 odb;
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u64 odb_mask;
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u64 idb;
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u64 idb_mask;
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u8 idb_vec_map[64];
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u32 msg_map;
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u32 reserved2;
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struct {
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u32 msg;
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u32 status;
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} omsg[4];
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struct {
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u32 msg;
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u8 status;
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u8 mask;
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u8 src;
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u8 reserved;
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} imsg[4];
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u8 reserved3[3928];
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u8 msix_table[1024];
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u8 reserved4[3072];
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u8 pba[24];
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u8 reserved5[4072];
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} __packed;
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enum {
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SWITCHTEC_PART_CFG_EVENT_RESET = 1 << 0,
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SWITCHTEC_PART_CFG_EVENT_MRPC_CMP = 1 << 1,
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