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riscv: dts: renesas: rzfive-smarc: Enable the blocks which were explicitly disabled

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Now that noncoherent dma support for the RZ/Five SoC has been added, enable
the IP blocks which were disabled on the RZ/Five SMARC.  This adds
support for the below peripherals:
  * Ethernet
  * DMAC
  * SDHI
  * USB
  * RSPI
  * SSI

Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20230929000704.53217-4-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
This commit is contained in:
Lad Prabhakar 2023-09-29 01:07:02 +01:00 committed by Geert Uytterhoeven
parent 9e40584dc2
commit bfef0760d2
2 changed files with 0 additions and 79 deletions
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23
arch/riscv/boot/dts/renesas/rzfive-smarc-som.dtsi
View File

@ -7,25 +7,8 @@
#include <arm64/renesas/rzg2ul-smarc-som.dtsi>
/ {
aliases {
/delete-property/ ethernet0;
/delete-property/ ethernet1;
};
chosen {
bootargs = "ignore_loglevel";
};
};
&dmac {
status = "disabled";
};
#if (!SW_ET0_EN_N)
&eth0 {
status = "disabled";
phy0: ethernet-phy@7 {
/delete-property/ interrupt-parent;
/delete-property/ interrupts;
@ -34,14 +17,8 @@
#endif
&eth1 {
status = "disabled";
phy1: ethernet-phy@7 {
/delete-property/ interrupt-parent;
/delete-property/ interrupts;
};
};
&sdhi0 {
status = "disabled";
};

56
arch/riscv/boot/dts/renesas/rzfive-smarc.dtsi
View File

@ -6,59 +6,3 @@
*/
#include <arm64/renesas/rzg2ul-smarc.dtsi>
&ehci0 {
status = "disabled";
};
&ehci1 {
status = "disabled";
};
&hsusb {
status = "disabled";
};
&ohci0 {
status = "disabled";
};
&ohci1 {
status = "disabled";
};
&phyrst {
status = "disabled";
};
&sdhi1 {
status = "disabled";
};
&snd_rzg2l {
status = "disabled";
};
&spi1 {
status = "disabled";
};
&ssi1 {
status = "disabled";
};
&usb0_vbus_otg {
status = "disabled";
};
&usb2_phy0 {
status = "disabled";
};
&usb2_phy1 {
status = "disabled";
};
&vccq_sdhi1 {
status = "disabled";
};