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clk: zynq: clkc: Remove various instances of an unused variable 'clk'
Fixes the following W=1 kernel build warning(s): drivers/clk/zynq/clkc.c: In function ‘zynq_clk_register_fclk’: drivers/clk/zynq/clkc.c:106:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] drivers/clk/zynq/clkc.c: In function ‘zynq_clk_register_periph_clk’: drivers/clk/zynq/clkc.c:179:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] drivers/clk/zynq/clkc.c: In function ‘zynq_clk_setup’: drivers/clk/zynq/clkc.c:220:14: warning: variable ‘clk’ set but not used [-Wunused-but-set-variable] Cc: Michael Turquette <mturquette@baylibre.com> Cc: Stephen Boyd <sboyd@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com> Cc: linux-clk@vger.kernel.org Cc: linux-arm-kernel@lists.infradead.org Signed-off-by: Lee Jones <lee.jones@linaro.org> Link: https://lore.kernel.org/r/20210120093040.1719407-21-lee.jones@linaro.org Signed-off-by: Stephen Boyd <sboyd@kernel.org>
This commit is contained in:
Lee Jones
Stephen Boyd
parent
0c1d46d3a7
commit
bf2244ba9d
@ -103,7 +103,6 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
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const char *clk_name, void __iomem *fclk_ctrl_reg,
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const char **parents, int enable)
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{
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struct clk *clk;
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u32 enable_reg;
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char *mux_name;
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char *div0_name;
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@ -131,15 +130,15 @@ static void __init zynq_clk_register_fclk(enum zynq_clk fclk,
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if (!div1_name)
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goto err_div1_name;
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clk = clk_register_mux(NULL, mux_name, parents, 4,
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clk_register_mux(NULL, mux_name, parents, 4,
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CLK_SET_RATE_NO_REPARENT, fclk_ctrl_reg, 4, 2, 0,
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fclk_lock);
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clk = clk_register_divider(NULL, div0_name, mux_name,
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clk_register_divider(NULL, div0_name, mux_name,
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0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, fclk_lock);
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clk = clk_register_divider(NULL, div1_name, div0_name,
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clk_register_divider(NULL, div1_name, div0_name,
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CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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fclk_lock);
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@ -176,7 +175,6 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
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const char *clk_name1, void __iomem *clk_ctrl,
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const char **parents, unsigned int two_gates)
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{
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struct clk *clk;
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char *mux_name;
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char *div_name;
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spinlock_t *lock;
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@ -189,10 +187,10 @@ static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0,
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mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0);
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div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0);
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clk = clk_register_mux(NULL, mux_name, parents, 4,
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clk_register_mux(NULL, mux_name, parents, 4,
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CLK_SET_RATE_NO_REPARENT, clk_ctrl, 4, 2, 0, lock);
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clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
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clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock);
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clks[clk0] = clk_register_gate(NULL, clk_name0, div_name,
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@ -217,7 +215,6 @@ static void __init zynq_clk_setup(struct device_node *np)
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int i;
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u32 tmp;
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int ret;
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struct clk *clk;
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char *clk_name;
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unsigned int fclk_enable = 0;
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const char *clk_output_name[clk_max];
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@ -257,19 +254,19 @@ static void __init zynq_clk_setup(struct device_node *np)
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ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, 0, tmp);
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/* PLLs */
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clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
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clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL,
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SLCR_PLL_STATUS, 0, &armpll_lock);
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clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll],
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armpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
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SLCR_ARMPLL_CTRL, 4, 1, 0, &armpll_lock);
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clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
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clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL,
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SLCR_PLL_STATUS, 1, &ddrpll_lock);
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clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll],
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ddrpll_parents, 2, CLK_SET_RATE_NO_REPARENT,
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SLCR_DDRPLL_CTRL, 4, 1, 0, &ddrpll_lock);
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clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
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clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL,
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SLCR_PLL_STATUS, 2, &iopll_lock);
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clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll],
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iopll_parents, 2, CLK_SET_RATE_NO_REPARENT,
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@ -277,10 +274,10 @@ static void __init zynq_clk_setup(struct device_node *np)
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/* CPU clocks */
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tmp = readl(SLCR_621_TRUE) & 1;
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clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
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clk_register_mux(NULL, "cpu_mux", cpu_parents, 4,
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CLK_SET_RATE_NO_REPARENT, SLCR_ARM_CLK_CTRL, 4, 2, 0,
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&armclk_lock);
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clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
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clk_register_divider(NULL, "cpu_div", "cpu_mux", 0,
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SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &armclk_lock);
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@ -288,20 +285,20 @@ static void __init zynq_clk_setup(struct device_node *np)
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"cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED,
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SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock);
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clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
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clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0,
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1, 2);
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clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x],
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"cpu_3or2x_div", CLK_IGNORE_UNUSED,
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SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock);
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clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
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clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1,
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2 + tmp);
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clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x],
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"cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL,
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26, 0, &armclk_lock);
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clk_prepare_enable(clks[cpu_2x]);
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clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
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clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1,
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4 + 2 * tmp);
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clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x],
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"cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27,
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@ -324,23 +321,23 @@ static void __init zynq_clk_setup(struct device_node *np)
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&swdtclk_lock);
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/* DDR clocks */
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clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
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clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0,
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SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
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clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x],
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"ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock);
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clk_prepare_enable(clks[ddr2x]);
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clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
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clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0,
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SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock);
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clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x],
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"ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock);
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clk_prepare_enable(clks[ddr3x]);
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clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
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clk_register_divider(NULL, "dci_div0", "ddrpll", 0,
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SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock);
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clk = clk_register_divider(NULL, "dci_div1", "dci_div0",
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clk_register_divider(NULL, "dci_div1", "dci_div0",
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CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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&dciclk_lock);
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@ -385,17 +382,17 @@ static void __init zynq_clk_setup(struct device_node *np)
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gem0_mux_parents[i + 1] = of_clk_get_parent_name(np,
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idx);
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}
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clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
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clk_register_mux(NULL, "gem0_mux", periph_parents, 4,
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CLK_SET_RATE_NO_REPARENT, SLCR_GEM0_CLK_CTRL, 4, 2, 0,
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&gem0clk_lock);
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clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
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clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0,
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SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock);
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clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0",
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clk_register_divider(NULL, "gem0_div1", "gem0_div0",
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CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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&gem0clk_lock);
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clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
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clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SLCR_GEM0_CLK_CTRL, 6, 1, 0,
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&gem0clk_lock);
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@ -410,17 +407,17 @@ static void __init zynq_clk_setup(struct device_node *np)
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gem1_mux_parents[i + 1] = of_clk_get_parent_name(np,
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idx);
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}
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clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
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clk_register_mux(NULL, "gem1_mux", periph_parents, 4,
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CLK_SET_RATE_NO_REPARENT, SLCR_GEM1_CLK_CTRL, 4, 2, 0,
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&gem1clk_lock);
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clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
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clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0,
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SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock);
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clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0",
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clk_register_divider(NULL, "gem1_div1", "gem1_div0",
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CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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&gem1clk_lock);
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clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
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clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2,
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CLK_SET_RATE_PARENT | CLK_SET_RATE_NO_REPARENT,
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SLCR_GEM1_CLK_CTRL, 6, 1, 0,
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&gem1clk_lock);
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@ -442,27 +439,27 @@ static void __init zynq_clk_setup(struct device_node *np)
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can_mio_mux_parents[i] = dummy_nm;
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}
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kfree(clk_name);
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clk = clk_register_mux(NULL, "can_mux", periph_parents, 4,
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clk_register_mux(NULL, "can_mux", periph_parents, 4,
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CLK_SET_RATE_NO_REPARENT, SLCR_CAN_CLK_CTRL, 4, 2, 0,
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&canclk_lock);
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clk = clk_register_divider(NULL, "can_div0", "can_mux", 0,
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clk_register_divider(NULL, "can_div0", "can_mux", 0,
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SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &canclk_lock);
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clk = clk_register_divider(NULL, "can_div1", "can_div0",
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clk_register_divider(NULL, "can_div1", "can_div0",
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CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6,
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CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO,
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&canclk_lock);
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clk = clk_register_gate(NULL, "can0_gate", "can_div1",
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clk_register_gate(NULL, "can0_gate", "can_div1",
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CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0,
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&canclk_lock);
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clk = clk_register_gate(NULL, "can1_gate", "can_div1",
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clk_register_gate(NULL, "can1_gate", "can_div1",
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CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0,
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&canclk_lock);
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clk = clk_register_mux(NULL, "can0_mio_mux",
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clk_register_mux(NULL, "can0_mio_mux",
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can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
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CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 0, 6, 0,
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&canmioclk_lock);
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clk = clk_register_mux(NULL, "can1_mio_mux",
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clk_register_mux(NULL, "can1_mio_mux",
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can_mio_mux_parents, 54, CLK_SET_RATE_PARENT |
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CLK_SET_RATE_NO_REPARENT, SLCR_CAN_MIOCLK_CTRL, 16, 6,
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0, &canmioclk_lock);
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@ -482,13 +479,13 @@ static void __init zynq_clk_setup(struct device_node *np)
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dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np,
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idx);
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}
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clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
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clk_register_mux(NULL, "dbg_mux", periph_parents, 4,
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CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 4, 2, 0,
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&dbgclk_lock);
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clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
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clk_register_divider(NULL, "dbg_div", "dbg_mux", 0,
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SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED |
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CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock);
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clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
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clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2,
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CLK_SET_RATE_NO_REPARENT, SLCR_DBG_CLK_CTRL, 6, 1, 0,
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&dbgclk_lock);
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clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc],
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