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perf vendor events intel: Update event list for haswellx

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Update JSON core/uncore events for haswellx to perf.

Based on HSX JSON list v24:

https://download.01.org/perfmon/HSX

Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Signed-off-by: Xing Zhengjun <zhengjun.xing@linux.intel.com>
Cc: Alexander Shishkin <alexander.shishkin@intel.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ian Rogers <irogers@google.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Link: https://lore.kernel.org/r/20220614145019.2177071-2-zhengjun.xing@linux.intel.com
Signed-off-by: Arnaldo Carvalho de Melo <acme@redhat.com>
This commit is contained in:
Zhengjun Xing 2022-06-14 22:50:19 +08:00 committed by Arnaldo Carvalho de Melo
parent 28738de918
commit bedd17381b
12 changed files with 11459 additions and 215 deletions
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37
tools/perf/pmu-events/arch/x86/haswellx/cache.json
View File

@ -832,9 +832,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0244",
"MSRValue": "0x4003C0244",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -847,7 +846,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -858,9 +856,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0091",
"MSRValue": "0x4003C0091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -873,7 +870,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C07F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -884,9 +880,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C07F7",
"MSRValue": "0x4003C07F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -899,7 +894,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C8FFF",
"Offcore": "1",
"PublicDescription": "Counts all requests hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -912,7 +906,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0122",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -923,9 +916,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0122",
"MSRValue": "0x4003C0122",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch RFOs hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -938,7 +930,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0004",
"Offcore": "1",
"PublicDescription": "Counts all demand code reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -949,9 +940,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0004",
"MSRValue": "0x4003C0004",
"Offcore": "1",
"PublicDescription": "Counts all demand code reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -964,7 +954,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0001",
"Offcore": "1",
"PublicDescription": "Counts demand data reads hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -975,9 +964,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0001",
"MSRValue": "0x4003C0001",
"Offcore": "1",
"PublicDescription": "Counts demand data reads hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -990,7 +978,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x10003C0002",
"Offcore": "1",
"PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoop to one of the sibling cores hits the line in M state and the line is forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -1001,9 +988,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_HIT.HIT_OTHER_CORE_NO_FWD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x04003C0002",
"MSRValue": "0x4003C0002",
"Offcore": "1",
"PublicDescription": "Counts all demand data writes (RFOs) hit in the L3 and the snoops to sibling cores hit in either E/S state and the line is not forwarded",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -1016,7 +1002,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0040",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -1029,7 +1014,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0010",
"Offcore": "1",
"PublicDescription": "Counts prefetch (that bring data to L2) data reads hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -1042,7 +1026,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0020",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to L2) RFOs hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -1055,7 +1038,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0200",
"Offcore": "1",
"PublicDescription": "Counts prefetch (that bring data to LLC only) code reads hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -1068,7 +1050,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0080",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -1081,7 +1062,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3F803C0100",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs hit in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -1091,7 +1071,8 @@
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "SQ_MISC.SPLIT_LOCK",
"SampleAfterValue": "100003",
"UMask": "0x10"
}
]
]

2
tools/perf/pmu-events/arch/x86/haswellx/floating-point.json
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@ -100,4 +100,4 @@
"SampleAfterValue": "100003",
"UMask": "0x10"
}
]
]

2
tools/perf/pmu-events/arch/x86/haswellx/frontend.json
View File

@ -301,4 +301,4 @@
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]
]

52
tools/perf/pmu-events/arch/x86/haswellx/memory.json
View File

@ -233,7 +233,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00244",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch code reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -244,9 +243,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0600400244",
"MSRValue": "0x600400244",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch code reads miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -259,7 +257,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -270,9 +267,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0600400091",
"MSRValue": "0x600400091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -283,9 +279,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x063F800091",
"MSRValue": "0x63F800091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the data is returned from remote dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -298,7 +293,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and the modified data is transferred from remote cache",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -309,9 +303,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_DATA_RD.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x083FC00091",
"MSRValue": "0x83FC00091",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch data reads miss the L3 and clean or shared data is transferred from remote cache",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -324,7 +317,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC007F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -335,9 +327,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x06004007F7",
"MSRValue": "0x6004007F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -348,9 +339,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x063F8007F7",
"MSRValue": "0x63F8007F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the data is returned from remote dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -363,7 +353,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC007F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and the modified data is transferred from remote cache",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -374,9 +363,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_READS.LLC_MISS.REMOTE_HIT_FORWARD",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x083FC007F7",
"MSRValue": "0x83FC007F7",
"Offcore": "1",
"PublicDescription": "Counts all data/code/rfo reads (demand & prefetch) miss the L3 and clean or shared data is transferred from remote cache",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -389,7 +377,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC08FFF",
"Offcore": "1",
"PublicDescription": "Counts all requests miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -402,7 +389,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00122",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch RFOs miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -413,9 +399,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.ALL_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0600400122",
"MSRValue": "0x600400122",
"Offcore": "1",
"PublicDescription": "Counts all demand & prefetch RFOs miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -428,7 +413,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00004",
"Offcore": "1",
"PublicDescription": "Counts all demand code reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -439,9 +423,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_CODE_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0600400004",
"MSRValue": "0x600400004",
"Offcore": "1",
"PublicDescription": "Counts all demand code reads miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -454,7 +437,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00001",
"Offcore": "1",
"PublicDescription": "Counts demand data reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -465,9 +447,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_DATA_RD.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0600400001",
"MSRValue": "0x600400001",
"Offcore": "1",
"PublicDescription": "Counts demand data reads miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -480,7 +461,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00002",
"Offcore": "1",
"PublicDescription": "Counts all demand data writes (RFOs) miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -491,9 +471,8 @@
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE.DEMAND_RFO.LLC_MISS.LOCAL_DRAM",
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x0600400002",
"MSRValue": "0x600400002",
"Offcore": "1",
"PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the data is returned from local dram",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -506,7 +485,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x103FC00002",
"Offcore": "1",
"PublicDescription": "Counts all demand data writes (RFOs) miss the L3 and the modified data is transferred from remote cache",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -519,7 +497,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00040",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) code reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -532,7 +509,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00010",
"Offcore": "1",
"PublicDescription": "Counts prefetch (that bring data to L2) data reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -545,7 +521,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00020",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to L2) RFOs miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -558,7 +533,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00200",
"Offcore": "1",
"PublicDescription": "Counts prefetch (that bring data to LLC only) code reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -571,7 +545,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00080",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) data reads miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -584,7 +557,6 @@
"MSRIndex": "0x1a6,0x1a7",
"MSRValue": "0x3FBFC00100",
"Offcore": "1",
"PublicDescription": "Counts all prefetch (that bring data to LLC only) RFOs miss in the L3",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
@ -772,4 +744,4 @@
"SampleAfterValue": "2000003",
"UMask": "0x40"
}
]
]

2
tools/perf/pmu-events/arch/x86/haswellx/other.json
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@ -40,4 +40,4 @@
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]
]

4
tools/perf/pmu-events/arch/x86/haswellx/pipeline.json
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@ -1295,11 +1295,11 @@
"BriefDescription": "Cycles with less than 10 actually retired uops.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "10",
"CounterMask": "16",
"EventCode": "0xC2",
"EventName": "UOPS_RETIRED.TOTAL_CYCLES",
"Invert": "1",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}
]
]

3659
tools/perf/pmu-events/arch/x86/haswellx/uncore-cache.json
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tools/perf/pmu-events/arch/x86/haswellx/uncore-interconnect.json
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tools/perf/pmu-events/arch/x86/haswellx/uncore-memory.json
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tools/perf/pmu-events/arch/x86/haswellx/uncore-other.json Normal file
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tools/perf/pmu-events/arch/x86/haswellx/uncore-power.json
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@ -1,91 +1,496 @@
[
{
"BriefDescription": "PCU clock ticks. Use to get percentages of PCU cycles events",
"BriefDescription": "pclk Cycles",
"Counter": "0,1,2,3",
"EventName": "UNC_P_CLOCKTICKS",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "This is an occupancy event that tracks the number of cores that are in C0. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details",
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"Filter": "occ_sel=1",
"MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C0 / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "power_state_occupancy.cores_c0 %",
"EventCode": "0x60",
"EventName": "UNC_P_CORE0_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "This is an occupancy event that tracks the number of cores that are in C3. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events and occupancy triggering to capture other details",
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"Filter": "occ_sel=2",
"MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C3 / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "power_state_occupancy.cores_c3 %",
"EventCode": "0x6A",
"EventName": "UNC_P_CORE10_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "This is an occupancy event that tracks the number of cores that are in C6. It can be used by itself to get the average number of cores in C0, with threshholding to generate histograms, or with other PCU events ",
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"Filter": "occ_sel=3",
"MetricExpr": "(UNC_P_POWER_STATE_OCCUPANCY.CORES_C6 / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "power_state_occupancy.cores_c6 %",
"EventCode": "0x6B",
"EventName": "UNC_P_CORE11_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Counts the number of cycles that we are in external PROCHOT mode. This mode is triggered when a sensor off the die determines that something off-die (like DRAM) is too hot and must throttle to avoid damaging the chip",
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"MetricExpr": "(UNC_P_PROCHOT_EXTERNAL_CYCLES / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "prochot_external_cycles %",
"EventCode": "0x6C",
"EventName": "UNC_P_CORE12_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Counts the number of cycles when temperature is the upper limit on frequency",
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6D",
"EventName": "UNC_P_CORE13_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6E",
"EventName": "UNC_P_CORE14_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6F",
"EventName": "UNC_P_CORE15_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x70",
"EventName": "UNC_P_CORE16_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x71",
"EventName": "UNC_P_CORE17_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x61",
"EventName": "UNC_P_CORE1_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x62",
"EventName": "UNC_P_CORE2_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x63",
"EventName": "UNC_P_CORE3_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x64",
"EventName": "UNC_P_CORE4_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x65",
"EventName": "UNC_P_CORE5_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x66",
"EventName": "UNC_P_CORE6_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x67",
"EventName": "UNC_P_CORE7_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x68",
"EventName": "UNC_P_CORE8_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x69",
"EventName": "UNC_P_CORE9_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x30",
"EventName": "UNC_P_DEMOTIONS_CORE0",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x31",
"EventName": "UNC_P_DEMOTIONS_CORE1",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3A",
"EventName": "UNC_P_DEMOTIONS_CORE10",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3B",
"EventName": "UNC_P_DEMOTIONS_CORE11",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3C",
"EventName": "UNC_P_DEMOTIONS_CORE12",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3D",
"EventName": "UNC_P_DEMOTIONS_CORE13",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3E",
"EventName": "UNC_P_DEMOTIONS_CORE14",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x3F",
"EventName": "UNC_P_DEMOTIONS_CORE15",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x40",
"EventName": "UNC_P_DEMOTIONS_CORE16",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x41",
"EventName": "UNC_P_DEMOTIONS_CORE17",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x32",
"EventName": "UNC_P_DEMOTIONS_CORE2",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x33",
"EventName": "UNC_P_DEMOTIONS_CORE3",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x34",
"EventName": "UNC_P_DEMOTIONS_CORE4",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x35",
"EventName": "UNC_P_DEMOTIONS_CORE5",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x36",
"EventName": "UNC_P_DEMOTIONS_CORE6",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x37",
"EventName": "UNC_P_DEMOTIONS_CORE7",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x38",
"EventName": "UNC_P_DEMOTIONS_CORE8",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Core C State Demotions",
"Counter": "0,1,2,3",
"EventCode": "0x39",
"EventName": "UNC_P_DEMOTIONS_CORE9",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
"Counter": "0,1,2,3",
"EventCode": "0xB",
"EventName": "UNC_P_FREQ_BAND0_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
"Counter": "0,1,2,3",
"EventCode": "0xC",
"EventName": "UNC_P_FREQ_BAND1_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
"Counter": "0,1,2,3",
"EventCode": "0xD",
"EventName": "UNC_P_FREQ_BAND2_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Frequency Residency",
"Counter": "0,1,2,3",
"EventCode": "0xE",
"EventName": "UNC_P_FREQ_BAND3_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Thermal Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x4",
"EventName": "UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES",
"MetricExpr": "(UNC_P_FREQ_MAX_LIMIT_THERMAL_CYCLES / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "freq_max_limit_thermal_cycles %",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Counts the number of cycles when the OS is the upper limit on frequency",
"BriefDescription": "OS Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x6",
"EventName": "UNC_P_FREQ_MAX_OS_CYCLES",
"MetricExpr": "(UNC_P_FREQ_MAX_OS_CYCLES / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "freq_max_os_cycles %",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Counts the number of cycles when power is the upper limit on frequency",
"BriefDescription": "Power Strongest Upper Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x5",
"EventName": "UNC_P_FREQ_MAX_POWER_CYCLES",
"MetricExpr": "(UNC_P_FREQ_MAX_POWER_CYCLES / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "freq_max_power_cycles %",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Counts the number of cycles when current is the upper limit on frequency",
"BriefDescription": "IO P Limit Strongest Lower Limit Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x73",
"EventName": "UNC_P_FREQ_MIN_IO_P_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Cycles spent changing Frequency",
"Counter": "0,1,2,3",
"EventCode": "0x74",
"EventName": "UNC_P_FREQ_TRANS_CYCLES",
"MetricExpr": "(UNC_P_FREQ_TRANS_CYCLES / UNC_P_CLOCKTICKS) * 100.",
"MetricName": "freq_trans_cycles %",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Memory Phase Shedding Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x2F",
"EventName": "UNC_P_MEMORY_PHASE_SHEDDING_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C0",
"Counter": "0,1,2,3",
"EventCode": "0x2A",
"EventName": "UNC_P_PKG_RESIDENCY_C0_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C2E",
"Counter": "0,1,2,3",
"EventCode": "0x2B",
"EventName": "UNC_P_PKG_RESIDENCY_C2E_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C3",
"Counter": "0,1,2,3",
"EventCode": "0x2C",
"EventName": "UNC_P_PKG_RESIDENCY_C3_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C6",
"Counter": "0,1,2,3",
"EventCode": "0x2D",
"EventName": "UNC_P_PKG_RESIDENCY_C6_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C7 State Residency",
"Counter": "0,1,2,3",
"EventCode": "0x2E",
"EventName": "UNC_P_PKG_RESIDENCY_C7_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C0 and C1",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C0",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C3",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C3",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Number of cores in C-State; C6 and C7",
"Counter": "0,1,2,3",
"EventCode": "0x80",
"EventName": "UNC_P_POWER_STATE_OCCUPANCY.CORES_C6",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "External Prochot",
"Counter": "0,1,2,3",
"EventCode": "0xA",
"EventName": "UNC_P_PROCHOT_EXTERNAL_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Internal Prochot",
"Counter": "0,1,2,3",
"EventCode": "0x9",
"EventName": "UNC_P_PROCHOT_INTERNAL_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Total Core C State Transition Cycles",
"Counter": "0,1,2,3",
"EventCode": "0x72",
"EventName": "UNC_P_TOTAL_TRANSITION_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_UFS_TRANSITIONS_NO_CHANGE",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_P_UFS_TRANSITIONS_NO_CHANGE",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "VR Hot",
"Counter": "0,1,2,3",
"EventCode": "0x42",
"EventName": "UNC_P_VR_HOT_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "Package C State Residency - C1E",
"Counter": "0,1,2,3",
"EventCode": "0x4E",
"EventName": "UNC_P_PKG_RESIDENCY_C1E_CYCLES",
"PerPkg": "1",
"Unit": "PCU"
},
{
"BriefDescription": "UNC_P_UFS_TRANSITIONS_RING_GV",
"Counter": "0,1,2,3",
"EventCode": "0x79",
"EventName": "UNC_P_UFS_TRANSITIONS_RING_GV",
"PerPkg": "1",
"Unit": "PCU"
}

2
tools/perf/pmu-events/arch/x86/haswellx/virtual-memory.json
View File

@ -481,4 +481,4 @@
"SampleAfterValue": "100003",
"UMask": "0x20"
}
]
]