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KVM: arm64: PMU: Align chained counter implementation with architecture pseudocode
Ricardo recently pointed out that the PMU chained counter emulation in KVM wasn't quite behaving like the one on actual hardware, in the sense that a chained counter would expose an overflow on both halves of a chained counter, while KVM would only expose the overflow on the top half. The difference is subtle, but significant. What does the architecture say (DDI0087 H.a): - Up to PMUv3p4, all counters but the cycle counter are 32bit - A 32bit counter that overflows generates a CHAIN event on the adjacent counter after exposing its own overflow status - The CHAIN event is accounted if the counter is correctly configured (CHAIN event selected and counter enabled) This all means that our current implementation (which uses 64bit perf events) prevents us from emulating this overflow on the lower half. How to fix this? By implementing the above, to the letter. This largely results in code deletion, removing the notions of "counter pair", "chained counters", and "canonical counter". The code is further restructured to make the CHAIN handling similar to SWINC, as the two are now extremely similar in behaviour. Reported-by: Ricardo Koller <ricarkol@google.com> Signed-off-by: Marc Zyngier <maz@kernel.org> Reviewed-by: Reiji Watanabe <reijiw@google.com> Link: https://lore.kernel.org/r/20221113163832.3154370-3-maz@kernel.org
This commit is contained in:
Marc Zyngier
parent
d017eeabd5
commit
bead02204e
@ -15,16 +15,14 @@
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#include <kvm/arm_pmu.h>
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#include <kvm/arm_vgic.h>
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#define PERF_ATTR_CFG1_COUNTER_64BIT BIT(0)
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DEFINE_STATIC_KEY_FALSE(kvm_arm_pmu_available);
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static LIST_HEAD(arm_pmus);
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static DEFINE_MUTEX(arm_pmus_lock);
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static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx);
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static void kvm_pmu_update_pmc_chained(struct kvm_vcpu *vcpu, u64 select_idx);
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static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, struct kvm_pmc *pmc);
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#define PERF_ATTR_CFG1_KVM_PMU_CHAINED 0x1
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static u32 kvm_pmu_event_mask(struct kvm *kvm)
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{
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@ -57,6 +55,11 @@ static bool kvm_pmu_idx_is_64bit(struct kvm_vcpu *vcpu, u64 select_idx)
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__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_LC);
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}
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static bool kvm_pmu_counter_can_chain(struct kvm_vcpu *vcpu, u64 idx)
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{
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return (!(idx & 1) && (idx + 1) < ARMV8_PMU_CYCLE_IDX);
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}
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static struct kvm_vcpu *kvm_pmc_to_vcpu(struct kvm_pmc *pmc)
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{
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struct kvm_pmu *pmu;
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@ -69,91 +72,22 @@ static struct kvm_vcpu *kvm_pmc_to_vcpu(struct kvm_pmc *pmc)
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}
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/**
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* kvm_pmu_pmc_is_chained - determine if the pmc is chained
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* @pmc: The PMU counter pointer
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*/
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static bool kvm_pmu_pmc_is_chained(struct kvm_pmc *pmc)
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{
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struct kvm_vcpu *vcpu = kvm_pmc_to_vcpu(pmc);
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return test_bit(pmc->idx >> 1, vcpu->arch.pmu.chained);
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}
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/**
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* kvm_pmu_idx_is_high_counter - determine if select_idx is a high/low counter
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* @select_idx: The counter index
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*/
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static bool kvm_pmu_idx_is_high_counter(u64 select_idx)
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{
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return select_idx & 0x1;
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}
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/**
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* kvm_pmu_get_canonical_pmc - obtain the canonical pmc
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* @pmc: The PMU counter pointer
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*
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* When a pair of PMCs are chained together we use the low counter (canonical)
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* to hold the underlying perf event.
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*/
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static struct kvm_pmc *kvm_pmu_get_canonical_pmc(struct kvm_pmc *pmc)
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{
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if (kvm_pmu_pmc_is_chained(pmc) &&
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kvm_pmu_idx_is_high_counter(pmc->idx))
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return pmc - 1;
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return pmc;
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}
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static struct kvm_pmc *kvm_pmu_get_alternate_pmc(struct kvm_pmc *pmc)
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{
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if (kvm_pmu_idx_is_high_counter(pmc->idx))
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return pmc - 1;
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else
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return pmc + 1;
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}
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/**
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* kvm_pmu_idx_has_chain_evtype - determine if the event type is chain
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* kvm_pmu_get_counter_value - get PMU counter value
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* @vcpu: The vcpu pointer
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* @select_idx: The counter index
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*/
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static bool kvm_pmu_idx_has_chain_evtype(struct kvm_vcpu *vcpu, u64 select_idx)
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u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
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{
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u64 eventsel, reg;
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u64 counter, reg, enabled, running;
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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struct kvm_pmc *pmc = &pmu->pmc[select_idx];
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select_idx |= 0x1;
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if (!kvm_vcpu_has_pmu(vcpu))
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return 0;
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if (select_idx == ARMV8_PMU_CYCLE_IDX)
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return false;
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reg = PMEVTYPER0_EL0 + select_idx;
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eventsel = __vcpu_sys_reg(vcpu, reg) & kvm_pmu_event_mask(vcpu->kvm);
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return eventsel == ARMV8_PMUV3_PERFCTR_CHAIN;
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}
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/**
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* kvm_pmu_get_pair_counter_value - get PMU counter value
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* @vcpu: The vcpu pointer
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* @pmc: The PMU counter pointer
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*/
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static u64 kvm_pmu_get_pair_counter_value(struct kvm_vcpu *vcpu,
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struct kvm_pmc *pmc)
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{
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u64 counter, counter_high, reg, enabled, running;
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if (kvm_pmu_pmc_is_chained(pmc)) {
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pmc = kvm_pmu_get_canonical_pmc(pmc);
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reg = PMEVCNTR0_EL0 + pmc->idx;
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counter = __vcpu_sys_reg(vcpu, reg);
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counter_high = __vcpu_sys_reg(vcpu, reg + 1);
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counter = lower_32_bits(counter) | (counter_high << 32);
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} else {
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reg = (pmc->idx == ARMV8_PMU_CYCLE_IDX)
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? PMCCNTR_EL0 : PMEVCNTR0_EL0 + pmc->idx;
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counter = __vcpu_sys_reg(vcpu, reg);
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}
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/*
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* The real counter value is equal to the value of counter register plus
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@ -163,29 +97,7 @@ static u64 kvm_pmu_get_pair_counter_value(struct kvm_vcpu *vcpu,
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counter += perf_event_read_value(pmc->perf_event, &enabled,
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&running);
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return counter;
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}
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/**
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* kvm_pmu_get_counter_value - get PMU counter value
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* @vcpu: The vcpu pointer
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* @select_idx: The counter index
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*/
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u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx)
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{
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u64 counter;
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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struct kvm_pmc *pmc = &pmu->pmc[select_idx];
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if (!kvm_vcpu_has_pmu(vcpu))
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return 0;
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counter = kvm_pmu_get_pair_counter_value(vcpu, pmc);
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if (kvm_pmu_pmc_is_chained(pmc) &&
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kvm_pmu_idx_is_high_counter(select_idx))
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counter = upper_32_bits(counter);
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else if (select_idx != ARMV8_PMU_CYCLE_IDX)
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if (select_idx != ARMV8_PMU_CYCLE_IDX)
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counter = lower_32_bits(counter);
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return counter;
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@ -218,7 +130,6 @@ void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 val)
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*/
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static void kvm_pmu_release_perf_event(struct kvm_pmc *pmc)
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{
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pmc = kvm_pmu_get_canonical_pmc(pmc);
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if (pmc->perf_event) {
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perf_event_disable(pmc->perf_event);
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perf_event_release_kernel(pmc->perf_event);
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@ -236,11 +147,10 @@ static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, struct kvm_pmc *pmc)
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{
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u64 counter, reg, val;
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pmc = kvm_pmu_get_canonical_pmc(pmc);
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if (!pmc->perf_event)
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return;
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counter = kvm_pmu_get_pair_counter_value(vcpu, pmc);
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counter = kvm_pmu_get_counter_value(vcpu, pmc->idx);
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if (pmc->idx == ARMV8_PMU_CYCLE_IDX) {
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reg = PMCCNTR_EL0;
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@ -252,9 +162,6 @@ static void kvm_pmu_stop_counter(struct kvm_vcpu *vcpu, struct kvm_pmc *pmc)
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__vcpu_sys_reg(vcpu, reg) = val;
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if (kvm_pmu_pmc_is_chained(pmc))
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__vcpu_sys_reg(vcpu, reg + 1) = upper_32_bits(counter);
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kvm_pmu_release_perf_event(pmc);
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}
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@ -285,8 +192,6 @@ void kvm_pmu_vcpu_reset(struct kvm_vcpu *vcpu)
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for_each_set_bit(i, &mask, 32)
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kvm_pmu_stop_counter(vcpu, &pmu->pmc[i]);
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bitmap_zero(vcpu->arch.pmu.chained, ARMV8_PMU_MAX_COUNTER_PAIRS);
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}
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/**
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@ -340,12 +245,9 @@ void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val)
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pmc = &pmu->pmc[i];
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/* A change in the enable state may affect the chain state */
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kvm_pmu_update_pmc_chained(vcpu, i);
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if (!pmc->perf_event) {
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kvm_pmu_create_perf_event(vcpu, i);
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/* At this point, pmc must be the canonical */
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if (pmc->perf_event) {
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} else {
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perf_event_enable(pmc->perf_event);
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if (pmc->perf_event->state != PERF_EVENT_STATE_ACTIVE)
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kvm_debug("fail to enable perf event\n");
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@ -375,11 +277,6 @@ void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu, u64 val)
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pmc = &pmu->pmc[i];
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/* A change in the enable state may affect the chain state */
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kvm_pmu_update_pmc_chained(vcpu, i);
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kvm_pmu_create_perf_event(vcpu, i);
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/* At this point, pmc must be the canonical */
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if (pmc->perf_event)
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perf_event_disable(pmc->perf_event);
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}
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@ -484,6 +381,48 @@ static void kvm_pmu_perf_overflow_notify_vcpu(struct irq_work *work)
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kvm_vcpu_kick(vcpu);
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}
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/*
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* Perform an increment on any of the counters described in @mask,
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* generating the overflow if required, and propagate it as a chained
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* event if possible.
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*/
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static void kvm_pmu_counter_increment(struct kvm_vcpu *vcpu,
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unsigned long mask, u32 event)
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{
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int i;
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if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E))
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return;
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/* Weed out disabled counters */
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mask &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
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for_each_set_bit(i, &mask, ARMV8_PMU_CYCLE_IDX) {
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u64 type, reg;
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/* Filter on event type */
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type = __vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i);
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type &= kvm_pmu_event_mask(vcpu->kvm);
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if (type != event)
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continue;
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/* Increment this counter */
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reg = __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1;
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reg = lower_32_bits(reg);
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__vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = reg;
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if (reg) /* No overflow? move on */
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continue;
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/* Mark overflow */
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__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i);
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if (kvm_pmu_counter_can_chain(vcpu, i))
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kvm_pmu_counter_increment(vcpu, BIT(i + 1),
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ARMV8_PMUV3_PERFCTR_CHAIN);
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}
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}
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/**
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* When the perf event overflows, set the overflow status and inform the vcpu.
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*/
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@ -514,6 +453,10 @@ static void kvm_pmu_perf_overflow(struct perf_event *perf_event,
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__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(idx);
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if (kvm_pmu_counter_can_chain(vcpu, idx))
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kvm_pmu_counter_increment(vcpu, BIT(idx + 1),
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ARMV8_PMUV3_PERFCTR_CHAIN);
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if (kvm_pmu_overflow_status(vcpu)) {
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kvm_make_request(KVM_REQ_IRQ_PENDING, vcpu);
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@ -533,50 +476,7 @@ static void kvm_pmu_perf_overflow(struct perf_event *perf_event,
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*/
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void kvm_pmu_software_increment(struct kvm_vcpu *vcpu, u64 val)
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{
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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int i;
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if (!kvm_vcpu_has_pmu(vcpu))
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return;
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if (!(__vcpu_sys_reg(vcpu, PMCR_EL0) & ARMV8_PMU_PMCR_E))
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return;
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/* Weed out disabled counters */
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val &= __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
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for (i = 0; i < ARMV8_PMU_CYCLE_IDX; i++) {
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u64 type, reg;
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if (!(val & BIT(i)))
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continue;
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/* PMSWINC only applies to ... SW_INC! */
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type = __vcpu_sys_reg(vcpu, PMEVTYPER0_EL0 + i);
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type &= kvm_pmu_event_mask(vcpu->kvm);
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if (type != ARMV8_PMUV3_PERFCTR_SW_INCR)
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continue;
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/* increment this even SW_INC counter */
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reg = __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) + 1;
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reg = lower_32_bits(reg);
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__vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i) = reg;
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if (reg) /* no overflow on the low part */
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continue;
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if (kvm_pmu_pmc_is_chained(&pmu->pmc[i])) {
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/* increment the high counter */
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reg = __vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i + 1) + 1;
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reg = lower_32_bits(reg);
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__vcpu_sys_reg(vcpu, PMEVCNTR0_EL0 + i + 1) = reg;
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if (!reg) /* mark overflow on the high counter */
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__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i + 1);
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} else {
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/* mark overflow on low counter */
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__vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= BIT(i);
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}
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}
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kvm_pmu_counter_increment(vcpu, val, ARMV8_PMUV3_PERFCTR_SW_INCR);
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}
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/**
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@ -625,18 +525,11 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx)
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{
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struct arm_pmu *arm_pmu = vcpu->kvm->arch.arm_pmu;
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struct kvm_pmu *pmu = &vcpu->arch.pmu;
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struct kvm_pmc *pmc;
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struct kvm_pmc *pmc = &pmu->pmc[select_idx];
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struct perf_event *event;
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struct perf_event_attr attr;
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u64 eventsel, counter, reg, data;
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/*
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* For chained counters the event type and filtering attributes are
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* obtained from the low/even counter. We also use this counter to
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* determine if the event is enabled/disabled.
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*/
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pmc = kvm_pmu_get_canonical_pmc(&pmu->pmc[select_idx]);
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reg = (pmc->idx == ARMV8_PMU_CYCLE_IDX)
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? PMCCFILTR_EL0 : PMEVTYPER0_EL0 + pmc->idx;
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data = __vcpu_sys_reg(vcpu, reg);
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@ -647,8 +540,12 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx)
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else
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eventsel = data & kvm_pmu_event_mask(vcpu->kvm);
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/* Software increment event doesn't need to be backed by a perf event */
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if (eventsel == ARMV8_PMUV3_PERFCTR_SW_INCR)
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/*
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* Neither SW increment nor chained events need to be backed
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* by a perf event.
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*/
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if (eventsel == ARMV8_PMUV3_PERFCTR_SW_INCR ||
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eventsel == ARMV8_PMUV3_PERFCTR_CHAIN)
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return;
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/*
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@ -670,30 +567,21 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx)
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attr.exclude_host = 1; /* Don't count host events */
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attr.config = eventsel;
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counter = kvm_pmu_get_pair_counter_value(vcpu, pmc);
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counter = kvm_pmu_get_counter_value(vcpu, select_idx);
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if (kvm_pmu_pmc_is_chained(pmc)) {
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/**
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* The initial sample period (overflow count) of an event. For
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* chained counters we only support overflow interrupts on the
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* high counter.
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/*
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* If counting with a 64bit counter, advertise it to the perf
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* code, carefully dealing with the initial sample period.
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*/
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if (kvm_pmu_idx_is_64bit(vcpu, select_idx)) {
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attr.config1 |= PERF_ATTR_CFG1_COUNTER_64BIT;
|
||||
attr.sample_period = (-counter) & GENMASK(63, 0);
|
||||
attr.config1 |= PERF_ATTR_CFG1_KVM_PMU_CHAINED;
|
||||
|
||||
event = perf_event_create_kernel_counter(&attr, -1, current,
|
||||
kvm_pmu_perf_overflow,
|
||||
pmc + 1);
|
||||
} else {
|
||||
/* The initial sample period (overflow count) of an event. */
|
||||
if (kvm_pmu_idx_is_64bit(vcpu, pmc->idx))
|
||||
attr.sample_period = (-counter) & GENMASK(63, 0);
|
||||
else
|
||||
attr.sample_period = (-counter) & GENMASK(31, 0);
|
||||
}
|
||||
|
||||
event = perf_event_create_kernel_counter(&attr, -1, current,
|
||||
kvm_pmu_perf_overflow, pmc);
|
||||
}
|
||||
|
||||
if (IS_ERR(event)) {
|
||||
pr_err_once("kvm: pmu event creation failed %ld\n",
|
||||
@ -704,41 +592,6 @@ static void kvm_pmu_create_perf_event(struct kvm_vcpu *vcpu, u64 select_idx)
|
||||
pmc->perf_event = event;
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_pmu_update_pmc_chained - update chained bitmap
|
||||
* @vcpu: The vcpu pointer
|
||||
* @select_idx: The number of selected counter
|
||||
*
|
||||
* Update the chained bitmap based on the event type written in the
|
||||
* typer register and the enable state of the odd register.
|
||||
*/
|
||||
static void kvm_pmu_update_pmc_chained(struct kvm_vcpu *vcpu, u64 select_idx)
|
||||
{
|
||||
struct kvm_pmu *pmu = &vcpu->arch.pmu;
|
||||
struct kvm_pmc *pmc = &pmu->pmc[select_idx], *canonical_pmc;
|
||||
bool new_state, old_state;
|
||||
|
||||
old_state = kvm_pmu_pmc_is_chained(pmc);
|
||||
new_state = kvm_pmu_idx_has_chain_evtype(vcpu, pmc->idx) &&
|
||||
kvm_pmu_counter_is_enabled(vcpu, pmc->idx | 0x1);
|
||||
|
||||
if (old_state == new_state)
|
||||
return;
|
||||
|
||||
canonical_pmc = kvm_pmu_get_canonical_pmc(pmc);
|
||||
kvm_pmu_stop_counter(vcpu, canonical_pmc);
|
||||
if (new_state) {
|
||||
/*
|
||||
* During promotion from !chained to chained we must ensure
|
||||
* the adjacent counter is stopped and its event destroyed
|
||||
*/
|
||||
kvm_pmu_stop_counter(vcpu, kvm_pmu_get_alternate_pmc(pmc));
|
||||
set_bit(pmc->idx >> 1, vcpu->arch.pmu.chained);
|
||||
return;
|
||||
}
|
||||
clear_bit(pmc->idx >> 1, vcpu->arch.pmu.chained);
|
||||
}
|
||||
|
||||
/**
|
||||
* kvm_pmu_set_counter_event_type - set selected counter to monitor some event
|
||||
* @vcpu: The vcpu pointer
|
||||
@ -766,7 +619,6 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vcpu, u64 data,
|
||||
|
||||
__vcpu_sys_reg(vcpu, reg) = data & mask;
|
||||
|
||||
kvm_pmu_update_pmc_chained(vcpu, select_idx);
|
||||
kvm_pmu_create_perf_event(vcpu, select_idx);
|
||||
}
|
||||
|
||||
|
||||
@ -11,7 +11,6 @@
|
||||
#include <asm/perf_event.h>
|
||||
|
||||
#define ARMV8_PMU_CYCLE_IDX (ARMV8_PMU_MAX_COUNTERS - 1)
|
||||
#define ARMV8_PMU_MAX_COUNTER_PAIRS ((ARMV8_PMU_MAX_COUNTERS + 1) >> 1)
|
||||
|
||||
#ifdef CONFIG_HW_PERF_EVENTS
|
||||
|
||||
@ -29,7 +28,6 @@ struct kvm_pmu {
|
||||
struct irq_work overflow_work;
|
||||
struct kvm_pmu_events events;
|
||||
struct kvm_pmc pmc[ARMV8_PMU_MAX_COUNTERS];
|
||||
DECLARE_BITMAP(chained, ARMV8_PMU_MAX_COUNTER_PAIRS);
|
||||
int irq_num;
|
||||
bool created;
|
||||
bool irq_level;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user