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mlxsw: reg: Add XM Direct Register
The XMDR allows direct access to the XM device via the switch. Signed-off-by: Jiri Pirko <jiri@nvidia.com> Signed-off-by: Ido Schimmel <idosch@nvidia.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jiri Pirko
Jakub Kicinski
parent
22f07b86d4
commit
be6ba3b61e
@ -8469,11 +8469,278 @@ mlxsw_reg_rmft2_ipv6_pack(char *payload, bool v, u16 offset, u16 virtual_router,
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mlxsw_reg_rmft2_sip6_mask_memcpy_to(payload, (void *)&sip6_mask);
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}
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/* Note that XRALXX register position violates the rule of ordering register
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* definition by the ID. However, XRALXX pack helpers are using RALXX pack
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* helpers, RALXX registers have higher IDs.
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/* Note that XMDR and XRALXX register positions violate the rule of ordering
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* register definitions by the ID. However, XRALXX pack helpers are
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* using RALXX pack helpers, RALXX registers have higher IDs.
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* Also XMDR is using RALUE enums.
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*/
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/* XMDR - XM Direct Register
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* -------------------------
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* The XMDR allows direct access to the XM device via the switch.
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* Working in synchronous mode. FW waits for response from the XLT
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* for each command. FW acks the XMDR accordingly.
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*/
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#define MLXSW_REG_XMDR_ID 0x7803
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#define MLXSW_REG_XMDR_BASE_LEN 0x20
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#define MLXSW_REG_XMDR_TRANS_LEN 0x80
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#define MLXSW_REG_XMDR_LEN (MLXSW_REG_XMDR_BASE_LEN + \
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MLXSW_REG_XMDR_TRANS_LEN)
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MLXSW_REG_DEFINE(xmdr, MLXSW_REG_XMDR_ID, MLXSW_REG_XMDR_LEN);
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/* reg_xmdr_bulk_entry
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* Bulk_entry
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* 0: Last entry - immediate flush of XRT-cache
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* 1: Bulk entry - do not flush the XRT-cache
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* Access: OP
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*/
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MLXSW_ITEM32(reg, xmdr, bulk_entry, 0x04, 8, 1);
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/* reg_xmdr_num_rec
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* Number of records for Direct access to XM
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* Supported: 0..4 commands (except NOP which is a filler)
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* 0 commands is reserved when bulk_entry = 1.
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* 0 commands is allowed when bulk_entry = 0 for immediate XRT-cache flush.
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* Access: OP
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*/
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MLXSW_ITEM32(reg, xmdr, num_rec, 0x04, 0, 4);
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/* reg_xmdr_reply_vect
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* Reply Vector
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* Bit i for command index i+1
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* values per bit:
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* 0: failed
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* 1: succeeded
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* e.g. if commands 1, 2, 4 succeeded and command 3 failed then binary
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* value will be 0b1011
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* Access: RO
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*/
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MLXSW_ITEM_BIT_ARRAY(reg, xmdr, reply_vect, 0x08, 4, 1);
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static inline void mlxsw_reg_xmdr_pack(char *payload, bool bulk_entry)
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{
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MLXSW_REG_ZERO(xmdr, payload);
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mlxsw_reg_xmdr_bulk_entry_set(payload, bulk_entry);
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}
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enum mlxsw_reg_xmdr_c_cmd_id {
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MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4 = 0x30,
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MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6 = 0x31,
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};
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#define MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN 32
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#define MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN 48
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/* reg_xmdr_c_cmd_id
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*/
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MLXSW_ITEM32(reg, xmdr_c, cmd_id, 0x00, 24, 8);
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/* reg_xmdr_c_seq_number
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*/
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MLXSW_ITEM32(reg, xmdr_c, seq_number, 0x00, 12, 12);
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enum mlxsw_reg_xmdr_c_ltr_op {
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/* Activity is set */
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MLXSW_REG_XMDR_C_LTR_OP_WRITE = 0,
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/* There is no update mask. All fields are updated. */
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MLXSW_REG_XMDR_C_LTR_OP_UPDATE = 1,
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MLXSW_REG_XMDR_C_LTR_OP_DELETE = 2,
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};
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/* reg_xmdr_c_ltr_op
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* Operation.
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_op, 0x04, 24, 8);
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/* reg_xmdr_c_ltr_trap_action
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* Trap action.
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* Values are defined in enum mlxsw_reg_ralue_trap_action.
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_trap_action, 0x04, 20, 4);
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enum mlxsw_reg_xmdr_c_ltr_trap_id_num {
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MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS0,
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MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS1,
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MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS2,
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MLXSW_REG_XMDR_C_LTR_TRAP_ID_NUM_RTR_INGRESS3,
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};
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/* reg_xmdr_c_ltr_trap_id_num
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* Trap-ID number.
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_trap_id_num, 0x04, 16, 4);
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/* reg_xmdr_c_ltr_virtual_router
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* Virtual Router ID.
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* Range is 0..cap_max_virtual_routers-1
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_virtual_router, 0x04, 0, 16);
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/* reg_xmdr_c_ltr_prefix_len
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* Number of bits in the prefix of the LPM route.
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_prefix_len, 0x08, 24, 8);
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/* reg_xmdr_c_ltr_bmp_len
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* The best match prefix length in the case that there is no match for
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* longer prefixes.
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* If (entry_type != MARKER_ENTRY), bmp_len must be equal to prefix_len
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_bmp_len, 0x08, 16, 8);
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/* reg_xmdr_c_ltr_entry_type
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* Entry type.
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* Values are defined in enum mlxsw_reg_ralue_entry_type.
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_entry_type, 0x08, 4, 4);
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enum mlxsw_reg_xmdr_c_ltr_action_type {
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MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL,
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MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE,
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MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME,
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};
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/* reg_xmdr_c_ltr_action_type
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* Action Type.
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_action_type, 0x08, 0, 4);
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/* reg_xmdr_c_ltr_erif
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* Egress Router Interface.
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* Only relevant in case of LOCAL action.
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_erif, 0x10, 0, 16);
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/* reg_xmdr_c_ltr_adjacency_index
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* Points to the first entry of the group-based ECMP.
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* Only relevant in case of REMOTE action.
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_adjacency_index, 0x10, 0, 24);
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#define MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC 0xFFFFFF
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/* reg_xmdr_c_ltr_pointer_to_tunnel
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* Only relevant in case of IP2ME action.
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_pointer_to_tunnel, 0x10, 0, 24);
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/* reg_xmdr_c_ltr_ecmp_size
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* Amount of sequential entries starting
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* from the adjacency_index (the number of ECMPs).
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* The valid range is 1-64, 512, 1024, 2048 and 4096.
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* Only relevant in case of REMOTE action.
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_ecmp_size, 0x14, 0, 32);
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/* reg_xmdr_c_ltr_dip*
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* The prefix of the route or of the marker that the object of the LPM
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* is compared with. The most significant bits of the dip are the prefix.
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* The least significant bits must be '0' if the prefix_len is smaller
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* than 128 for IPv6 or smaller than 32 for IPv4.
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*/
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MLXSW_ITEM32(reg, xmdr_c, ltr_dip4, 0x1C, 0, 32);
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MLXSW_ITEM_BUF(reg, xmdr_c, ltr_dip6, 0x1C, 16);
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static inline void
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mlxsw_reg_xmdr_c_ltr_pack(char *xmdr_payload, unsigned int trans_offset,
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enum mlxsw_reg_xmdr_c_cmd_id cmd_id, u16 seq_number,
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enum mlxsw_reg_xmdr_c_ltr_op op, u16 virtual_router,
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u8 prefix_len)
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{
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char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
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u8 num_rec = mlxsw_reg_xmdr_num_rec_get(xmdr_payload);
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mlxsw_reg_xmdr_num_rec_set(xmdr_payload, num_rec + 1);
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mlxsw_reg_xmdr_c_cmd_id_set(payload, cmd_id);
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mlxsw_reg_xmdr_c_seq_number_set(payload, seq_number);
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mlxsw_reg_xmdr_c_ltr_op_set(payload, op);
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mlxsw_reg_xmdr_c_ltr_virtual_router_set(payload, virtual_router);
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mlxsw_reg_xmdr_c_ltr_prefix_len_set(payload, prefix_len);
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mlxsw_reg_xmdr_c_ltr_entry_type_set(payload,
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MLXSW_REG_RALUE_ENTRY_TYPE_ROUTE_ENTRY);
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mlxsw_reg_xmdr_c_ltr_bmp_len_set(payload, prefix_len);
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}
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static inline unsigned int
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mlxsw_reg_xmdr_c_ltr_pack4(char *xmdr_payload, unsigned int trans_offset,
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u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op,
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u16 virtual_router, u8 prefix_len, u32 *dip)
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{
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char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
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mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset,
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MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V4,
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seq_number, op, virtual_router, prefix_len);
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if (dip)
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mlxsw_reg_xmdr_c_ltr_dip4_set(payload, *dip);
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return MLXSW_REG_XMDR_C_LT_ROUTE_V4_LEN;
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}
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static inline unsigned int
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mlxsw_reg_xmdr_c_ltr_pack6(char *xmdr_payload, unsigned int trans_offset,
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u16 seq_number, enum mlxsw_reg_xmdr_c_ltr_op op,
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u16 virtual_router, u8 prefix_len, const void *dip)
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{
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char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
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mlxsw_reg_xmdr_c_ltr_pack(xmdr_payload, trans_offset,
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MLXSW_REG_XMDR_C_CMD_ID_LT_ROUTE_V6,
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seq_number, op, virtual_router, prefix_len);
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if (dip)
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mlxsw_reg_xmdr_c_ltr_dip6_memcpy_to(payload, dip);
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return MLXSW_REG_XMDR_C_LT_ROUTE_V6_LEN;
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}
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static inline void
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mlxsw_reg_xmdr_c_ltr_act_remote_pack(char *xmdr_payload, unsigned int trans_offset,
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enum mlxsw_reg_ralue_trap_action trap_action,
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enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num,
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u32 adjacency_index, u16 ecmp_size)
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{
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char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
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mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_REMOTE);
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mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action);
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mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num);
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mlxsw_reg_xmdr_c_ltr_adjacency_index_set(payload, adjacency_index);
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mlxsw_reg_xmdr_c_ltr_ecmp_size_set(payload, ecmp_size);
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}
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static inline void
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mlxsw_reg_xmdr_c_ltr_act_local_pack(char *xmdr_payload, unsigned int trans_offset,
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enum mlxsw_reg_ralue_trap_action trap_action,
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enum mlxsw_reg_xmdr_c_ltr_trap_id_num trap_id_num, u16 erif)
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{
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char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
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mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_LOCAL);
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mlxsw_reg_xmdr_c_ltr_trap_action_set(payload, trap_action);
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mlxsw_reg_xmdr_c_ltr_trap_id_num_set(payload, trap_id_num);
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mlxsw_reg_xmdr_c_ltr_erif_set(payload, erif);
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}
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static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_pack(char *xmdr_payload,
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unsigned int trans_offset)
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{
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char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
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mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME);
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mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload,
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MLXSW_REG_XMDR_C_LTR_POINTER_TO_TUNNEL_DISABLED_MAGIC);
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}
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static inline void mlxsw_reg_xmdr_c_ltr_act_ip2me_tun_pack(char *xmdr_payload,
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unsigned int trans_offset,
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u32 pointer_to_tunnel)
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{
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char *payload = xmdr_payload + MLXSW_REG_XMDR_BASE_LEN + trans_offset;
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mlxsw_reg_xmdr_c_ltr_action_type_set(payload, MLXSW_REG_XMDR_C_LTR_ACTION_TYPE_IP2ME);
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mlxsw_reg_xmdr_c_ltr_pointer_to_tunnel_set(payload, pointer_to_tunnel);
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}
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/* XRALTA - XM Router Algorithmic LPM Tree Allocation Register
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* -----------------------------------------------------------
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* The XRALTA is used to allocate the XLT LPM trees.
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@ -11487,6 +11754,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
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MLXSW_REG(rigr2),
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MLXSW_REG(recr2),
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MLXSW_REG(rmft2),
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MLXSW_REG(xmdr),
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MLXSW_REG(xralta),
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MLXSW_REG(xralst),
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MLXSW_REG(xraltb),
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