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ASoC: SOF: Intel: hda: fix the hda init chip
re-write hda_init_caps and remove the HDA reset, clean HDA
streams and clear interrupt steps in hda_dsp_probe so the
HDA init steps will not be called twice if the
CONFIG_SND_SOC_SOF_HDA is true.
Fixes: 8a300c8fb1 ("ASoC: SOF: Intel: Add HDA controller for Intel DSP")
Reviewed-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Zhu Yingjiang <yingjiang.zhu@linux.intel.com>
Signed-off-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: Mark Brown <broonie@kernel.org>
This commit is contained in:
Zhu Yingjiang
Mark Brown
parent
1183e9a634
commit
be1b577d01
@ -161,21 +161,105 @@ int hda_dsp_ctrl_clock_power_gating(struct snd_sof_dev *sdev, bool enable)
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return 0;
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}
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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/*
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* While performing reset, controller may not come back properly and causing
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* issues, so recommendation is to set CGCTL.MISCBDCGE to 0 then do reset
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* (init chip) and then again set CGCTL.MISCBDCGE to 1
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*/
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int hda_dsp_ctrl_init_chip(struct snd_sof_dev *sdev, bool full_reset)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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int ret;
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struct hdac_stream *stream;
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int sd_offset, ret = 0;
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if (bus->chip_init)
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return 0;
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hda_dsp_ctrl_misc_clock_gating(sdev, false);
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ret = snd_hdac_bus_init_chip(bus, full_reset);
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if (full_reset) {
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/* clear WAKESTS */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
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SOF_HDA_WAKESTS_INT_MASK,
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SOF_HDA_WAKESTS_INT_MASK);
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/* reset HDA controller */
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ret = hda_dsp_ctrl_link_reset(sdev, true);
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if (ret < 0) {
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dev_err(sdev->dev, "error: failed to reset HDA controller\n");
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return ret;
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}
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usleep_range(500, 1000);
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/* exit HDA controller reset */
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ret = hda_dsp_ctrl_link_reset(sdev, false);
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if (ret < 0) {
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dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
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return ret;
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}
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usleep_range(1000, 1200);
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}
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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/* check to see if controller is ready */
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if (!snd_hdac_chip_readb(bus, GCTL)) {
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dev_dbg(bus->dev, "controller not ready!\n");
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return -EBUSY;
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}
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/* Accept unsolicited responses */
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snd_hdac_chip_updatel(bus, GCTL, AZX_GCTL_UNSOL, AZX_GCTL_UNSOL);
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/* detect codecs */
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if (!bus->codec_mask) {
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bus->codec_mask = snd_hdac_chip_readw(bus, STATESTS);
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dev_dbg(bus->dev, "codec_mask = 0x%lx\n", bus->codec_mask);
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}
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#endif
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/* clear stream status */
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list_for_each_entry(stream, &bus->stream_list, list) {
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sd_offset = SOF_STREAM_SD_OFFSET(stream);
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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sd_offset +
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SOF_HDA_ADSP_REG_CL_SD_STS,
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SOF_HDA_CL_DMA_SD_INT_MASK,
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SOF_HDA_CL_DMA_SD_INT_MASK);
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}
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/* clear WAKESTS */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
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SOF_HDA_WAKESTS_INT_MASK,
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SOF_HDA_WAKESTS_INT_MASK);
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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/* clear rirb status */
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snd_hdac_chip_writeb(bus, RIRBSTS, RIRB_INT_MASK);
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#endif
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/* clear interrupt status register */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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/* initialize the codec command I/O */
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snd_hdac_bus_init_cmd_io(bus);
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#endif
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/* enable CIE and GIE interrupts */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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/* program the position buffer */
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if (bus->use_posbuf && bus->posbuf.addr) {
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snd_hdac_chip_writel(bus, DPLBASE, (u32)bus->posbuf.addr);
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snd_hdac_chip_writel(bus, DPUBASE,
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upper_32_bits(bus->posbuf.addr));
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}
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#endif
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bus->chip_init = true;
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hda_dsp_ctrl_misc_clock_gating(sdev, true);
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return ret;
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}
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#endif
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@ -264,9 +264,12 @@ static const char *fixup_tplg_name(struct snd_sof_dev *sdev,
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return tplg_filename;
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}
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#endif
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static int hda_init_caps(struct snd_sof_dev *sdev)
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{
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struct hdac_bus *bus = sof_to_bus(sdev);
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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struct hdac_ext_link *hlink;
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struct snd_soc_acpi_mach_params *mach_params;
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struct snd_soc_acpi_mach *hda_mach;
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@ -274,8 +277,9 @@ static int hda_init_caps(struct snd_sof_dev *sdev)
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struct snd_soc_acpi_mach *mach;
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const char *tplg_filename;
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int codec_num = 0;
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int ret = 0;
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int i;
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#endif
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int ret = 0;
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device_disable_async_suspend(bus->dev);
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@ -283,6 +287,14 @@ static int hda_init_caps(struct snd_sof_dev *sdev)
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if (bus->ppcap)
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dev_dbg(sdev->dev, "PP capability, will probe DSP later.\n");
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ret = hda_dsp_ctrl_init_chip(sdev, true);
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if (ret < 0) {
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dev_err(bus->dev, "error: init chip failed with ret: %d\n",
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ret);
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return ret;
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}
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#if IS_ENABLED(CONFIG_SND_SOC_SOF_HDA)
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if (bus->mlcap)
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snd_hdac_ext_bus_get_ml_capabilities(bus);
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@ -293,12 +305,6 @@ static int hda_init_caps(struct snd_sof_dev *sdev)
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return ret;
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}
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ret = hda_dsp_ctrl_init_chip(sdev, true);
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if (ret < 0) {
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dev_err(bus->dev, "error: init chip failed with ret: %d\n", ret);
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goto out;
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}
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/* codec detection */
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if (!bus->codec_mask) {
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dev_info(bus->dev, "no hda codecs found!\n");
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@ -339,8 +345,10 @@ static int hda_init_caps(struct snd_sof_dev *sdev)
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/* use local variable for readability */
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tplg_filename = pdata->tplg_filename;
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tplg_filename = fixup_tplg_name(sdev, tplg_filename);
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if (!tplg_filename)
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goto out;
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if (!tplg_filename) {
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hda_codec_i915_exit(sdev);
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return ret;
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}
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pdata->tplg_filename = tplg_filename;
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}
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}
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@ -364,34 +372,9 @@ static int hda_init_caps(struct snd_sof_dev *sdev)
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*/
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list_for_each_entry(hlink, &bus->hlink_list, list)
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snd_hdac_ext_bus_link_put(bus, hlink);
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return 0;
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out:
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hda_codec_i915_exit(sdev);
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return ret;
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}
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#else
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static int hda_init_caps(struct snd_sof_dev *sdev)
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{
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/*
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* set CGCTL.MISCBDCGE to 0 during reset and set back to 1
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* when reset finished.
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* TODO: maybe no need for init_caps?
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*/
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hda_dsp_ctrl_misc_clock_gating(sdev, 0);
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/* clear WAKESTS */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
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SOF_HDA_WAKESTS_INT_MASK,
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SOF_HDA_WAKESTS_INT_MASK);
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return 0;
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}
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#endif
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return 0;
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}
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static const struct sof_intel_dsp_desc
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*get_chip_info(struct snd_sof_pdata *pdata)
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@ -409,9 +392,8 @@ int hda_dsp_probe(struct snd_sof_dev *sdev)
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struct pci_dev *pci = to_pci_dev(sdev->dev);
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struct sof_intel_hda_dev *hdev;
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struct hdac_bus *bus;
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struct hdac_stream *stream;
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const struct sof_intel_dsp_desc *chip;
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int sd_offset, ret = 0;
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int ret = 0;
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/*
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* detect DSP by checking class/subclass/prog-id information
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@ -558,49 +540,6 @@ int hda_dsp_probe(struct snd_sof_dev *sdev)
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if (ret < 0)
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goto free_ipc_irq;
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/* reset HDA controller */
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ret = hda_dsp_ctrl_link_reset(sdev, true);
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if (ret < 0) {
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dev_err(sdev->dev, "error: failed to reset HDA controller\n");
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goto free_ipc_irq;
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}
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/* exit HDA controller reset */
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ret = hda_dsp_ctrl_link_reset(sdev, false);
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if (ret < 0) {
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dev_err(sdev->dev, "error: failed to exit HDA controller reset\n");
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goto free_ipc_irq;
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}
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/* clear stream status */
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list_for_each_entry(stream, &bus->stream_list, list) {
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sd_offset = SOF_STREAM_SD_OFFSET(stream);
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR,
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sd_offset +
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SOF_HDA_ADSP_REG_CL_SD_STS,
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SOF_HDA_CL_DMA_SD_INT_MASK,
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SOF_HDA_CL_DMA_SD_INT_MASK);
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}
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/* clear WAKESTS */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_WAKESTS,
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SOF_HDA_WAKESTS_INT_MASK,
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SOF_HDA_WAKESTS_INT_MASK);
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/* clear interrupt status register */
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snd_sof_dsp_write(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTSTS,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_ALL_STREAM);
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/* enable CIE and GIE interrupts */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, SOF_HDA_INTCTL,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN,
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SOF_HDA_INT_CTRL_EN | SOF_HDA_INT_GLOBAL_EN);
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/* re-enable CGCTL.MISCBDCGE after reset */
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hda_dsp_ctrl_misc_clock_gating(sdev, true);
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device_disable_async_suspend(&pci->dev);
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/* enable DSP features */
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snd_sof_dsp_update_bits(sdev, HDA_DSP_PP_BAR, SOF_HDA_REG_PP_PPCTL,
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SOF_HDA_PPCTL_GPROCEN, SOF_HDA_PPCTL_GPROCEN);
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