mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-12-26 12:34:41 +08:00
staging: vt6655: Fix macro definitions
Macros should be able to be used in if/else
without braces.
Convert macros to use do {} while (0) instead
of bare braces where appropriate.
Convert macros to use single line macro definitions
where appropriate.
Signed-off-by: Joe Perches <joe@perches.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
Joe Perches
Greg Kroah-Hartman
parent
a730753880
commit
bda2a44e2a
@ -72,14 +72,10 @@
|
||||
/*--------------------- Export Macros ------------------------------*/
|
||||
|
||||
#define BBvClearFOE(dwIoBase) \
|
||||
{ \
|
||||
BBbWriteEmbedded(dwIoBase, 0xB1, 0); \
|
||||
}
|
||||
BBbWriteEmbedded(dwIoBase, 0xB1, 0)
|
||||
|
||||
#define BBvSetFOE(dwIoBase) \
|
||||
{ \
|
||||
BBbWriteEmbedded(dwIoBase, 0xB1, 0x0C); \
|
||||
}
|
||||
BBbWriteEmbedded(dwIoBase, 0xB1, 0x0C)
|
||||
|
||||
|
||||
/*--------------------- Export Classes ----------------------------*/
|
||||
|
||||
@ -83,13 +83,14 @@ typedef enum _chip_type {
|
||||
|
||||
|
||||
#ifdef VIAWET_DEBUG
|
||||
#define ASSERT(x) { \
|
||||
if (!(x)) { \
|
||||
printk(KERN_ERR "assertion %s failed: file %s line %d\n", #x, \
|
||||
__FUNCTION__, __LINE__); \
|
||||
*(int *)0 = 0; \
|
||||
} \
|
||||
}
|
||||
#define ASSERT(x) \
|
||||
do { \
|
||||
if (!(x)) { \
|
||||
printk(KERN_ERR "assertion %s failed: file %s line %d\n", \
|
||||
#x, __func__, __LINE__); \
|
||||
*(int *)0 = 0; \
|
||||
} \
|
||||
} while (0)
|
||||
#define DBG_PORT80(value) outb(value, 0x80)
|
||||
#else
|
||||
#define ASSERT(x)
|
||||
|
||||
@ -638,411 +638,340 @@
|
||||
/*--------------------- Export Macros ------------------------------*/
|
||||
|
||||
#define MACvRegBitsOn(dwIoBase, byRegOfs, byBits) \
|
||||
{ \
|
||||
unsigned char byData; \
|
||||
VNSvInPortB(dwIoBase + byRegOfs, &byData); \
|
||||
VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
|
||||
}
|
||||
do { \
|
||||
unsigned char byData; \
|
||||
VNSvInPortB(dwIoBase + byRegOfs, &byData); \
|
||||
VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
|
||||
} while (0)
|
||||
|
||||
#define MACvWordRegBitsOn(dwIoBase, byRegOfs, wBits) \
|
||||
{ \
|
||||
unsigned short wData; \
|
||||
VNSvInPortW(dwIoBase + byRegOfs, &wData); \
|
||||
VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits)); \
|
||||
}
|
||||
do { \
|
||||
unsigned short wData; \
|
||||
VNSvInPortW(dwIoBase + byRegOfs, &wData); \
|
||||
VNSvOutPortW(dwIoBase + byRegOfs, wData | (wBits)); \
|
||||
} while (0)
|
||||
|
||||
#define MACvDWordRegBitsOn(dwIoBase, byRegOfs, dwBits) \
|
||||
{ \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
|
||||
VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits)); \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
|
||||
VNSvOutPortD(dwIoBase + byRegOfs, dwData | (dwBits)); \
|
||||
} while (0)
|
||||
|
||||
#define MACvRegBitsOnEx(dwIoBase, byRegOfs, byMask, byBits) \
|
||||
{ \
|
||||
unsigned char byData; \
|
||||
VNSvInPortB(dwIoBase + byRegOfs, &byData); \
|
||||
byData &= byMask; \
|
||||
VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
|
||||
}
|
||||
do { \
|
||||
unsigned char byData; \
|
||||
VNSvInPortB(dwIoBase + byRegOfs, &byData); \
|
||||
byData &= byMask; \
|
||||
VNSvOutPortB(dwIoBase + byRegOfs, byData | (byBits)); \
|
||||
} while (0)
|
||||
|
||||
#define MACvRegBitsOff(dwIoBase, byRegOfs, byBits) \
|
||||
{ \
|
||||
unsigned char byData; \
|
||||
VNSvInPortB(dwIoBase + byRegOfs, &byData); \
|
||||
VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits)); \
|
||||
}
|
||||
do { \
|
||||
unsigned char byData; \
|
||||
VNSvInPortB(dwIoBase + byRegOfs, &byData); \
|
||||
VNSvOutPortB(dwIoBase + byRegOfs, byData & ~(byBits)); \
|
||||
} while (0)
|
||||
|
||||
#define MACvWordRegBitsOff(dwIoBase, byRegOfs, wBits) \
|
||||
{ \
|
||||
unsigned short wData; \
|
||||
VNSvInPortW(dwIoBase + byRegOfs, &wData); \
|
||||
VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits)); \
|
||||
}
|
||||
do { \
|
||||
unsigned short wData; \
|
||||
VNSvInPortW(dwIoBase + byRegOfs, &wData); \
|
||||
VNSvOutPortW(dwIoBase + byRegOfs, wData & ~(wBits)); \
|
||||
} while (0)
|
||||
|
||||
#define MACvDWordRegBitsOff(dwIoBase, byRegOfs, dwBits) \
|
||||
{ \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
|
||||
VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits)); \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + byRegOfs, &dwData); \
|
||||
VNSvOutPortD(dwIoBase + byRegOfs, dwData & ~(dwBits)); \
|
||||
} while (0)
|
||||
|
||||
#define MACvGetCurrRx0DescAddr(dwIoBase, pdwCurrDescAddr) \
|
||||
{ \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0, \
|
||||
(unsigned long *)pdwCurrDescAddr); \
|
||||
}
|
||||
VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR0, \
|
||||
(unsigned long *)pdwCurrDescAddr)
|
||||
|
||||
#define MACvGetCurrRx1DescAddr(dwIoBase, pdwCurrDescAddr) \
|
||||
{ \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1, \
|
||||
(unsigned long *)pdwCurrDescAddr); \
|
||||
}
|
||||
VNSvInPortD(dwIoBase + MAC_REG_RXDMAPTR1, \
|
||||
(unsigned long *)pdwCurrDescAddr)
|
||||
|
||||
#define MACvGetCurrTx0DescAddr(dwIoBase, pdwCurrDescAddr) \
|
||||
{ \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0, \
|
||||
(unsigned long *)pdwCurrDescAddr); \
|
||||
}
|
||||
VNSvInPortD(dwIoBase + MAC_REG_TXDMAPTR0, \
|
||||
(unsigned long *)pdwCurrDescAddr)
|
||||
|
||||
#define MACvGetCurrAC0DescAddr(dwIoBase, pdwCurrDescAddr) \
|
||||
{ \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR, \
|
||||
(unsigned long *)pdwCurrDescAddr); \
|
||||
}
|
||||
VNSvInPortD(dwIoBase + MAC_REG_AC0DMAPTR, \
|
||||
(unsigned long *)pdwCurrDescAddr)
|
||||
|
||||
#define MACvGetCurrSyncDescAddr(dwIoBase, pdwCurrDescAddr) \
|
||||
{ \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR, \
|
||||
(unsigned long *)pdwCurrDescAddr); \
|
||||
}
|
||||
VNSvInPortD(dwIoBase + MAC_REG_SYNCDMAPTR, \
|
||||
(unsigned long *)pdwCurrDescAddr)
|
||||
|
||||
#define MACvGetCurrATIMDescAddr(dwIoBase, pdwCurrDescAddr) \
|
||||
{ \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \
|
||||
(unsigned long *)pdwCurrDescAddr); \
|
||||
} \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ATIMDMAPTR, \
|
||||
(unsigned long *)pdwCurrDescAddr)
|
||||
|
||||
// set the chip with current BCN tx descriptor address
|
||||
#define MACvSetCurrBCNTxDescAddr(dwIoBase, dwCurrDescAddr) \
|
||||
{ \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \
|
||||
dwCurrDescAddr); \
|
||||
}
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_BCNDMAPTR, \
|
||||
dwCurrDescAddr)
|
||||
|
||||
// set the chip with current BCN length
|
||||
#define MACvSetCurrBCNLength(dwIoBase, wCurrBCNLength) \
|
||||
{ \
|
||||
VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \
|
||||
wCurrBCNLength); \
|
||||
}
|
||||
VNSvOutPortW(dwIoBase + MAC_REG_BCNDMACTL+2, \
|
||||
wCurrBCNLength)
|
||||
|
||||
#define MACvReadBSSIDAddress(dwIoBase, pbyEtherAddr) \
|
||||
{ \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_BSSID0, \
|
||||
(unsigned char *)pbyEtherAddr); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
|
||||
pbyEtherAddr + 1); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
|
||||
pbyEtherAddr + 2); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
|
||||
pbyEtherAddr + 3); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
|
||||
pbyEtherAddr + 4); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
|
||||
pbyEtherAddr + 5); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
||||
}
|
||||
do { \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_BSSID0, \
|
||||
(unsigned char *)pbyEtherAddr); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
|
||||
pbyEtherAddr + 1); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
|
||||
pbyEtherAddr + 2); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
|
||||
pbyEtherAddr + 3); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
|
||||
pbyEtherAddr + 4); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
|
||||
pbyEtherAddr + 5); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
||||
} while (0)
|
||||
|
||||
#define MACvWriteBSSIDAddress(dwIoBase, pbyEtherAddr) \
|
||||
{ \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0, \
|
||||
*(pbyEtherAddr)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
|
||||
*(pbyEtherAddr + 1)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
|
||||
*(pbyEtherAddr + 2)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
|
||||
*(pbyEtherAddr + 3)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
|
||||
*(pbyEtherAddr + 4)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
|
||||
*(pbyEtherAddr + 5)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
||||
}
|
||||
do { \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0, \
|
||||
*(pbyEtherAddr)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 1, \
|
||||
*(pbyEtherAddr + 1)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 2, \
|
||||
*(pbyEtherAddr + 2)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 3, \
|
||||
*(pbyEtherAddr + 3)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 4, \
|
||||
*(pbyEtherAddr + 4)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BSSID0 + 5, \
|
||||
*(pbyEtherAddr + 5)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
||||
} while (0)
|
||||
|
||||
#define MACvReadEtherAddress(dwIoBase, pbyEtherAddr) \
|
||||
{ \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_PAR0, \
|
||||
(unsigned char *)pbyEtherAddr); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1, \
|
||||
pbyEtherAddr + 1); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2, \
|
||||
pbyEtherAddr + 2); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3, \
|
||||
pbyEtherAddr + 3); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4, \
|
||||
pbyEtherAddr + 4); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5, \
|
||||
pbyEtherAddr + 5); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
||||
}
|
||||
|
||||
do { \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_PAR0, \
|
||||
(unsigned char *)pbyEtherAddr); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 1, \
|
||||
pbyEtherAddr + 1); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 2, \
|
||||
pbyEtherAddr + 2); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 3, \
|
||||
pbyEtherAddr + 3); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 4, \
|
||||
pbyEtherAddr + 4); \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_PAR0 + 5, \
|
||||
pbyEtherAddr + 5); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
||||
} while (0)
|
||||
|
||||
#define MACvWriteEtherAddress(dwIoBase, pbyEtherAddr) \
|
||||
{ \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAR0, \
|
||||
*pbyEtherAddr); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1, \
|
||||
*(pbyEtherAddr + 1)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2, \
|
||||
*(pbyEtherAddr + 2)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3, \
|
||||
*(pbyEtherAddr + 3)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4, \
|
||||
*(pbyEtherAddr + 4)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5, \
|
||||
*(pbyEtherAddr + 5)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
||||
}
|
||||
|
||||
do { \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAR0, \
|
||||
*pbyEtherAddr); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 1, \
|
||||
*(pbyEtherAddr + 1)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 2, \
|
||||
*(pbyEtherAddr + 2)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 3, \
|
||||
*(pbyEtherAddr + 3)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 4, \
|
||||
*(pbyEtherAddr + 4)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAR0 + 5, \
|
||||
*(pbyEtherAddr + 5)); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
||||
} while (0)
|
||||
|
||||
#define MACvClearISR(dwIoBase) \
|
||||
{ \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE); \
|
||||
}
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ISR, IMR_MASK_VALUE)
|
||||
|
||||
#define MACvStart(dwIoBase) \
|
||||
{ \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, \
|
||||
(HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON)); \
|
||||
}
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_HOSTCR, \
|
||||
(HOSTCR_MACEN | HOSTCR_RXON | HOSTCR_TXON))
|
||||
|
||||
#define MACvRx0PerPktMode(dwIoBase) \
|
||||
{ \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT); \
|
||||
}
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKT)
|
||||
|
||||
#define MACvRx0BufferFillMode(dwIoBase) \
|
||||
{ \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR); \
|
||||
}
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, RX_PERPKTCLR)
|
||||
|
||||
#define MACvRx1PerPktMode(dwIoBase) \
|
||||
{ \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT); \
|
||||
}
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKT)
|
||||
|
||||
#define MACvRx1BufferFillMode(dwIoBase) \
|
||||
{ \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR); \
|
||||
}
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, RX_PERPKTCLR)
|
||||
|
||||
#define MACvRxOn(dwIoBase) \
|
||||
{ \
|
||||
MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON); \
|
||||
}
|
||||
MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_RXON)
|
||||
|
||||
#define MACvReceive0(dwIoBase) \
|
||||
{ \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); \
|
||||
if (dwData & DMACTL_RUN) { \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \
|
||||
} \
|
||||
else { \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
|
||||
} \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL0, &dwData); \
|
||||
if (dwData & DMACTL_RUN) \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_WAKE); \
|
||||
else \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL0, DMACTL_RUN); \
|
||||
} while (0)
|
||||
|
||||
#define MACvReceive1(dwIoBase) \
|
||||
{ \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); \
|
||||
if (dwData & DMACTL_RUN) { \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \
|
||||
} \
|
||||
else { \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
|
||||
} \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_RXDMACTL1, &dwData); \
|
||||
if (dwData & DMACTL_RUN) \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_WAKE); \
|
||||
else \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_RXDMACTL1, DMACTL_RUN); \
|
||||
} while (0)
|
||||
|
||||
#define MACvTxOn(dwIoBase) \
|
||||
{ \
|
||||
MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON); \
|
||||
}
|
||||
MACvRegBitsOn(dwIoBase, MAC_REG_HOSTCR, HOSTCR_TXON)
|
||||
|
||||
#define MACvTransmit0(dwIoBase) \
|
||||
{ \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); \
|
||||
if (dwData & DMACTL_RUN) { \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \
|
||||
} \
|
||||
else { \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
|
||||
} \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_TXDMACTL0, &dwData); \
|
||||
if (dwData & DMACTL_RUN) \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_WAKE); \
|
||||
else \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_TXDMACTL0, DMACTL_RUN); \
|
||||
} while (0)
|
||||
|
||||
#define MACvTransmitAC0(dwIoBase) \
|
||||
{ \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); \
|
||||
if (dwData & DMACTL_RUN) { \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \
|
||||
} \
|
||||
else { \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
|
||||
} \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_AC0DMACTL, &dwData); \
|
||||
if (dwData & DMACTL_RUN) \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_WAKE); \
|
||||
else \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_AC0DMACTL, DMACTL_RUN); \
|
||||
} while (0)
|
||||
|
||||
#define MACvTransmitSYNC(dwIoBase) \
|
||||
{ \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData); \
|
||||
if (dwData & DMACTL_RUN) { \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \
|
||||
} \
|
||||
else { \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
|
||||
} \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_SYNCDMACTL, &dwData); \
|
||||
if (dwData & DMACTL_RUN) \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_WAKE); \
|
||||
else \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_SYNCDMACTL, DMACTL_RUN); \
|
||||
} while (0)
|
||||
|
||||
#define MACvTransmitATIM(dwIoBase) \
|
||||
{ \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData); \
|
||||
if (dwData & DMACTL_RUN) { \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \
|
||||
} \
|
||||
else { \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
|
||||
} \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwData; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ATIMDMACTL, &dwData); \
|
||||
if (dwData & DMACTL_RUN) \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_WAKE); \
|
||||
else \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ATIMDMACTL, DMACTL_RUN); \
|
||||
} while (0)
|
||||
|
||||
#define MACvTransmitBCN(dwIoBase) \
|
||||
{ \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY); \
|
||||
}
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_BCNDMACTL, BEACON_READY)
|
||||
|
||||
#define MACvClearStckDS(dwIoBase) \
|
||||
{ \
|
||||
unsigned char byOrgValue; \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue); \
|
||||
byOrgValue = byOrgValue & 0xFC; \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue); \
|
||||
}
|
||||
do { \
|
||||
unsigned char byOrgValue; \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_STICKHW, &byOrgValue); \
|
||||
byOrgValue = byOrgValue & 0xFC; \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_STICKHW, byOrgValue); \
|
||||
} while (0)
|
||||
|
||||
#define MACvReadISR(dwIoBase, pdwValue) \
|
||||
{ \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue); \
|
||||
}
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ISR, pdwValue)
|
||||
|
||||
#define MACvWriteISR(dwIoBase, dwValue) \
|
||||
{ \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue); \
|
||||
}
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ISR, dwValue)
|
||||
|
||||
#define MACvIntEnable(dwIoBase, dwMask) \
|
||||
{ \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask); \
|
||||
}
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_IMR, dwMask)
|
||||
|
||||
#define MACvIntDisable(dwIoBase) \
|
||||
{ \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0); \
|
||||
}
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_IMR, 0)
|
||||
|
||||
#define MACvSelectPage0(dwIoBase) \
|
||||
{ \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
||||
}
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0)
|
||||
|
||||
#define MACvSelectPage1(dwIoBase) \
|
||||
{ \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
||||
}
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1)
|
||||
|
||||
#define MACvReadMIBCounter(dwIoBase, pdwCounter) \
|
||||
{ \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR , pdwCounter); \
|
||||
}
|
||||
VNSvInPortD(dwIoBase + MAC_REG_MIBCNTR , pdwCounter)
|
||||
|
||||
#define MACvPwrEvntDisable(dwIoBase) \
|
||||
{ \
|
||||
VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000); \
|
||||
}
|
||||
VNSvOutPortW(dwIoBase + MAC_REG_WAKEUPEN0, 0x0000)
|
||||
|
||||
#define MACvEnableProtectMD(dwIoBase) \
|
||||
{ \
|
||||
unsigned long dwOrgValue; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
|
||||
dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwOrgValue; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
|
||||
dwOrgValue = dwOrgValue | EnCFG_ProtectMd; \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
|
||||
} while (0)
|
||||
|
||||
#define MACvDisableProtectMD(dwIoBase) \
|
||||
{ \
|
||||
unsigned long dwOrgValue; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
|
||||
dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwOrgValue; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
|
||||
dwOrgValue = dwOrgValue & ~EnCFG_ProtectMd; \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
|
||||
} while (0)
|
||||
|
||||
#define MACvEnableBarkerPreambleMd(dwIoBase) \
|
||||
{ \
|
||||
unsigned long dwOrgValue; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
|
||||
dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwOrgValue; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
|
||||
dwOrgValue = dwOrgValue | EnCFG_BarkerPream; \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
|
||||
} while (0)
|
||||
|
||||
#define MACvDisableBarkerPreambleMd(dwIoBase) \
|
||||
{ \
|
||||
unsigned long dwOrgValue; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
|
||||
dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwOrgValue; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
|
||||
dwOrgValue = dwOrgValue & ~EnCFG_BarkerPream; \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
|
||||
} while (0)
|
||||
|
||||
#define MACvSetBBType(dwIoBase, byTyp) \
|
||||
{ \
|
||||
unsigned long dwOrgValue; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
|
||||
dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \
|
||||
dwOrgValue = dwOrgValue | (unsigned long) byTyp; \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
|
||||
}
|
||||
do { \
|
||||
unsigned long dwOrgValue; \
|
||||
VNSvInPortD(dwIoBase + MAC_REG_ENCFG , &dwOrgValue); \
|
||||
dwOrgValue = dwOrgValue & ~EnCFG_BBType_MASK; \
|
||||
dwOrgValue = dwOrgValue | (unsigned long)byTyp; \
|
||||
VNSvOutPortD(dwIoBase + MAC_REG_ENCFG, dwOrgValue); \
|
||||
} while (0)
|
||||
|
||||
#define MACvReadATIMW(dwIoBase, pwCounter) \
|
||||
{ \
|
||||
VNSvInPortW(dwIoBase + MAC_REG_AIDATIM , pwCounter); \
|
||||
}
|
||||
VNSvInPortW(dwIoBase + MAC_REG_AIDATIM, pwCounter)
|
||||
|
||||
#define MACvWriteATIMW(dwIoBase, wCounter) \
|
||||
{ \
|
||||
VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM , wCounter); \
|
||||
}
|
||||
VNSvOutPortW(dwIoBase + MAC_REG_AIDATIM, wCounter)
|
||||
|
||||
#define MACvWriteCRC16_128(dwIoBase, byRegOfs, wCRC) \
|
||||
{ \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
||||
VNSvOutPortW(dwIoBase + byRegOfs, wCRC); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
||||
}
|
||||
do { \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 1); \
|
||||
VNSvOutPortW(dwIoBase + byRegOfs, wCRC); \
|
||||
VNSvOutPortB(dwIoBase + MAC_REG_PAGE1SEL, 0); \
|
||||
} while (0)
|
||||
|
||||
#define MACvGPIOIn(dwIoBase, pbyValue) \
|
||||
{ \
|
||||
VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue); \
|
||||
}
|
||||
VNSvInPortB(dwIoBase + MAC_REG_GPIOCTL1, pbyValue)
|
||||
|
||||
#define MACvSetRFLE_LatchBase(dwIoBase) \
|
||||
{ \
|
||||
MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT); \
|
||||
}
|
||||
MACvWordRegBitsOn(dwIoBase, MAC_REG_SOFTPWRCTL, SOFTPWRCTL_RFLEOPT)
|
||||
|
||||
/*--------------------- Export Classes ----------------------------*/
|
||||
|
||||
|
||||
@ -41,32 +41,29 @@
|
||||
|
||||
#ifdef IO_MAP
|
||||
|
||||
#define VNSvInPortB(dwIOAddress, pbyData) { \
|
||||
*(pbyData) = inb(dwIOAddress); \
|
||||
}
|
||||
#define VNSvInPortB(dwIOAddress, pbyData) \
|
||||
do { \
|
||||
*(pbyData) = inb(dwIOAddress); \
|
||||
} while (0)
|
||||
|
||||
#define VNSvInPortW(dwIOAddress, pwData) \
|
||||
do { \
|
||||
*(pwData) = inw(dwIOAddress); \
|
||||
} while (0)
|
||||
|
||||
#define VNSvInPortW(dwIOAddress, pwData) { \
|
||||
*(pwData) = inw(dwIOAddress); \
|
||||
}
|
||||
#define VNSvInPortD(dwIOAddress, pdwData) \
|
||||
do { \
|
||||
*(pdwData) = inl(dwIOAddress); \
|
||||
} while (0)
|
||||
|
||||
#define VNSvInPortD(dwIOAddress, pdwData) { \
|
||||
*(pdwData) = inl(dwIOAddress); \
|
||||
}
|
||||
#define VNSvOutPortB(dwIOAddress, byData) \
|
||||
outb(byData, dwIOAddress)
|
||||
|
||||
#define VNSvOutPortW(dwIOAddress, wData) \
|
||||
outw(wData, dwIOAddress)
|
||||
|
||||
#define VNSvOutPortB(dwIOAddress, byData) { \
|
||||
outb(byData, dwIOAddress); \
|
||||
}
|
||||
|
||||
|
||||
#define VNSvOutPortW(dwIOAddress, wData) { \
|
||||
outw(wData, dwIOAddress); \
|
||||
}
|
||||
|
||||
#define VNSvOutPortD(dwIOAddress, dwData) { \
|
||||
outl(dwData, dwIOAddress); \
|
||||
}
|
||||
#define VNSvOutPortD(dwIOAddress, dwData) \
|
||||
outl(dwData, dwIOAddress)
|
||||
|
||||
#else
|
||||
|
||||
@ -75,38 +72,43 @@
|
||||
//
|
||||
|
||||
|
||||
#define VNSvInPortB(dwIOAddress, pbyData) { \
|
||||
volatile unsigned char *pbyAddr = ((unsigned char *)(dwIOAddress)); \
|
||||
*(pbyData) = readb(pbyAddr); \
|
||||
}
|
||||
#define VNSvInPortB(dwIOAddress, pbyData) \
|
||||
do { \
|
||||
volatile unsigned char *pbyAddr = (unsigned char *)(dwIOAddress); \
|
||||
*(pbyData) = readb(pbyAddr); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define VNSvInPortW(dwIOAddress, pwData) { \
|
||||
volatile unsigned short *pwAddr = ((unsigned short *)(dwIOAddress)); \
|
||||
*(pwData) = readw(pwAddr); \
|
||||
}
|
||||
#define VNSvInPortW(dwIOAddress, pwData) \
|
||||
do { \
|
||||
volatile unsigned short *pwAddr = (unsigned short *)(dwIOAddress); \
|
||||
*(pwData) = readw(pwAddr); \
|
||||
} while (0)
|
||||
|
||||
#define VNSvInPortD(dwIOAddress, pdwData) { \
|
||||
volatile unsigned long *pdwAddr = ((unsigned long *)(dwIOAddress)); \
|
||||
*(pdwData) = readl(pdwAddr); \
|
||||
}
|
||||
#define VNSvInPortD(dwIOAddress, pdwData) \
|
||||
do { \
|
||||
volatile unsigned long *pdwAddr = (unsigned long *)(dwIOAddress); \
|
||||
*(pdwData) = readl(pdwAddr); \
|
||||
} while (0)
|
||||
|
||||
#define VNSvOutPortB(dwIOAddress, byData) \
|
||||
do { \
|
||||
volatile unsigned char *pbyAddr = (unsigned char *)(dwIOAddress); \
|
||||
writeb((unsigned char)byData, pbyAddr); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define VNSvOutPortB(dwIOAddress, byData) { \
|
||||
volatile unsigned char *pbyAddr = ((unsigned char *)(dwIOAddress)); \
|
||||
writeb((unsigned char)byData, pbyAddr); \
|
||||
}
|
||||
#define VNSvOutPortW(dwIOAddress, wData) \
|
||||
do { \
|
||||
volatile unsigned short *pwAddr = ((unsigned short *)(dwIOAddress)); \
|
||||
writew((unsigned short)wData, pwAddr); \
|
||||
} while (0)
|
||||
|
||||
|
||||
#define VNSvOutPortW(dwIOAddress, wData) { \
|
||||
volatile unsigned short *pwAddr = ((unsigned short *)(dwIOAddress)); \
|
||||
writew((unsigned short)wData, pwAddr); \
|
||||
}
|
||||
|
||||
#define VNSvOutPortD(dwIOAddress, dwData) { \
|
||||
volatile unsigned long *pdwAddr = ((unsigned long *)(dwIOAddress)); \
|
||||
writel((unsigned long)dwData, pdwAddr); \
|
||||
}
|
||||
#define VNSvOutPortD(dwIOAddress, dwData) \
|
||||
do { \
|
||||
volatile unsigned long *pdwAddr = (unsigned long *)(dwIOAddress); \
|
||||
writel((unsigned long)dwData, pdwAddr); \
|
||||
} while (0)
|
||||
|
||||
#endif
|
||||
|
||||
@ -114,43 +116,42 @@
|
||||
//
|
||||
// ALWAYS IO-Mapped IO when in 16-bit/32-bit environment
|
||||
//
|
||||
#define PCBvInPortB(dwIOAddress, pbyData) { \
|
||||
*(pbyData) = inb(dwIOAddress); \
|
||||
}
|
||||
#define PCBvInPortB(dwIOAddress, pbyData) \
|
||||
do { \
|
||||
*(pbyData) = inb(dwIOAddress); \
|
||||
} while (0)
|
||||
|
||||
#define PCBvInPortW(dwIOAddress, pwData) { \
|
||||
*(pwData) = inw(dwIOAddress); \
|
||||
}
|
||||
#define PCBvInPortW(dwIOAddress, pwData) \
|
||||
do { \
|
||||
*(pwData) = inw(dwIOAddress); \
|
||||
} while (0)
|
||||
|
||||
#define PCBvInPortD(dwIOAddress, pdwData) { \
|
||||
*(pdwData) = inl(dwIOAddress); \
|
||||
}
|
||||
#define PCBvInPortD(dwIOAddress, pdwData) \
|
||||
do { \
|
||||
*(pdwData) = inl(dwIOAddress); \
|
||||
} while (0)
|
||||
|
||||
#define PCBvOutPortB(dwIOAddress, byData) { \
|
||||
outb(byData, dwIOAddress); \
|
||||
}
|
||||
#define PCBvOutPortB(dwIOAddress, byData) \
|
||||
outb(byData, dwIOAddress)
|
||||
|
||||
#define PCBvOutPortW(dwIOAddress, wData) { \
|
||||
outw(wData, dwIOAddress); \
|
||||
}
|
||||
#define PCBvOutPortW(dwIOAddress, wData) \
|
||||
outw(wData, dwIOAddress)
|
||||
|
||||
#define PCBvOutPortD(dwIOAddress, dwData) { \
|
||||
outl(dwData, dwIOAddress); \
|
||||
}
|
||||
#define PCBvOutPortD(dwIOAddress, dwData) \
|
||||
outl(dwData, dwIOAddress)
|
||||
|
||||
|
||||
#define PCAvDelayByIO(uDelayUnit) { \
|
||||
unsigned char byData; \
|
||||
unsigned long ii; \
|
||||
#define PCAvDelayByIO(uDelayUnit) \
|
||||
do { \
|
||||
unsigned char byData; \
|
||||
unsigned long ii; \
|
||||
\
|
||||
if (uDelayUnit <= 50) { \
|
||||
udelay(uDelayUnit); \
|
||||
} \
|
||||
else { \
|
||||
for (ii = 0; ii < (uDelayUnit); ii++) \
|
||||
byData = inb(0x61); \
|
||||
} \
|
||||
}
|
||||
if (uDelayUnit <= 50) { \
|
||||
udelay(uDelayUnit); \
|
||||
} else { \
|
||||
for (ii = 0; ii < (uDelayUnit); ii++) \
|
||||
byData = inb(0x61); \
|
||||
} \
|
||||
} while (0)
|
||||
|
||||
|
||||
/*--------------------- Export Classes ----------------------------*/
|
||||
|
||||
@ -83,12 +83,13 @@
|
||||
((((PS802_11Header) pMACHeader)->wFrameCtl & TYPE_SUBTYPE_MASK) == TYPE_CTL_PSPOLL)
|
||||
|
||||
|
||||
#define ADD_ONE_WITH_WRAP_AROUND(uVar, uModulo) { \
|
||||
if ((uVar) >= ((uModulo) - 1)) \
|
||||
(uVar) = 0; \
|
||||
else \
|
||||
(uVar)++; \
|
||||
}
|
||||
#define ADD_ONE_WITH_WRAP_AROUND(uVar, uModulo) \
|
||||
do { \
|
||||
if ((uVar) >= ((uModulo) - 1)) \
|
||||
(uVar) = 0; \
|
||||
else \
|
||||
(uVar)++; \
|
||||
} while (0)
|
||||
|
||||
|
||||
/*--------------------- Export Classes ----------------------------*/
|
||||
|
||||
Loading…
Reference in New Issue
Block a user