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ARM: socfpga: dts: Remove hard coded clock-frequency property

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The timers and uart can get their clock frequencies using the common clock
driver.

Reviewed-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
This commit is contained in:
Dinh Nguyen 2014-04-02 21:14:57 -05:00
parent 58303f1f96
commit bd785efda7
3 changed files with 10 additions and 48 deletions
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10
arch/arm/boot/dts/socfpga.dtsi
View File

@ -571,24 +571,32 @@
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
interrupts = <0 167 4>; interrupts = <0 167 4>;
reg = <0xffc08000 0x1000>; reg = <0xffc08000 0x1000>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
}; };
timer1: timer1@ffc09000 { timer1: timer1@ffc09000 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
interrupts = <0 168 4>; interrupts = <0 168 4>;
reg = <0xffc09000 0x1000>; reg = <0xffc09000 0x1000>;
clocks = <&l4_sp_clk>;
clock-names = "timer";
}; };
timer2: timer2@ffd00000 { timer2: timer2@ffd00000 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
interrupts = <0 169 4>; interrupts = <0 169 4>;
reg = <0xffd00000 0x1000>; reg = <0xffd00000 0x1000>;
clocks = <&osc1>;
clock-names = "timer";
}; };
timer3: timer3@ffd01000 { timer3: timer3@ffd01000 {
compatible = "snps,dw-apb-timer"; compatible = "snps,dw-apb-timer";
interrupts = <0 170 4>; interrupts = <0 170 4>;
reg = <0xffd01000 0x1000>; reg = <0xffd01000 0x1000>;
clocks = <&osc1>;
clock-names = "timer";
}; };
uart0: serial0@ffc02000 { uart0: serial0@ffc02000 {
@ -597,6 +605,7 @@
interrupts = <0 162 4>; interrupts = <0 162 4>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&l4_sp_clk>;
}; };
uart1: serial1@ffc03000 { uart1: serial1@ffc03000 {
@ -605,6 +614,7 @@
interrupts = <0 163 4>; interrupts = <0 163 4>;
reg-shift = <2>; reg-shift = <2>;
reg-io-width = <4>; reg-io-width = <4>;
clocks = <&l4_sp_clk>;
}; };
rstmgr@ffd05000 { rstmgr@ffd05000 {

24
arch/arm/boot/dts/socfpga_arria5.dtsi
View File

@ -38,32 +38,8 @@
}; };
}; };
serial0@ffc02000 {
clock-frequency = <100000000>;
};
serial1@ffc03000 {
clock-frequency = <100000000>;
};
sysmgr@ffd08000 { sysmgr@ffd08000 {
cpu1-start-addr = <0xffd080c4>; cpu1-start-addr = <0xffd080c4>;
}; };
timer0@ffc08000 {
clock-frequency = <100000000>;
};
timer1@ffc09000 {
clock-frequency = <100000000>;
};
timer2@ffd00000 {
clock-frequency = <25000000>;
};
timer3@ffd01000 {
clock-frequency = <25000000>;
};
}; };
}; };

24
arch/arm/boot/dts/socfpga_cyclone5.dtsi
View File

@ -45,30 +45,6 @@
status = "okay"; status = "okay";
}; };
timer0@ffc08000 {
clock-frequency = <100000000>;
};
timer1@ffc09000 {
clock-frequency = <100000000>;
};
timer2@ffd00000 {
clock-frequency = <25000000>;
};
timer3@ffd01000 {
clock-frequency = <25000000>;
};
serial0@ffc02000 {
clock-frequency = <100000000>;
};
serial1@ffc03000 {
clock-frequency = <100000000>;
};
sysmgr@ffd08000 { sysmgr@ffd08000 {
cpu1-start-addr = <0xffd080c4>; cpu1-start-addr = <0xffd080c4>;
}; };