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sh: Fix IPR-IRQ's for IRQ-chip change breakage.
The conversion from IPR-IRQ to IRQ-chip resulted in the ipr data being allocated in a local variable in make_ipr_irq - breaking anything using IPR interrupts. This changes all of the callers of make_ipr_irq to allocate a static structure containing the IPR data which is then passed to make_ipr_irq. This removes the need for make_ipr_irq to allocate any additional space for the IPR information. Signed-off-by: Jamie Lenehan <lenehan@twibble.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
This commit is contained in:
Jamie Lenehan
Paul Mundt
parent
1f6c526c40
commit
bd71ab88de
@ -15,12 +15,16 @@
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#include <asm/io.h>
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#include <asm/machvec.h>
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static struct ipr_data hs77501rvoip_ipr_map[] = {
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#if defined(CONFIG_HS7751RVOIP_CODEC)
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{ DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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#endif
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};
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static void __init hs7751rvoip_init_irq(void)
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{
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#if defined(CONFIG_HS7751RVOIP_CODEC)
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make_ipr_irq(DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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make_ipr_irq(DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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#endif
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make_ipr_irq(hs77501rvoip_ipr_map, ARRAY_SIZE(hs77501rvoip_ipr_map));
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init_hs7751rvoip_IRQ();
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}
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@ -13,6 +13,51 @@
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#include <asm/io.h>
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#include <asm/irq.h>
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static struct ipr_data sh7710voipgw_ipr_map[] = {
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{ TIMER2_IRQ, TIMER2_IPR_ADDR, TIMER2_IPR_POS, TIMER2_PRIORITY },
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{ WDT_IRQ, WDT_IPR_ADDR, WDT_IPR_POS, WDT_PRIORITY },
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/* SCIF0 */
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{ SCIF0_ERI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
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{ SCIF0_RXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
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{ SCIF0_BRI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
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{ SCIF0_TXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
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/* DMAC-1 */
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{ DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE2_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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{ DMTE3_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
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/* DMAC-2 */
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{ DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
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{ DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
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/* IPSEC */
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{ IPSEC_IRQ, IPSEC_IPR_ADDR, IPSEC_IPR_POS, IPSEC_PRIORITY },
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/* EDMAC */
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{ EDMAC0_IRQ, EDMAC0_IPR_ADDR, EDMAC0_IPR_POS, EDMAC0_PRIORITY },
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{ EDMAC1_IRQ, EDMAC1_IPR_ADDR, EDMAC1_IPR_POS, EDMAC1_PRIORITY },
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{ EDMAC2_IRQ, EDMAC2_IPR_ADDR, EDMAC2_IPR_POS, EDMAC2_PRIORITY },
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/* SIOF0 */
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{ SIOF0_ERI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ SIOF0_TXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ SIOF0_RXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ SIOF0_CCI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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/* SIOF1 */
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{ SIOF1_ERI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY },
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{ SIOF1_TXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY },
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{ SIOF1_RXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY },
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{ SIOF1_CCI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS, SIOF1_PRIORITY },
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/* SLIC IRQ's */
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{ IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY },
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{ IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY },
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};
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/*
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* Initialize IRQ setting
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*/
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@ -37,65 +82,7 @@ static void __init sh7710voipgw_init_irq(void)
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*/
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ctrl_outw(0x2aa, INTC_ICR1);
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/* Now make IPR interrupts */
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make_ipr_irq(TIMER2_IRQ, TIMER2_IPR_ADDR,
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TIMER2_IPR_POS, TIMER2_PRIORITY);
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make_ipr_irq(WDT_IRQ, WDT_IPR_ADDR, WDT_IPR_POS, WDT_PRIORITY);
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/* SCIF0 */
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make_ipr_irq(SCIF0_ERI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS,
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SCIF0_PRIORITY);
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make_ipr_irq(SCIF0_RXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS,
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SCIF0_PRIORITY);
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make_ipr_irq(SCIF0_BRI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS,
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SCIF0_PRIORITY);
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make_ipr_irq(SCIF0_TXI_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS,
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SCIF0_PRIORITY);
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/* DMAC-1 */
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make_ipr_irq(DMTE0_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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make_ipr_irq(DMTE1_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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make_ipr_irq(DMTE2_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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make_ipr_irq(DMTE3_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
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/* DMAC-2 */
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make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
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make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
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/* IPSEC */
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make_ipr_irq(IPSEC_IRQ, IPSEC_IPR_ADDR, IPSEC_IPR_POS, IPSEC_PRIORITY);
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/* EDMAC */
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make_ipr_irq(EDMAC0_IRQ, EDMAC0_IPR_ADDR, EDMAC0_IPR_POS,
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EDMAC0_PRIORITY);
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make_ipr_irq(EDMAC1_IRQ, EDMAC1_IPR_ADDR, EDMAC1_IPR_POS,
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EDMAC1_PRIORITY);
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make_ipr_irq(EDMAC2_IRQ, EDMAC2_IPR_ADDR, EDMAC2_IPR_POS,
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EDMAC2_PRIORITY);
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/* SIOF0 */
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make_ipr_irq(SIOF0_ERI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS,
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SIOF0_PRIORITY);
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make_ipr_irq(SIOF0_TXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS,
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SIOF0_PRIORITY);
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make_ipr_irq(SIOF0_RXI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS,
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SIOF0_PRIORITY);
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make_ipr_irq(SIOF0_CCI_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS,
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SIOF0_PRIORITY);
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/* SIOF1 */
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make_ipr_irq(SIOF1_ERI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS,
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SIOF1_PRIORITY);
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make_ipr_irq(SIOF1_TXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS,
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SIOF1_PRIORITY);
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make_ipr_irq(SIOF1_RXI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS,
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SIOF1_PRIORITY);
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make_ipr_irq(SIOF1_CCI_IRQ, SIOF1_IPR_ADDR, SIOF1_IPR_POS,
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SIOF1_PRIORITY);
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/* SLIC IRQ's */
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make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
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make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
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make_ipr_irq(sh7710voipgw_ipr_map, ARRAY_SIZE(sh7710voipgw_ipr_map));
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}
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/*
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@ -13,6 +13,17 @@
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#include <asm/io.h>
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#include <asm/se7300.h>
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static struct ipr_data se7300_ipr_map[] = {
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/* PC_IRQ[0-3] -> IRQ0 (32) */
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{ IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, 0x0f - IRQ0_IRQ },
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/* A_IRQ[0-3] -> IRQ1 (33) */
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{ IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, 0x0f - IRQ1_IRQ },
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{ SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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};
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/*
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* Initialize IRQ setting
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*/
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@ -23,14 +34,7 @@ init_7300se_IRQ(void)
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ctrl_outw(0xa000, INTC_ICR1); /* IRQ mode; IRQ0,1 enable. */
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ctrl_outw(0x0000, PORT_PFCR); /* use F for IRQ[3:0] and SIU. */
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/* PC_IRQ[0-3] -> IRQ0 (32) */
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make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, 0x0f - IRQ0_IRQ);
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/* A_IRQ[0-3] -> IRQ1 (33) */
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make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, 0x0f - IRQ1_IRQ);
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make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
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make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
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make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
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make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
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make_ipr_irq(se7300_ipr_map, ARRAY_SIZE(se7300_ipr_map));
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ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
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}
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@ -87,13 +87,38 @@ shmse_irq_demux(int irq)
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return irq;
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}
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static struct ipr_data se73180_siof0_ipr_map[] = {
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{ SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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};
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static struct ipr_data se73180_vpu_ipr_map[] = {
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{ VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
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};
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static struct ipr_data se73180_other_ipr_map[] = {
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{ DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
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{ IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
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/* VIO interrupt */
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{ CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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{ BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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{ VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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{ LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
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};
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/*
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* Initialize IRQ setting
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*/
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void __init
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init_73180se_IRQ(void)
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{
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make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
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make_ipr_irq(se73180_siof0_ipr_map, ARRAY_SIZE(se73180_siof0_ipr_map));
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ctrl_outw(0x2000, 0xb03fffec); /* mrshpc irq enable */
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ctrl_outw(0x2000, 0xb07fffec); /* mrshpc irq enable */
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@ -101,27 +126,11 @@ init_73180se_IRQ(void)
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ctrl_outw(2 << ((7 - 5) * 2), INTC_ICR1); /* low-level irq */
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make_intreq_irq(10);
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make_ipr_irq(VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8);
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make_ipr_irq(se73180_vpu_ipr_map, ARRAY_SIZE(se73180_vpu_ipr_map));
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ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
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make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
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make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
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make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
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make_ipr_irq(IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
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make_ipr_irq(IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
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IIC0_PRIORITY);
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make_ipr_irq(IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
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IIC0_PRIORITY);
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make_ipr_irq(IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
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make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
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make_ipr_irq(SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY);
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make_ipr_irq(se73180_other_ipr_map, ARRAY_SIZE(se73180_other_ipr_map));
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/* VIO interrupt */
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make_ipr_irq(CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
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make_ipr_irq(BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
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make_ipr_irq(VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
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make_ipr_irq(LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY);
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ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
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}
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@ -102,6 +102,51 @@ shmse_irq_demux(int irq)
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static struct irqaction irq5 = { no_action, 0, CPU_MASK_NONE, "IRQ5-cascade",
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NULL, NULL};
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static struct ipr_data se7343_irq5_ipr_map[] = {
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{ IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY },
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};
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static struct ipr_data se7343_siof0_vpu_ipr_map[] = {
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{ SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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{ VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8 },
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};
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static struct ipr_data se7343_other_ipr_map[] = {
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{ DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
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{ DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
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{ DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY },
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/* I2C block */
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{ IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY },
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{ IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
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{ IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
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{ IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
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{ IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY },
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/* SIOF */
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{ SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY },
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/* SIU */
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{ SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY },
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/* VIO interrupt */
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{ CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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{ BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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{ VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
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/*MFI interrupt*/
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||||
|
||||
{ MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY },
|
||||
|
||||
/* LCD controller */
|
||||
{ LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY },
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize IRQ setting
|
||||
*/
|
||||
@ -138,54 +183,17 @@ init_7343se_IRQ(void)
|
||||
/* Setup all external interrupts to be active low */
|
||||
ctrl_outw(0xaaaa, INTC_ICR1);
|
||||
|
||||
make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR+2, IRQ5_IPR_POS, IRQ5_PRIORITY);
|
||||
make_ipr_irq(se7343_irq5_ipr_map, ARRAY_SIZE(se7343_irq5_ipr_map));
|
||||
|
||||
setup_irq(IRQ5_IRQ, &irq5);
|
||||
/* Set port control to use IRQ5 */
|
||||
*(u16 *)0xA4050108 &= ~0xc;
|
||||
|
||||
make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
|
||||
make_ipr_irq(VPU_IRQ, VPU_IPR_ADDR, VPU_IPR_POS, 8);
|
||||
make_ipr_irq(se7343_siof0_vpu_ipr_map, ARRAY_SIZE(se7343_siof0_vpu_ipr_map));
|
||||
|
||||
ctrl_outb(0x0f, INTC_IMCR5); /* enable SCIF IRQ */
|
||||
|
||||
make_ipr_irq(DMTE0_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(DMTE1_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(DMTE4_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
|
||||
make_ipr_irq(DMTE5_IRQ, DMA2_IPR_ADDR, DMA2_IPR_POS, DMA2_PRIORITY);
|
||||
make_ipr_irq(se7343_other_ipr_map, ARRAY_SIZE(se7343_other_ipr_map));
|
||||
|
||||
/* I2C block */
|
||||
make_ipr_irq(IIC0_ALI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
|
||||
make_ipr_irq(IIC0_TACKI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
|
||||
IIC0_PRIORITY);
|
||||
make_ipr_irq(IIC0_WAITI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS,
|
||||
IIC0_PRIORITY);
|
||||
make_ipr_irq(IIC0_DTEI_IRQ, IIC0_IPR_ADDR, IIC0_IPR_POS, IIC0_PRIORITY);
|
||||
|
||||
make_ipr_irq(IIC1_ALI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY);
|
||||
make_ipr_irq(IIC1_TACKI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS,
|
||||
IIC1_PRIORITY);
|
||||
make_ipr_irq(IIC1_WAITI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS,
|
||||
IIC1_PRIORITY);
|
||||
make_ipr_irq(IIC1_DTEI_IRQ, IIC1_IPR_ADDR, IIC1_IPR_POS, IIC1_PRIORITY);
|
||||
|
||||
/* SIOF */
|
||||
make_ipr_irq(SIOF0_IRQ, SIOF0_IPR_ADDR, SIOF0_IPR_POS, SIOF0_PRIORITY);
|
||||
|
||||
/* SIU */
|
||||
make_ipr_irq(SIU_IRQ, SIU_IPR_ADDR, SIU_IPR_POS, SIU_PRIORITY);
|
||||
|
||||
/* VIO interrupt */
|
||||
make_ipr_irq(CEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
|
||||
make_ipr_irq(BEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
|
||||
make_ipr_irq(VEU_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
|
||||
|
||||
/*MFI interrupt*/
|
||||
|
||||
make_ipr_irq(MFI_IRQ, MFI_IPR_ADDR, MFI_IPR_POS, MFI_PRIORITY);
|
||||
|
||||
/* LCD controller */
|
||||
make_ipr_irq(LCDC_IRQ, LCDC_IPR_ADDR, LCDC_IPR_POS, LCDC_PRIORITY);
|
||||
ctrl_outw(0x2000, PA_MRSHPC + 0x0c); /* mrshpc irq enable */
|
||||
}
|
||||
|
||||
@ -13,6 +13,48 @@
|
||||
#include <asm/io.h>
|
||||
#include <asm/se.h>
|
||||
|
||||
static struct ipr_data se770x_ipr_map[] = {
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
/* This is default value */
|
||||
{ 0xf-0x2, BCR_ILCRA, 2, 0x2 },
|
||||
{ 0xf-0xa, BCR_ILCRA, 1, 0xa },
|
||||
{ 0xf-0x5, BCR_ILCRB, 0, 0x5 },
|
||||
{ 0xf-0x8, BCR_ILCRC, 1, 0x8 },
|
||||
{ 0xf-0xc, BCR_ILCRC, 0, 0xc },
|
||||
{ 0xf-0xe, BCR_ILCRD, 3, 0xe },
|
||||
{ 0xf-0x3, BCR_ILCRD, 1, 0x3 }, /* LAN */
|
||||
{ 0xf-0xd, BCR_ILCRE, 2, 0xd },
|
||||
{ 0xf-0x9, BCR_ILCRE, 1, 0x9 },
|
||||
{ 0xf-0x1, BCR_ILCRE, 0, 0x1 },
|
||||
{ 0xf-0xf, BCR_ILCRF, 3, 0xf },
|
||||
{ 0xf-0xb, BCR_ILCRF, 1, 0xb },
|
||||
{ 0xf-0x7, BCR_ILCRG, 3, 0x7 },
|
||||
{ 0xf-0x6, BCR_ILCRG, 2, 0x6 },
|
||||
{ 0xf-0x4, BCR_ILCRG, 1, 0x4 },
|
||||
#else
|
||||
{ 14, BCR_ILCRA, 2, 0x0f-14 },
|
||||
{ 12, BCR_ILCRA, 1, 0x0f-12 },
|
||||
{ 8, BCR_ILCRB, 1, 0x0f- 8 },
|
||||
{ 6, BCR_ILCRC, 3, 0x0f- 6 },
|
||||
{ 5, BCR_ILCRC, 2, 0x0f- 5 },
|
||||
{ 4, BCR_ILCRC, 1, 0x0f- 4 },
|
||||
{ 3, BCR_ILCRC, 0, 0x0f- 3 },
|
||||
{ 1, BCR_ILCRD, 3, 0x0f- 1 },
|
||||
|
||||
{ 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */
|
||||
|
||||
{ 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */
|
||||
{ 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */
|
||||
{ 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */
|
||||
{ 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */
|
||||
|
||||
/* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
|
||||
/* NOTE: #2 and #13 are not used on PC */
|
||||
{ 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */
|
||||
{ 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize IRQ setting
|
||||
*/
|
||||
@ -38,42 +80,6 @@ void __init init_se_IRQ(void)
|
||||
ctrl_outw(0, BCR_ILCRE);
|
||||
ctrl_outw(0, BCR_ILCRF);
|
||||
ctrl_outw(0, BCR_ILCRG);
|
||||
/* This is default value */
|
||||
make_ipr_irq(0xf-0x2, BCR_ILCRA, 2, 0x2);
|
||||
make_ipr_irq(0xf-0xa, BCR_ILCRA, 1, 0xa);
|
||||
make_ipr_irq(0xf-0x5, BCR_ILCRB, 0, 0x5);
|
||||
make_ipr_irq(0xf-0x8, BCR_ILCRC, 1, 0x8);
|
||||
make_ipr_irq(0xf-0xc, BCR_ILCRC, 0, 0xc);
|
||||
make_ipr_irq(0xf-0xe, BCR_ILCRD, 3, 0xe);
|
||||
make_ipr_irq(0xf-0x3, BCR_ILCRD, 1, 0x3); /* LAN */
|
||||
make_ipr_irq(0xf-0xd, BCR_ILCRE, 2, 0xd);
|
||||
make_ipr_irq(0xf-0x9, BCR_ILCRE, 1, 0x9);
|
||||
make_ipr_irq(0xf-0x1, BCR_ILCRE, 0, 0x1);
|
||||
make_ipr_irq(0xf-0xf, BCR_ILCRF, 3, 0xf);
|
||||
make_ipr_irq(0xf-0xb, BCR_ILCRF, 1, 0xb);
|
||||
make_ipr_irq(0xf-0x7, BCR_ILCRG, 3, 0x7);
|
||||
make_ipr_irq(0xf-0x6, BCR_ILCRG, 2, 0x6);
|
||||
make_ipr_irq(0xf-0x4, BCR_ILCRG, 1, 0x4);
|
||||
#else
|
||||
make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-14);
|
||||
make_ipr_irq(12, BCR_ILCRA, 1, 0x0f-12);
|
||||
make_ipr_irq( 8, BCR_ILCRB, 1, 0x0f- 8);
|
||||
make_ipr_irq( 6, BCR_ILCRC, 3, 0x0f- 6);
|
||||
make_ipr_irq( 5, BCR_ILCRC, 2, 0x0f- 5);
|
||||
make_ipr_irq( 4, BCR_ILCRC, 1, 0x0f- 4);
|
||||
make_ipr_irq( 3, BCR_ILCRC, 0, 0x0f- 3);
|
||||
make_ipr_irq( 1, BCR_ILCRD, 3, 0x0f- 1);
|
||||
|
||||
make_ipr_irq(10, BCR_ILCRD, 1, 0x0f-10); /* LAN */
|
||||
|
||||
make_ipr_irq( 0, BCR_ILCRE, 3, 0x0f- 0); /* PCIRQ3 */
|
||||
make_ipr_irq(11, BCR_ILCRE, 2, 0x0f-11); /* PCIRQ2 */
|
||||
make_ipr_irq( 9, BCR_ILCRE, 1, 0x0f- 9); /* PCIRQ1 */
|
||||
make_ipr_irq( 7, BCR_ILCRE, 0, 0x0f- 7); /* PCIRQ0 */
|
||||
|
||||
/* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
|
||||
/* NOTE: #2 and #13 are not used on PC */
|
||||
make_ipr_irq(13, BCR_ILCRG, 1, 0x0f-13); /* SLOTIRQ2 */
|
||||
make_ipr_irq( 2, BCR_ILCRG, 0, 0x0f- 2); /* SLOTIRQ1 */
|
||||
#endif
|
||||
make_ipr_irq(se770x_ipr_map, ARRAY_SIZE(se770x_ipr_map));
|
||||
}
|
||||
|
||||
@ -14,53 +14,50 @@
|
||||
#include <asm/irq.h>
|
||||
#include <asm/se7751.h>
|
||||
|
||||
static struct ipr_data se7751_ipr_map[] = {
|
||||
/* Leave old Solution Engine code in for reference. */
|
||||
#if defined(CONFIG_SH_SOLUTION_ENGINE)
|
||||
/*
|
||||
* Super I/O (Just mimic PC):
|
||||
* 1: keyboard
|
||||
* 3: serial 0
|
||||
* 4: serial 1
|
||||
* 5: printer
|
||||
* 6: floppy
|
||||
* 8: rtc
|
||||
* 12: mouse
|
||||
* 14: ide0
|
||||
*/
|
||||
{ 14, BCR_ILCRA, 2, 0x0f-14 },
|
||||
{ 12, BCR_ILCRA, 1, 0x0f-12 },
|
||||
{ 8, BCR_ILCRB, 1, 0x0f- 8 },
|
||||
{ 6, BCR_ILCRC, 3, 0x0f- 6 },
|
||||
{ 5, BCR_ILCRC, 2, 0x0f- 5 },
|
||||
{ 4, BCR_ILCRC, 1, 0x0f- 4 },
|
||||
{ 3, BCR_ILCRC, 0, 0x0f- 3 },
|
||||
{ 1, BCR_ILCRD, 3, 0x0f- 1 },
|
||||
|
||||
{ 10, BCR_ILCRD, 1, 0x0f-10 }, /* LAN */
|
||||
|
||||
{ 0, BCR_ILCRE, 3, 0x0f- 0 }, /* PCIRQ3 */
|
||||
{ 11, BCR_ILCRE, 2, 0x0f-11 }, /* PCIRQ2 */
|
||||
{ 9, BCR_ILCRE, 1, 0x0f- 9 }, /* PCIRQ1 */
|
||||
{ 7, BCR_ILCRE, 0, 0x0f- 7 }, /* PCIRQ0 */
|
||||
|
||||
/* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
|
||||
/* NOTE: #2 and #13 are not used on PC */
|
||||
{ 13, BCR_ILCRG, 1, 0x0f-13 }, /* SLOTIRQ2 */
|
||||
{ 2, BCR_ILCRG, 0, 0x0f- 2 }, /* SLOTIRQ1 */
|
||||
#elif defined(CONFIG_SH_7751_SOLUTION_ENGINE)
|
||||
{ 13, BCR_ILCRD, 3, 2 },
|
||||
/* Add additional entries here as drivers are added and tested. */
|
||||
#endif
|
||||
};
|
||||
|
||||
/*
|
||||
* Initialize IRQ setting
|
||||
*/
|
||||
void __init init_7751se_IRQ(void)
|
||||
{
|
||||
|
||||
/* Leave old Solution Engine code in for reference. */
|
||||
#if defined(CONFIG_SH_SOLUTION_ENGINE)
|
||||
/*
|
||||
* Super I/O (Just mimic PC):
|
||||
* 1: keyboard
|
||||
* 3: serial 0
|
||||
* 4: serial 1
|
||||
* 5: printer
|
||||
* 6: floppy
|
||||
* 8: rtc
|
||||
* 12: mouse
|
||||
* 14: ide0
|
||||
*/
|
||||
make_ipr_irq(14, BCR_ILCRA, 2, 0x0f-14);
|
||||
make_ipr_irq(12, BCR_ILCRA, 1, 0x0f-12);
|
||||
make_ipr_irq( 8, BCR_ILCRB, 1, 0x0f- 8);
|
||||
make_ipr_irq( 6, BCR_ILCRC, 3, 0x0f- 6);
|
||||
make_ipr_irq( 5, BCR_ILCRC, 2, 0x0f- 5);
|
||||
make_ipr_irq( 4, BCR_ILCRC, 1, 0x0f- 4);
|
||||
make_ipr_irq( 3, BCR_ILCRC, 0, 0x0f- 3);
|
||||
make_ipr_irq( 1, BCR_ILCRD, 3, 0x0f- 1);
|
||||
|
||||
make_ipr_irq(10, BCR_ILCRD, 1, 0x0f-10); /* LAN */
|
||||
|
||||
make_ipr_irq( 0, BCR_ILCRE, 3, 0x0f- 0); /* PCIRQ3 */
|
||||
make_ipr_irq(11, BCR_ILCRE, 2, 0x0f-11); /* PCIRQ2 */
|
||||
make_ipr_irq( 9, BCR_ILCRE, 1, 0x0f- 9); /* PCIRQ1 */
|
||||
make_ipr_irq( 7, BCR_ILCRE, 0, 0x0f- 7); /* PCIRQ0 */
|
||||
|
||||
/* #2, #13 are allocated for SLOT IRQ #1 and #2 (for now) */
|
||||
/* NOTE: #2 and #13 are not used on PC */
|
||||
make_ipr_irq(13, BCR_ILCRG, 1, 0x0f-13); /* SLOTIRQ2 */
|
||||
make_ipr_irq( 2, BCR_ILCRG, 0, 0x0f- 2); /* SLOTIRQ1 */
|
||||
|
||||
#elif defined(CONFIG_SH_7751_SOLUTION_ENGINE)
|
||||
|
||||
make_ipr_irq(13, BCR_ILCRD, 3, 2);
|
||||
|
||||
/* Add additional calls to make_ipr_irq() as drivers are added
|
||||
* and tested.
|
||||
*/
|
||||
#endif
|
||||
|
||||
make_ipr_irq(se7751_ipr_map, ARRAY_SIZE(se7751_ipr_map));
|
||||
}
|
||||
|
||||
@ -14,14 +14,17 @@
|
||||
#include <asm/sh03/sh03.h>
|
||||
#include <asm/addrspace.h>
|
||||
|
||||
static struct ipr_data sh03_ipr_map[] = {
|
||||
{ IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY },
|
||||
{ IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY },
|
||||
{ IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY },
|
||||
{ IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY },
|
||||
};
|
||||
|
||||
static void __init init_sh03_IRQ(void)
|
||||
{
|
||||
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
|
||||
|
||||
make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY);
|
||||
make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY);
|
||||
make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY);
|
||||
make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY);
|
||||
make_ipr_irq(sh03_ipr_map, ARRAY_SIZE(sh03_ipr_map));
|
||||
}
|
||||
|
||||
extern void *cf_io_base;
|
||||
|
||||
@ -68,6 +68,13 @@ module_init(eraseconfig_init);
|
||||
* IRL3 = crypto
|
||||
*/
|
||||
|
||||
static struct ipr_data snapgear_ipr_map[] = {
|
||||
make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY);
|
||||
make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY);
|
||||
make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY);
|
||||
make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY);
|
||||
};
|
||||
|
||||
static void __init init_snapgear_IRQ(void)
|
||||
{
|
||||
/* enable individual interrupt mode for externals */
|
||||
@ -75,10 +82,7 @@ static void __init init_snapgear_IRQ(void)
|
||||
|
||||
printk("Setup SnapGear IRQ/IPR ...\n");
|
||||
|
||||
make_ipr_irq(IRL0_IRQ, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY);
|
||||
make_ipr_irq(IRL1_IRQ, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY);
|
||||
make_ipr_irq(IRL2_IRQ, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY);
|
||||
make_ipr_irq(IRL3_IRQ, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY);
|
||||
make_ipr_irq(snapgear_ipr_map, ARRAY_SIZE(snapgear_ipr_map));
|
||||
}
|
||||
|
||||
/*
|
||||
|
||||
@ -9,15 +9,19 @@
|
||||
|
||||
extern void __init pcibios_init_platform(void);
|
||||
|
||||
static struct ipr_data titan_ipr_map[] = {
|
||||
{ TITAN_IRQ_WAN, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY },
|
||||
{ TITAN_IRQ_LAN, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY },
|
||||
{ TITAN_IRQ_MPCIA, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY },
|
||||
{ TITAN_IRQ_USB, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY },
|
||||
};
|
||||
|
||||
static void __init init_titan_irq(void)
|
||||
{
|
||||
/* enable individual interrupt mode for externals */
|
||||
ctrl_outw(ctrl_inw(INTC_ICR) | INTC_ICR_IRLM, INTC_ICR);
|
||||
|
||||
make_ipr_irq( TITAN_IRQ_WAN, IRL0_IPR_ADDR, IRL0_IPR_POS, IRL0_PRIORITY); /* PCIRQ0 */
|
||||
make_ipr_irq( TITAN_IRQ_LAN, IRL1_IPR_ADDR, IRL1_IPR_POS, IRL1_PRIORITY); /* PCIRQ1 */
|
||||
make_ipr_irq( TITAN_IRQ_MPCIA, IRL2_IPR_ADDR, IRL2_IPR_POS, IRL2_PRIORITY); /* PCIRQ2 */
|
||||
make_ipr_irq( TITAN_IRQ_USB, IRL3_IPR_ADDR, IRL3_IPR_POS, IRL3_PRIORITY); /* PCIRQ3 */
|
||||
make_ipr_irq(titan_ipr_map, ARRAY_SIZE(titan_ipr_map));
|
||||
}
|
||||
|
||||
struct sh_machine_vector mv_titan __initmv = {
|
||||
|
||||
@ -19,23 +19,34 @@
|
||||
#include <asm/io.h>
|
||||
#include "dma-sh.h"
|
||||
|
||||
static inline unsigned int get_dmte_irq(unsigned int chan)
|
||||
{
|
||||
unsigned int irq = 0;
|
||||
|
||||
|
||||
#ifdef CONFIG_CPU_SH4
|
||||
static struct ipr_data dmae_ipr_map[] = {
|
||||
{ DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
};
|
||||
#endif
|
||||
static struct ipr_data dmte_ipr_map[] = {
|
||||
/*
|
||||
* Normally we could just do DMTE0_IRQ + chan outright, though in the
|
||||
* case of the 7751R, the DMTE IRQs for channels > 4 start right above
|
||||
* the SCIF
|
||||
*/
|
||||
if (chan < 4) {
|
||||
irq = DMTE0_IRQ + chan;
|
||||
} else {
|
||||
#ifdef DMTE4_IRQ
|
||||
irq = DMTE4_IRQ + chan - 4;
|
||||
#endif
|
||||
}
|
||||
{ DMTE0_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE0_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE0_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE0_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE4_IRQ + 0, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE4_IRQ + 1, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE4_IRQ + 2, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
{ DMTE4_IRQ + 3, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY },
|
||||
};
|
||||
|
||||
static inline unsigned int get_dmte_irq(unsigned int chan)
|
||||
{
|
||||
unsigned int irq = 0;
|
||||
if (chan < ARRAY_SIZE(dmte_ipr_map))
|
||||
irq = dmte_ipr_map[chan].irq;
|
||||
return irq;
|
||||
}
|
||||
|
||||
@ -258,17 +269,16 @@ static int __init sh_dmac_init(void)
|
||||
int i;
|
||||
|
||||
#ifdef CONFIG_CPU_SH4
|
||||
make_ipr_irq(DMAE_IRQ, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
|
||||
make_ipr_irq(dmae_ipr_map, ARRAY_SIZE(dmae_ipr_map));
|
||||
i = request_irq(DMAE_IRQ, dma_err, IRQF_DISABLED, "DMAC Address Error", 0);
|
||||
if (unlikely(i < 0))
|
||||
return i;
|
||||
#endif
|
||||
|
||||
for (i = 0; i < info->nr_channels; i++) {
|
||||
int irq = get_dmte_irq(i);
|
||||
|
||||
make_ipr_irq(irq, DMA_IPR_ADDR, DMA_IPR_POS, DMA_PRIORITY);
|
||||
}
|
||||
i = info->nr_channels;
|
||||
if (i > ARRAY_SIZE(dmte_ipr_map))
|
||||
i = ARRAY_SIZE(dmte_ipr_map);
|
||||
make_ipr_irq(dmte_ipr_map, i);
|
||||
|
||||
/*
|
||||
* Initialize DMAOR, and clean up any error flags that may have
|
||||
|
||||
@ -23,24 +23,21 @@
|
||||
#include <asm/io.h>
|
||||
#include <asm/machvec.h>
|
||||
|
||||
struct ipr_data {
|
||||
unsigned int addr; /* Address of Interrupt Priority Register */
|
||||
int shift; /* Shifts of the 16-bit data */
|
||||
int priority; /* The priority */
|
||||
};
|
||||
|
||||
static void disable_ipr_irq(unsigned int irq)
|
||||
{
|
||||
struct ipr_data *p = get_irq_chip_data(irq);
|
||||
int shift = p->shift*4;
|
||||
/* Set the priority in IPR to 0 */
|
||||
ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << p->shift)), p->addr);
|
||||
ctrl_outw(ctrl_inw(p->addr) & (0xffff ^ (0xf << shift)), p->addr);
|
||||
}
|
||||
|
||||
static void enable_ipr_irq(unsigned int irq)
|
||||
{
|
||||
struct ipr_data *p = get_irq_chip_data(irq);
|
||||
int shift = p->shift*4;
|
||||
/* Set priority in IPR back to original value */
|
||||
ctrl_outw(ctrl_inw(p->addr) | (p->priority << p->shift), p->addr);
|
||||
ctrl_outw(ctrl_inw(p->addr) | (p->priority << shift), p->addr);
|
||||
}
|
||||
|
||||
static struct irq_chip ipr_irq_chip = {
|
||||
@ -50,67 +47,57 @@ static struct irq_chip ipr_irq_chip = {
|
||||
.mask_ack = disable_ipr_irq,
|
||||
};
|
||||
|
||||
void make_ipr_irq(unsigned int irq, unsigned int addr, int pos, int priority)
|
||||
void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs)
|
||||
{
|
||||
struct ipr_data ipr_data;
|
||||
int i;
|
||||
|
||||
disable_irq_nosync(irq);
|
||||
|
||||
ipr_data.addr = addr;
|
||||
ipr_data.shift = pos*4; /* POSition (0-3) x 4 means shift */
|
||||
ipr_data.priority = priority;
|
||||
|
||||
set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
|
||||
for (i = 0; i < nr_irqs; i++) {
|
||||
unsigned int irq = table[i].irq;
|
||||
disable_irq_nosync(irq);
|
||||
set_irq_chip_and_handler_name(irq, &ipr_irq_chip,
|
||||
handle_level_irq, "level");
|
||||
set_irq_chip_data(irq, &ipr_data);
|
||||
|
||||
enable_ipr_irq(irq);
|
||||
set_irq_chip_data(irq, &table[i]);
|
||||
enable_ipr_irq(irq);
|
||||
}
|
||||
}
|
||||
EXPORT_SYMBOL(make_ipr_irq);
|
||||
|
||||
/* XXX: This needs to die a horrible death.. */
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
static struct ipr_data sys_ipr_map[] = {
|
||||
#ifndef CONFIG_CPU_SUBTYPE_SH7780
|
||||
make_ipr_irq(TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY);
|
||||
make_ipr_irq(TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY);
|
||||
{ TIMER_IRQ, TIMER_IPR_ADDR, TIMER_IPR_POS, TIMER_PRIORITY },
|
||||
{ TIMER1_IRQ, TIMER1_IPR_ADDR, TIMER1_IPR_POS, TIMER1_PRIORITY },
|
||||
#ifdef RTC_IRQ
|
||||
make_ipr_irq(RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY);
|
||||
{ RTC_IRQ, RTC_IPR_ADDR, RTC_IPR_POS, RTC_PRIORITY },
|
||||
#endif
|
||||
|
||||
#ifdef SCI_ERI_IRQ
|
||||
make_ipr_irq(SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
|
||||
make_ipr_irq(SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
|
||||
make_ipr_irq(SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY);
|
||||
{ SCI_ERI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
|
||||
{ SCI_RXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
|
||||
{ SCI_TXI_IRQ, SCI_IPR_ADDR, SCI_IPR_POS, SCI_PRIORITY },
|
||||
#endif
|
||||
|
||||
#ifdef SCIF1_ERI_IRQ
|
||||
make_ipr_irq(SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
||||
make_ipr_irq(SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
||||
make_ipr_irq(SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
||||
make_ipr_irq(SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY);
|
||||
{ SCIF1_ERI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
|
||||
{ SCIF1_RXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
|
||||
{ SCIF1_BRI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
|
||||
{ SCIF1_TXI_IRQ, SCIF1_IPR_ADDR, SCIF1_IPR_POS, SCIF1_PRIORITY },
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
|
||||
make_ipr_irq(SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY);
|
||||
make_ipr_irq(DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY);
|
||||
make_ipr_irq(VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY);
|
||||
{ SCIF0_IRQ, SCIF0_IPR_ADDR, SCIF0_IPR_POS, SCIF0_PRIORITY },
|
||||
{ DMTE2_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
|
||||
{ DMTE3_IRQ, DMA1_IPR_ADDR, DMA1_IPR_POS, DMA1_PRIORITY },
|
||||
{ VIO_IRQ, VIO_IPR_ADDR, VIO_IPR_POS, VIO_PRIORITY },
|
||||
#endif
|
||||
|
||||
#ifdef SCIF_ERI_IRQ
|
||||
make_ipr_irq(SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
||||
make_ipr_irq(SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
||||
make_ipr_irq(SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
||||
make_ipr_irq(SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY);
|
||||
{ SCIF_ERI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
|
||||
{ SCIF_RXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
|
||||
{ SCIF_BRI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
|
||||
{ SCIF_TXI_IRQ, SCIF_IPR_ADDR, SCIF_IPR_POS, SCIF_PRIORITY },
|
||||
#endif
|
||||
|
||||
#ifdef IRDA_ERI_IRQ
|
||||
make_ipr_irq(IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
||||
make_ipr_irq(IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
||||
make_ipr_irq(IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
||||
make_ipr_irq(IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY);
|
||||
{ IRDA_ERI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
|
||||
{ IRDA_RXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
|
||||
{ IRDA_BRI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
|
||||
{ IRDA_TXI_IRQ, IRDA_IPR_ADDR, IRDA_IPR_POS, IRDA_PRIORITY },
|
||||
#endif
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7707) || defined(CONFIG_CPU_SUBTYPE_SH7709) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7706) || \
|
||||
defined(CONFIG_CPU_SUBTYPE_SH7300) || defined(CONFIG_CPU_SUBTYPE_SH7705)
|
||||
@ -124,14 +111,19 @@ void __init init_IRQ(void)
|
||||
* You should set corresponding bits of PFC to "00"
|
||||
* to enable these interrupts.
|
||||
*/
|
||||
make_ipr_irq(IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY);
|
||||
make_ipr_irq(IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY);
|
||||
make_ipr_irq(IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY);
|
||||
make_ipr_irq(IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY);
|
||||
make_ipr_irq(IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY);
|
||||
make_ipr_irq(IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY);
|
||||
{ IRQ0_IRQ, IRQ0_IPR_ADDR, IRQ0_IPR_POS, IRQ0_PRIORITY },
|
||||
{ IRQ1_IRQ, IRQ1_IPR_ADDR, IRQ1_IPR_POS, IRQ1_PRIORITY },
|
||||
{ IRQ2_IRQ, IRQ2_IPR_ADDR, IRQ2_IPR_POS, IRQ2_PRIORITY },
|
||||
{ IRQ3_IRQ, IRQ3_IPR_ADDR, IRQ3_IPR_POS, IRQ3_PRIORITY },
|
||||
{ IRQ4_IRQ, IRQ4_IPR_ADDR, IRQ4_IPR_POS, IRQ4_PRIORITY },
|
||||
{ IRQ5_IRQ, IRQ5_IPR_ADDR, IRQ5_IPR_POS, IRQ5_PRIORITY },
|
||||
#endif
|
||||
#endif
|
||||
};
|
||||
|
||||
void __init init_IRQ(void)
|
||||
{
|
||||
make_ipr_irq(sys_ipr_map, ARRAY_SIZE(sys_ipr_map));
|
||||
|
||||
#ifdef CONFIG_CPU_HAS_PINT_IRQ
|
||||
init_IRQ_pint();
|
||||
@ -153,5 +145,3 @@ int ipr_irq_demux(int irq)
|
||||
return irq;
|
||||
}
|
||||
#endif
|
||||
|
||||
EXPORT_SYMBOL(make_ipr_irq);
|
||||
|
||||
@ -84,12 +84,16 @@ void make_pint_irq(unsigned int irq)
|
||||
disable_pint_irq(irq);
|
||||
}
|
||||
|
||||
static struct ipr_data pint_ipr_map[] = {
|
||||
{ PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY },
|
||||
{ PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY },
|
||||
};
|
||||
|
||||
void __init init_IRQ_pint(void)
|
||||
{
|
||||
int i;
|
||||
|
||||
make_ipr_irq(PINT0_IRQ, PINT0_IPR_ADDR, PINT0_IPR_POS, PINT0_PRIORITY);
|
||||
make_ipr_irq(PINT8_IRQ, PINT8_IPR_ADDR, PINT8_IPR_POS, PINT8_PRIORITY);
|
||||
make_ipr_irq(pint_ipr_map, ARRAY_SIZE(pint_ipr_map));
|
||||
|
||||
enable_irq(PINT0_IRQ);
|
||||
enable_irq(PINT8_IRQ);
|
||||
|
||||
@ -327,11 +327,17 @@ extern unsigned short *irq_mask_register;
|
||||
*/
|
||||
void init_IRQ_pint(void);
|
||||
|
||||
struct ipr_data {
|
||||
unsigned int irq;
|
||||
unsigned int addr; /* Address of Interrupt Priority Register */
|
||||
int shift; /* Shifts of the 16-bit data */
|
||||
int priority; /* The priority */
|
||||
};
|
||||
|
||||
/*
|
||||
* Function for "on chip support modules".
|
||||
*/
|
||||
extern void make_ipr_irq(unsigned int irq, unsigned int addr,
|
||||
int pos, int priority);
|
||||
extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs);
|
||||
extern void make_imask_irq(unsigned int irq);
|
||||
|
||||
#if defined(CONFIG_CPU_SUBTYPE_SH7300)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user