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- add clock and pinctrl nodes for mt2712e
- add High-Speed DMA and audio nodes for mt7622 -----BEGIN PGP SIGNATURE----- iQJLBAABCAA1FiEEiUuSfQSYnG8EMsBltDliWyzx00MFAlr5W6AXHG1hdHRoaWFz LmJnZ0BnbWFpbC5jb20ACgkQtDliWyzx00Mt0Q//fI6OgAkSeW1vlBd5UraLPJKQ yYo/of4SQcU3kiFuGqq9DjtJRZy5BSGkfeOQCcZ2NGBYVtM1to3Wh4IgEzZU2KMx WpzsXF9KeXJaufZYwwCY8BgWEqmfP63TvUczj5BpUYMl74lyLp9Vj7ZCyAqx+xdy SiGYGCF11za33KcbEcRfnj2tEMfkNqddMUB6bARULvWxcZgM3DBI/PmstTtCt9YU jAGjJj3WBzdvuKqkbsuQxfY0R3f2FE+uKML3zLNcvSVrUjNcDR5n78UC09OmcW5f xA7bBdGS6yVqgaL74kJj4U59dfKEmaIrMx6Gr74Hvir/0y0oXzrsm2AVaKO+o6le 1vGg5rr1hpVSz1uCIEOHAY5/C5jY/ZiZOEQUeM/JD3uAK/ZnnkmT04cP1kp3rrU6 hz+nBrDro4zkMBwvG89DOJ8OT13hXP31tB1KtQItVWVNrGzTSt9KPjIyAQzeggOj nGYDbtJD37tAhPhOFrH5UGkTSQzu91fyrLk+5b1Kd00u6A7bdO9UuwEAve3DWsi/ KqQpow+YWhsbJufCxyGJ8KdCoSDGpVV78NUnkKr3MpO1LXKK5Z3kRhuLk0+TMCEC SSqgRWJDoYGLOMeKwqGbsGGAG0cTicHVKx1JFiwRFXTEQT4LYD4W9S3JuSHluIwm Q9EZn1t3iRFcsyZbmOE= =2VGp -----END PGP SIGNATURE----- Merge tag 'v4.17-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux into next/dt - add clock and pinctrl nodes for mt2712e - add High-Speed DMA and audio nodes for mt7622 * tag 'v4.17-next-dts64' of https://git.kernel.org/pub/scm/linux/kernel/git/matthias.bgg/linux: arm64: dts: mt7622: add audio related device nodes arm64: dts: mt7622: add High-Speed DMA device nodes arm64: dts: mt2712: add pintcrl device node. arm64: dts: mt2712: add pintcrl file arm64: dts: add clock device nodes of MT2712 Signed-off-by: Olof Johansson <olof@lixom.net>
This commit is contained in:
Olof Johansson
commit
bd1b5f5855
1123
arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h
Normal file
1123
arch/arm64/boot/dts/mediatek/mt2712-pinfunc.h
Normal file
File diff suppressed because it is too large
Load Diff
@ -9,6 +9,7 @@
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/power/mt2712-power.h>
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#include "mt2712-pinfunc.h"
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/ {
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compatible = "mediatek,mt2712";
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@ -199,6 +200,34 @@
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clock-output-names = "clkaud_ext_i_2";
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};
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clki2si0_mck_i: oscillator@6 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <30000000>;
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clock-output-names = "clki2si0_mck_i";
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};
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clki2si1_mck_i: oscillator@7 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <30000000>;
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clock-output-names = "clki2si1_mck_i";
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};
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clki2si2_mck_i: oscillator@8 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <30000000>;
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clock-output-names = "clki2si2_mck_i";
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};
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clktdmin_mclk_i: oscillator@9 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <30000000>;
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clock-output-names = "clktdmin_mclk_i";
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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@ -230,6 +259,23 @@
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#clock-cells = <1>;
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};
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syscfg_pctl_a: syscfg_pctl_a@10005000 {
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compatible = "mediatek,mt2712-pctl-a-syscfg", "syscon";
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reg = <0 0x10005000 0 0x1000>;
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};
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pio: pinctrl@10005000 {
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compatible = "mediatek,mt2712-pinctrl";
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reg = <0 0x1000b000 0 0x1000>;
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mediatek,pctl-regmap = <&syscfg_pctl_a>;
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pins-are-numbered;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>;
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};
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scpsys: scpsys@10006000 {
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compatible = "mediatek,mt2712-scpsys", "syscon";
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#power-domain-cells = <1>;
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@ -18,7 +18,7 @@
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compatible = "mediatek,mt7622-rfb1", "mediatek,mt7622";
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chosen {
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bootargs = "console=ttyS0,115200n1";
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bootargs = "console=ttyS0,115200n1 swiotlb=512";
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};
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cpus {
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@ -163,10 +163,17 @@
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i2s1_pins: i2s1-pins {
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mux {
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function = "i2s";
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groups = "i2s_out_bclk_ws_mclk",
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groups = "i2s_out_mclk_bclk_ws",
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"i2s1_in_data",
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"i2s1_out_data";
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};
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conf {
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pins = "I2S1_IN", "I2S1_OUT", "I2S_BCLK",
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"I2S_WS", "I2S_MCLK";
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drive-strength = <12>;
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bias-pull-down;
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};
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};
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irrx_pins: irrx-pins {
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@ -527,6 +527,95 @@
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status = "disabled";
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};
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audsys: clock-controller@11220000 {
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compatible = "mediatek,mt7622-audsys", "syscon";
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reg = <0 0x11220000 0 0x2000>;
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#clock-cells = <1>;
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afe: audio-controller {
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compatible = "mediatek,mt7622-audio";
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interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_LOW>,
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<GIC_SPI 145 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "afe", "asys";
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clocks = <&infracfg CLK_INFRA_AUDIO_PD>,
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<&topckgen CLK_TOP_AUD1_SEL>,
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<&topckgen CLK_TOP_AUD2_SEL>,
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<&topckgen CLK_TOP_A1SYS_HP_DIV_PD>,
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<&topckgen CLK_TOP_A2SYS_HP_DIV_PD>,
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<&topckgen CLK_TOP_I2S0_MCK_SEL>,
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<&topckgen CLK_TOP_I2S1_MCK_SEL>,
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<&topckgen CLK_TOP_I2S2_MCK_SEL>,
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<&topckgen CLK_TOP_I2S3_MCK_SEL>,
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<&topckgen CLK_TOP_I2S0_MCK_DIV>,
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<&topckgen CLK_TOP_I2S1_MCK_DIV>,
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<&topckgen CLK_TOP_I2S2_MCK_DIV>,
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<&topckgen CLK_TOP_I2S3_MCK_DIV>,
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<&topckgen CLK_TOP_I2S0_MCK_DIV_PD>,
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<&topckgen CLK_TOP_I2S1_MCK_DIV_PD>,
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<&topckgen CLK_TOP_I2S2_MCK_DIV_PD>,
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<&topckgen CLK_TOP_I2S3_MCK_DIV_PD>,
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<&audsys CLK_AUDIO_I2SO1>,
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<&audsys CLK_AUDIO_I2SO2>,
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<&audsys CLK_AUDIO_I2SO3>,
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<&audsys CLK_AUDIO_I2SO4>,
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<&audsys CLK_AUDIO_I2SIN1>,
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<&audsys CLK_AUDIO_I2SIN2>,
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<&audsys CLK_AUDIO_I2SIN3>,
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<&audsys CLK_AUDIO_I2SIN4>,
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<&audsys CLK_AUDIO_ASRCO1>,
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<&audsys CLK_AUDIO_ASRCO2>,
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<&audsys CLK_AUDIO_ASRCO3>,
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<&audsys CLK_AUDIO_ASRCO4>,
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<&audsys CLK_AUDIO_AFE>,
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<&audsys CLK_AUDIO_AFE_CONN>,
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<&audsys CLK_AUDIO_A1SYS>,
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<&audsys CLK_AUDIO_A2SYS>;
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clock-names = "infra_sys_audio_clk",
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"top_audio_mux1_sel",
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"top_audio_mux2_sel",
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"top_audio_a1sys_hp",
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"top_audio_a2sys_hp",
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"i2s0_src_sel",
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"i2s1_src_sel",
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"i2s2_src_sel",
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"i2s3_src_sel",
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"i2s0_src_div",
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"i2s1_src_div",
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"i2s2_src_div",
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"i2s3_src_div",
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"i2s0_mclk_en",
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"i2s1_mclk_en",
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"i2s2_mclk_en",
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"i2s3_mclk_en",
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"i2so0_hop_ck",
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"i2so1_hop_ck",
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"i2so2_hop_ck",
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"i2so3_hop_ck",
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"i2si0_hop_ck",
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"i2si1_hop_ck",
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"i2si2_hop_ck",
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"i2si3_hop_ck",
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"asrc0_out_ck",
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"asrc1_out_ck",
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"asrc2_out_ck",
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"asrc3_out_ck",
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"audio_afe_pd",
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"audio_afe_conn_pd",
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"audio_a1sys_pd",
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"audio_a2sys_pd";
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assigned-clocks = <&topckgen CLK_TOP_A1SYS_HP_SEL>,
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<&topckgen CLK_TOP_A2SYS_HP_SEL>,
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<&topckgen CLK_TOP_A1SYS_HP_DIV>,
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<&topckgen CLK_TOP_A2SYS_HP_DIV>;
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assigned-clock-parents = <&topckgen CLK_TOP_AUD1PLL>,
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<&topckgen CLK_TOP_AUD2PLL>;
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assigned-clock-rates = <0>, <0>, <49152000>, <45158400>;
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};
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};
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mmc0: mmc@11230000 {
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compatible = "mediatek,mt7622-mmc";
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reg = <0 0x11230000 0 0x1000>;
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@ -735,6 +824,16 @@
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#reset-cells = <1>;
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};
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hsdma: dma-controller@1b007000 {
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compatible = "mediatek,mt7622-hsdma";
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reg = <0 0x1b007000 0 0x1000>;
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interrupts = <GIC_SPI 219 IRQ_TYPE_LEVEL_LOW>;
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clocks = <ðsys CLK_ETH_HSDMA_EN>;
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clock-names = "hsdma";
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power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
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#dma-cells = <1>;
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};
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eth: ethernet@1b100000 {
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compatible = "mediatek,mt7622-eth",
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"mediatek,mt2701-eth",
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