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Merge branch 'various-cleanups'

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Rosen Penev says:

====================
various cleanups

Allow CI to build. Also a bugfix for dual GMAC devices.
====================

Link: https://patch.msgid.link/20240905194938.8453-1-rosenp@gmail.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
This commit is contained in:
Jakub Kicinski 2024-09-09 17:17:45 -07:00
commit bcd138b179
2 changed files with 42 additions and 38 deletions
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4
drivers/net/ethernet/atheros/Kconfig
View File

@ -6,7 +6,7 @@
config NET_VENDOR_ATHEROS
bool "Atheros devices"
default y
depends on (PCI || ATH79)
depends on PCI || ATH79 || COMPILE_TEST
help
If you have a network (Ethernet) card belonging to this class, say Y.
@ -19,7 +19,7 @@ if NET_VENDOR_ATHEROS
config AG71XX
tristate "Atheros AR7XXX/AR9XXX built-in ethernet mac support"
depends on ATH79
depends on ATH79 || COMPILE_TEST
select PHYLINK
imply NET_SELFTESTS
help

72
drivers/net/ethernet/atheros/ag71xx.c
View File

@ -149,11 +149,11 @@
#define FIFO_CFG4_MC BIT(8) /* Multicast Packet */
#define FIFO_CFG4_BC BIT(9) /* Broadcast Packet */
#define FIFO_CFG4_DR BIT(10) /* Dribble */
#define FIFO_CFG4_LE BIT(11) /* Long Event */
#define FIFO_CFG4_CF BIT(12) /* Control Frame */
#define FIFO_CFG4_PF BIT(13) /* Pause Frame */
#define FIFO_CFG4_UO BIT(14) /* Unsupported Opcode */
#define FIFO_CFG4_VT BIT(15) /* VLAN tag detected */
#define FIFO_CFG4_CF BIT(11) /* Control Frame */
#define FIFO_CFG4_PF BIT(12) /* Pause Frame */
#define FIFO_CFG4_UO BIT(13) /* Unsupported Opcode */
#define FIFO_CFG4_VT BIT(14) /* VLAN tag detected */
#define FIFO_CFG4_LE BIT(15) /* Long Event */
#define FIFO_CFG4_FT BIT(16) /* Frame Truncated */
#define FIFO_CFG4_UC BIT(17) /* Unicast Packet */
#define FIFO_CFG4_INIT (FIFO_CFG4_DE | FIFO_CFG4_DV | FIFO_CFG4_FC | \
@ -168,28 +168,28 @@
#define FIFO_CFG5_DV BIT(1) /* RX_DV Event */
#define FIFO_CFG5_FC BIT(2) /* False Carrier */
#define FIFO_CFG5_CE BIT(3) /* Code Error */
#define FIFO_CFG5_LM BIT(4) /* Length Mismatch */
#define FIFO_CFG5_LO BIT(5) /* Length Out of Range */
#define FIFO_CFG5_OK BIT(6) /* Packet is OK */
#define FIFO_CFG5_MC BIT(7) /* Multicast Packet */
#define FIFO_CFG5_BC BIT(8) /* Broadcast Packet */
#define FIFO_CFG5_DR BIT(9) /* Dribble */
#define FIFO_CFG5_CF BIT(10) /* Control Frame */
#define FIFO_CFG5_PF BIT(11) /* Pause Frame */
#define FIFO_CFG5_UO BIT(12) /* Unsupported Opcode */
#define FIFO_CFG5_VT BIT(13) /* VLAN tag detected */
#define FIFO_CFG5_LE BIT(14) /* Long Event */
#define FIFO_CFG5_FT BIT(15) /* Frame Truncated */
#define FIFO_CFG5_16 BIT(16) /* unknown */
#define FIFO_CFG5_17 BIT(17) /* unknown */
#define FIFO_CFG5_CR BIT(4) /* CRC error */
#define FIFO_CFG5_LM BIT(5) /* Length Mismatch */
#define FIFO_CFG5_LO BIT(6) /* Length Out of Range */
#define FIFO_CFG5_OK BIT(7) /* Packet is OK */
#define FIFO_CFG5_MC BIT(8) /* Multicast Packet */
#define FIFO_CFG5_BC BIT(9) /* Broadcast Packet */
#define FIFO_CFG5_DR BIT(10) /* Dribble */
#define FIFO_CFG5_CF BIT(11) /* Control Frame */
#define FIFO_CFG5_PF BIT(12) /* Pause Frame */
#define FIFO_CFG5_UO BIT(13) /* Unsupported Opcode */
#define FIFO_CFG5_VT BIT(14) /* VLAN tag detected */
#define FIFO_CFG5_LE BIT(15) /* Long Event */
#define FIFO_CFG5_FT BIT(16) /* Frame Truncated */
#define FIFO_CFG5_UC BIT(17) /* Unicast Packet */
#define FIFO_CFG5_SF BIT(18) /* Short Frame */
#define FIFO_CFG5_BM BIT(19) /* Byte Mode */
#define FIFO_CFG5_INIT (FIFO_CFG5_DE | FIFO_CFG5_DV | FIFO_CFG5_FC | \
FIFO_CFG5_CE | FIFO_CFG5_LO | FIFO_CFG5_OK | \
FIFO_CFG5_MC | FIFO_CFG5_BC | FIFO_CFG5_DR | \
FIFO_CFG5_CF | FIFO_CFG5_PF | FIFO_CFG5_VT | \
FIFO_CFG5_LE | FIFO_CFG5_FT | FIFO_CFG5_16 | \
FIFO_CFG5_17 | FIFO_CFG5_SF)
FIFO_CFG5_CE | FIFO_CFG5_LM | FIFO_CFG5_LO | \
FIFO_CFG5_OK | FIFO_CFG5_MC | FIFO_CFG5_BC | \
FIFO_CFG5_DR | FIFO_CFG5_CF | FIFO_CFG5_UO | \
FIFO_CFG5_VT | FIFO_CFG5_LE | FIFO_CFG5_FT | \
FIFO_CFG5_UC | FIFO_CFG5_SF)
#define AG71XX_REG_TX_CTRL 0x0180
#define TX_CTRL_TXE BIT(0) /* Tx Enable */
@ -379,7 +379,6 @@ struct ag71xx {
u32 fifodata[3];
int mac_idx;
struct reset_control *mdio_reset;
struct clk *clk_mdio;
};
@ -509,8 +508,7 @@ static void ag71xx_ethtool_get_strings(struct net_device *netdev, u32 sset,
switch (sset) {
case ETH_SS_STATS:
for (i = 0; i < ARRAY_SIZE(ag71xx_statistics); i++)
memcpy(data + i * ETH_GSTRING_LEN,
ag71xx_statistics[i].name, ETH_GSTRING_LEN);
ethtool_puts(&data, ag71xx_statistics[i].name);
break;
case ETH_SS_TEST:
net_selftest_get_strings(data);
@ -690,6 +688,7 @@ static int ag71xx_mdio_probe(struct ag71xx *ag)
{
struct device *dev = &ag->pdev->dev;
struct net_device *ndev = ag->ndev;
struct reset_control *mdio_reset;
static struct mii_bus *mii_bus;
struct device_node *np, *mnp;
int err;
@ -706,10 +705,10 @@ static int ag71xx_mdio_probe(struct ag71xx *ag)
if (!mii_bus)
return -ENOMEM;
ag->mdio_reset = of_reset_control_get_exclusive(np, "mdio");
if (IS_ERR(ag->mdio_reset)) {
mdio_reset = devm_reset_control_get_exclusive(dev, "mdio");
if (IS_ERR(mdio_reset)) {
netif_err(ag, probe, ndev, "Failed to get reset mdio.\n");
return PTR_ERR(ag->mdio_reset);
return PTR_ERR(mdio_reset);
}
mii_bus->name = "ag71xx_mdio";
@ -720,12 +719,10 @@ static int ag71xx_mdio_probe(struct ag71xx *ag)
mii_bus->parent = dev;
snprintf(mii_bus->id, MII_BUS_ID_SIZE, "%s.%d", np->name, ag->mac_idx);
if (!IS_ERR(ag->mdio_reset)) {
reset_control_assert(ag->mdio_reset);
reset_control_assert(mdio_reset);
msleep(100);
reset_control_deassert(ag->mdio_reset);
reset_control_deassert(mdio_reset);
msleep(200);
}
mnp = of_get_child_by_name(np, "mdio");
err = devm_of_mdiobus_register(dev, mii_bus, mnp);
@ -1853,6 +1850,12 @@ static int ag71xx_probe(struct platform_device *pdev)
if (!ag->mac_base)
return -ENOMEM;
/* ensure that HW is in manual polling mode before interrupts are
* activated. Otherwise ag71xx_interrupt might call napi_schedule
* before it is initialized by netif_napi_add.
*/
ag71xx_int_disable(ag, AG71XX_INT_POLL);
ndev->irq = platform_get_irq(pdev, 0);
err = devm_request_irq(&pdev->dev, ndev->irq, ag71xx_interrupt,
0x0, dev_name(&pdev->dev), ndev);
@ -2033,4 +2036,5 @@ static struct platform_driver ag71xx_driver = {
};
module_platform_driver(ag71xx_driver);
MODULE_DESCRIPTION("Atheros AR71xx built-in ethernet mac driver");
MODULE_LICENSE("GPL v2");