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drm/amd/display: Various fixes for PSR on DMCUB

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[Why]
- Driver does not recognize new definitions of psr states.
- Internal tool is required for checking if psr is active.

[How]
- Parse psr state correctly so that driver will recognize psr state.
- Add visual confirmation that psr is active using existing mechanisms.

Signed-off-by: Wyatt Wood <wyatt.wood@amd.com>
Reviewed-by: Anthony Koo <Anthony.Koo@amd.com>
Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
This commit is contained in:
Wyatt Wood 2020-04-05 13:48:56 -04:00 committed by Alex Deucher
parent 7241434f88
commit bccbf13dad
3 changed files with 51 additions and 1 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
drivers/gpu/drm/amd/display/dc/dc.h
View File

@ -241,6 +241,7 @@ enum visual_confirm {
VISUAL_CONFIRM_SURFACE = 1,
VISUAL_CONFIRM_HDR = 2,
VISUAL_CONFIRM_MPCTREE = 4,
VISUAL_CONFIRM_PSR = 5,
};
enum dcc_option {

45
drivers/gpu/drm/amd/display/dc/dce/dmub_psr.c
View File

@ -32,6 +32,45 @@
#define MAX_PIPES 6
/**
* Convert dmcub psr state to dmcu psr state.
*/
static void convert_psr_state(uint32_t *psr_state)
{
if (*psr_state == 0)
*psr_state = 0;
else if (*psr_state == 0x10)
*psr_state = 1;
else if (*psr_state == 0x11)
*psr_state = 2;
else if (*psr_state == 0x20)
*psr_state = 3;
else if (*psr_state == 0x21)
*psr_state = 4;
else if (*psr_state == 0x30)
*psr_state = 5;
else if (*psr_state == 0x31)
*psr_state = 6;
else if (*psr_state == 0x40)
*psr_state = 7;
else if (*psr_state == 0x41)
*psr_state = 8;
else if (*psr_state == 0x42)
*psr_state = 9;
else if (*psr_state == 0x43)
*psr_state = 10;
else if (*psr_state == 0x44)
*psr_state = 11;
else if (*psr_state == 0x50)
*psr_state = 12;
else if (*psr_state == 0x51)
*psr_state = 13;
else if (*psr_state == 0x52)
*psr_state = 14;
else if (*psr_state == 0x53)
*psr_state = 15;
}
/**
* Get PSR state from firmware.
*/
@ -43,6 +82,8 @@ static void dmub_psr_get_state(struct dmub_psr *dmub, uint32_t *psr_state)
dmub_srv_send_gpint_command(srv, DMUB_GPINT__GET_PSR_STATE, 0, 30);
dmub_srv_get_gpint_response(srv, psr_state);
convert_psr_state(psr_state);
}
/**
@ -158,7 +199,7 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
cmd.psr_copy_settings.header.payload_bytes = sizeof(struct dmub_cmd_psr_copy_settings_data);
// Hw insts
copy_settings_data->dpphy_inst = psr_context->phyType;
copy_settings_data->dpphy_inst = psr_context->transmitterId;
copy_settings_data->aux_inst = psr_context->channel;
copy_settings_data->digfe_inst = psr_context->engineId;
copy_settings_data->digbe_inst = psr_context->transmitterId;
@ -183,6 +224,8 @@ static bool dmub_psr_copy_settings(struct dmub_psr *dmub,
copy_settings_data->smu_optimizations_en = psr_context->allow_smu_optimizations;
copy_settings_data->frame_delay = psr_context->frame_delay;
copy_settings_data->frame_cap_ind = psr_context->psrFrameCaptureIndicationReq;
copy_settings_data->debug.visual_confirm = dc->dc->debug.visual_confirm == VISUAL_CONFIRM_PSR ?
true : false;
dc_dmub_srv_cmd_queue(dc->dmub_srv, &cmd.psr_copy_settings.header);
dc_dmub_srv_cmd_execute(dc->dmub_srv);

6
drivers/gpu/drm/amd/display/dmub/inc/dmub_cmd.h
View File

@ -215,6 +215,11 @@ struct dmub_rb_cmd_dpphy_init {
uint8_t reserved[60];
};
struct dmub_psr_debug_flags {
uint8_t visual_confirm : 1;
uint8_t reserved : 7;
};
struct dmub_cmd_psr_copy_settings_data {
uint16_t psr_level;
uint8_t dpp_inst;
@ -228,6 +233,7 @@ struct dmub_cmd_psr_copy_settings_data {
uint8_t smu_optimizations_en;
uint8_t frame_delay;
uint8_t frame_cap_ind;
struct dmub_psr_debug_flags debug;
};
struct dmub_rb_cmd_psr_copy_settings {