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ASoC: mxs-saif: fix setting master base rate
The SAIF base oversample rates are either 512*fs or 384*fs. An additional divider exists within the SAIF to generate sub-multiples of these two base rates if MCLK is required by the codec. * The sub-rates for the 512x base rate are: 256x, 128x, 64x, and 32x. * The sub-rates for the 384x base rate are: 192x, 96x, and 48x. Setting the base rate depending on the modulo operation with 32 and 48 give wrong results for some mclk. If mclk=18.432MHz both modulo operations results in 0. As testing the result with 32 is done first, a wrong base rate of 512*fs is set instead of the correct 384*fs. Fix this by setting the base rate depending on the calculated sub-rate. Signed-off-by: Jörg Krause <joerg.krause@embedded.rocks> Signed-off-by: Mark Brown <broonie@kernel.org>
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@ -119,23 +119,33 @@ static int mxs_saif_set_clk(struct mxs_saif *saif,
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* Set SAIF clock
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*
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* The SAIF clock should be either 384*fs or 512*fs.
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* If MCLK is used, the SAIF clk ratio need to match mclk ratio.
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* For 32x mclk, set saif clk as 512*fs.
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* For 48x mclk, set saif clk as 384*fs.
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* If MCLK is used, the SAIF clk ratio needs to match mclk ratio.
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* For 256x, 128x, 64x, and 32x sub-rates, set saif clk as 512*fs.
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* For 192x, 96x, and 48x sub-rates, set saif clk as 384*fs.
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*
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* If MCLK is not used, we just set saif clk to 512*fs.
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*/
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clk_prepare_enable(master_saif->clk);
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if (master_saif->mclk_in_use) {
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if (mclk % 32 == 0) {
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switch (mclk / rate) {
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case 32:
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case 64:
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case 128:
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case 256:
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case 512:
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scr &= ~BM_SAIF_CTRL_BITCLK_BASE_RATE;
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ret = clk_set_rate(master_saif->clk, 512 * rate);
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} else if (mclk % 48 == 0) {
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break;
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case 48:
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case 96:
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case 192:
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case 384:
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scr |= BM_SAIF_CTRL_BITCLK_BASE_RATE;
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ret = clk_set_rate(master_saif->clk, 384 * rate);
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} else {
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/* SAIF MCLK should be either 32x or 48x */
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break;
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default:
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/* SAIF MCLK should be a sub-rate of 512x or 384x */
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clk_disable_unprepare(master_saif->clk);
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return -EINVAL;
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}
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