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Core:

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* Remove obsolete macros only used by the old nand_ecclayout struct
 * MAINTAINERS: Add entry for Qualcomm NAND controller driver
 
 Raw NAND controller drivers:
 * Arasan:
   - Prevent an unsupported configuration
 * Xway, Socrates: plat_nand, Pasemi, Orion, mpc5121, GPIO, Au1550nd, AMS-Delta:
   - Keep the driver compatible with on-die ECC engines
 * cs553x, lpc32xx_slc, ndfc, sharpsl, tmio, txx9ndfmc:
   - Revert the commits: "Fix external use of SW Hamming ECC helper"
   - And let callers use the bare Hamming helpers
 * Fsmc: Fix use of SM ORDER
 * Intel:
   - Fix potential buffer overflow in probe
 * xway, vf610, txx9ndfm, tegra, stm32, plat_nand, oxnas, omap, mtk, hisi504,
   gpmi, gpio, denali, bcm6368, atmel:
   - Make use of the helper function devm_platform_ioremap_resource{,byname}()
 
 Onenand driver:
 * Samsung: Drop Exynos4 and describe driver in KConfig
 
 Raw NAND chip drivers:
 * Hynix: Add support for H27UCG8T2ETR-BC MLC NAND
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Merge tag 'nand/for-5.16' into mtd/next

Core:
* Remove obsolete macros only used by the old nand_ecclayout struct
* MAINTAINERS: Add entry for Qualcomm NAND controller driver

Raw NAND controller drivers:
* Arasan:
  - Prevent an unsupported configuration
* Xway, Socrates: plat_nand, Pasemi, Orion, mpc5121, GPIO, Au1550nd, AMS-Delta:
  - Keep the driver compatible with on-die ECC engines
* cs553x, lpc32xx_slc, ndfc, sharpsl, tmio, txx9ndfmc:
  - Revert the commits: "Fix external use of SW Hamming ECC helper"
  - And let callers use the bare Hamming helpers
* Fsmc: Fix use of SM ORDER
* Intel:
  - Fix potential buffer overflow in probe
* xway, vf610, txx9ndfm, tegra, stm32, plat_nand, oxnas, omap, mtk, hisi504,
  gpmi, gpio, denali, bcm6368, atmel:
  - Make use of the helper function devm_platform_ioremap_resource{,byname}()

Onenand driver:
* Samsung: Drop Exynos4 and describe driver in KConfig

Raw NAND chip drivers:
* Hynix: Add support for H27UCG8T2ETR-BC MLC NAND
This commit is contained in:
Miquel Raynal 2021-11-07 17:38:05 +01:00
commit bca20e6a73
36 changed files with 169 additions and 149 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
MAINTAINERS
View File

@ -15571,6 +15571,14 @@ S: Maintained
F: Documentation/devicetree/bindings/regulator/vqmmc-ipq4019-regulator.yaml
F: drivers/regulator/vqmmc-ipq4019-regulator.c
QUALCOMM NAND CONTROLLER DRIVER
M: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
L: linux-mtd@lists.infradead.org
L: linux-arm-msm@vger.kernel.org
S: Maintained
F: Documentation/devicetree/bindings/mtd/qcom,nandc.yaml
F: drivers/mtd/nand/raw/qcom_nandc.c
QUALCOMM RMNET DRIVER
M: Subash Abhinov Kasiviswanathan <subashab@codeaurora.org>
M: Sean Tranchetti <stranche@codeaurora.org>

7
drivers/mtd/nand/ecc-sw-hamming.c
View File

@ -364,9 +364,9 @@ int nand_ecc_sw_hamming_calculate(struct nand_device *nand,
{
struct nand_ecc_sw_hamming_conf *engine_conf = nand->ecc.ctx.priv;
unsigned int step_size = nand->ecc.ctx.conf.step_size;
bool sm_order = engine_conf ? engine_conf->sm_order : false;
return ecc_sw_hamming_calculate(buf, step_size, code,
engine_conf->sm_order);
return ecc_sw_hamming_calculate(buf, step_size, code, sm_order);
}
EXPORT_SYMBOL(nand_ecc_sw_hamming_calculate);
@ -457,9 +457,10 @@ int nand_ecc_sw_hamming_correct(struct nand_device *nand, unsigned char *buf,
{
struct nand_ecc_sw_hamming_conf *engine_conf = nand->ecc.ctx.priv;
unsigned int step_size = nand->ecc.ctx.conf.step_size;
bool sm_order = engine_conf ? engine_conf->sm_order : false;
return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc, step_size,
engine_conf->sm_order);
sm_order);
}
EXPORT_SYMBOL(nand_ecc_sw_hamming_correct);

9
drivers/mtd/nand/onenand/Kconfig
View File

@ -33,11 +33,12 @@ config MTD_ONENAND_OMAP2
config MTD_ONENAND_SAMSUNG
tristate "OneNAND on Samsung SOC controller support"
depends on ARCH_S3C64XX || ARCH_S5PV210 || ARCH_EXYNOS4 || COMPILE_TEST
depends on ARCH_S3C64XX || ARCH_S5PV210 || COMPILE_TEST
help
Support for a OneNAND flash device connected to an Samsung SOC.
S3C64XX uses command mapping method.
S5PC110/S5PC210 use generic OneNAND method.
Support for a OneNAND flash device connected to Samsung S3C64XX
(using command mapping method) and S5PC110/S5PC210 (using generic
OneNAND method) SoCs.
Choose Y here only if you build for such Samsung SoC.
config MTD_ONENAND_OTP
bool "OneNAND OTP Support"

12
drivers/mtd/nand/raw/ams-delta.c
View File

@ -217,9 +217,8 @@ static int gpio_nand_setup_interface(struct nand_chip *this, int csline,
static int gpio_nand_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;
@ -370,6 +369,13 @@ static int gpio_nand_probe(struct platform_device *pdev)
/* Release write protection */
gpiod_set_value(priv->gpiod_nwp, 0);
/*
* This driver assumes that the default ECC engine should be TYPE_SOFT.
* Set ->engine_type before registering the NAND devices in order to
* provide a driver specific default value.
*/
this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
/* Scan to find existence of the device */
err = nand_scan(this, 1);
if (err)

15
drivers/mtd/nand/raw/arasan-nand-controller.c
View File

@ -973,6 +973,21 @@ static int anfc_setup_interface(struct nand_chip *chip, int target,
nvddr = nand_get_nvddr_timings(conf);
if (IS_ERR(nvddr))
return PTR_ERR(nvddr);
/*
* The controller only supports data payload requests which are
* a multiple of 4. In practice, most data accesses are 4-byte
* aligned and this is not an issue. However, rounding up will
* simply be refused by the controller if we reached the end of
* the device *and* we are using the NV-DDR interface(!). In
* this situation, unaligned data requests ending at the device
* boundary will confuse the controller and cannot be performed.
*
* This is something that happens in nand_read_subpage() when
* selecting software ECC support and must be avoided.
*/
if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT)
return -ENOTSUPP;
} else {
sdr = nand_get_sdr_timings(conf);
if (IS_ERR(sdr))

7
drivers/mtd/nand/raw/atmel/pmecc.c
View File

@ -834,7 +834,6 @@ static struct atmel_pmecc *atmel_pmecc_create(struct platform_device *pdev,
{
struct device *dev = &pdev->dev;
struct atmel_pmecc *pmecc;
struct resource *res;
pmecc = devm_kzalloc(dev, sizeof(*pmecc), GFP_KERNEL);
if (!pmecc)
@ -844,13 +843,11 @@ static struct atmel_pmecc *atmel_pmecc_create(struct platform_device *pdev,
pmecc->dev = dev;
mutex_init(&pmecc->lock);
res = platform_get_resource(pdev, IORESOURCE_MEM, pmecc_res_idx);
pmecc->regs.base = devm_ioremap_resource(dev, res);
pmecc->regs.base = devm_platform_ioremap_resource(pdev, pmecc_res_idx);
if (IS_ERR(pmecc->regs.base))
return ERR_CAST(pmecc->regs.base);
res = platform_get_resource(pdev, IORESOURCE_MEM, errloc_res_idx);
pmecc->regs.errloc = devm_ioremap_resource(dev, res);
pmecc->regs.errloc = devm_platform_ioremap_resource(pdev, errloc_res_idx);
if (IS_ERR(pmecc->regs.errloc))
return ERR_CAST(pmecc->regs.errloc);

12
drivers/mtd/nand/raw/au1550nd.c
View File

@ -239,9 +239,8 @@ static int au1550nd_exec_op(struct nand_chip *this,
static int au1550nd_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;
@ -310,6 +309,13 @@ static int au1550nd_probe(struct platform_device *pdev)
if (pd->devwidth)
this->options |= NAND_BUSWIDTH_16;
/*
* This driver assumes that the default ECC engine should be TYPE_SOFT.
* Set ->engine_type before registering the NAND devices in order to
* provide a driver specific default value.
*/
this->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
ret = nand_scan(this, 1);
if (ret) {
dev_err(&pdev->dev, "NAND scan failed with %d\n", ret);

5
drivers/mtd/nand/raw/brcmnand/bcm6368_nand.c
View File

@ -88,16 +88,13 @@ static int bcm6368_nand_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct bcm6368_nand_soc *priv;
struct brcmnand_soc *soc;
struct resource *res;
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
soc = &priv->soc;
res = platform_get_resource_byname(pdev,
IORESOURCE_MEM, "nand-int-base");
priv->base = devm_ioremap_resource(dev, res);
priv->base = devm_platform_ioremap_resource_byname(pdev, "nand-int-base");
if (IS_ERR(priv->base))
return PTR_ERR(priv->base);

12
drivers/mtd/nand/raw/cs553x_nand.c
View File

@ -18,7 +18,6 @@
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand-ecc-sw-hamming.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/iopoll.h>
@ -241,15 +240,6 @@ static int cs_calculate_ecc(struct nand_chip *this, const u_char *dat,
return 0;
}
static int cs553x_ecc_correct(struct nand_chip *chip,
unsigned char *buf,
unsigned char *read_ecc,
unsigned char *calc_ecc)
{
return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
chip->ecc.size, false);
}
static struct cs553x_nand_controller *controllers[4];
static int cs553x_attach_chip(struct nand_chip *chip)
@ -261,7 +251,7 @@ static int cs553x_attach_chip(struct nand_chip *chip)
chip->ecc.bytes = 3;
chip->ecc.hwctl = cs_enable_hwecc;
chip->ecc.calculate = cs_calculate_ecc;
chip->ecc.correct = cs553x_ecc_correct;
chip->ecc.correct = rawnand_sw_hamming_correct;
chip->ecc.strength = 1;
return 0;

7
drivers/mtd/nand/raw/denali_dt.c
View File

@ -113,7 +113,6 @@ static int denali_dt_chip_init(struct denali_controller *denali,
static int denali_dt_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct resource *res;
struct denali_dt *dt;
const struct denali_dt_data *data;
struct denali_controller *denali;
@ -139,13 +138,11 @@ static int denali_dt_probe(struct platform_device *pdev)
if (denali->irq < 0)
return denali->irq;
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "denali_reg");
denali->reg = devm_ioremap_resource(dev, res);
denali->reg = devm_platform_ioremap_resource_byname(pdev, "denali_reg");
if (IS_ERR(denali->reg))
return PTR_ERR(denali->reg);
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data");
denali->host = devm_ioremap_resource(dev, res);
denali->host = devm_platform_ioremap_resource_byname(pdev, "nand_data");
if (IS_ERR(denali->host))
return PTR_ERR(denali->host);

4
drivers/mtd/nand/raw/fsmc_nand.c
View File

@ -438,8 +438,10 @@ static int fsmc_correct_ecc1(struct nand_chip *chip,
unsigned char *read_ecc,
unsigned char *calc_ecc)
{
bool sm_order = chip->ecc.options & NAND_ECC_SOFT_HAMMING_SM_ORDER;
return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
chip->ecc.size, false);
chip->ecc.size, sm_order);
}
/* Count the number of 0's in buff upto a max of max_bits */

15
drivers/mtd/nand/raw/gpio.c
View File

@ -163,9 +163,8 @@ static int gpio_nand_exec_op(struct nand_chip *chip,
static int gpio_nand_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;
@ -303,8 +302,7 @@ static int gpio_nand_probe(struct platform_device *pdev)
chip = &gpiomtd->nand_chip;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
gpiomtd->io = devm_ioremap_resource(dev, res);
gpiomtd->io = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(gpiomtd->io))
return PTR_ERR(gpiomtd->io);
@ -365,6 +363,13 @@ static int gpio_nand_probe(struct platform_device *pdev)
if (gpiomtd->nwp && !IS_ERR(gpiomtd->nwp))
gpiod_direction_output(gpiomtd->nwp, 1);
/*
* This driver assumes that the default ECC engine should be TYPE_SOFT.
* Set ->engine_type before registering the NAND devices in order to
* provide a driver specific default value.
*/
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
ret = nand_scan(chip, 1);
if (ret)
goto err_wp;

4
drivers/mtd/nand/raw/gpmi-nand/gpmi-nand.c
View File

@ -951,11 +951,9 @@ static int acquire_register_block(struct gpmi_nand_data *this,
{
struct platform_device *pdev = this->pdev;
struct resources *res = &this->resources;
struct resource *r;
void __iomem *p;
r = platform_get_resource_byname(pdev, IORESOURCE_MEM, res_name);
p = devm_ioremap_resource(&pdev->dev, r);
p = devm_platform_ioremap_resource_byname(pdev, res_name);
if (IS_ERR(p))
return PTR_ERR(p);

7
drivers/mtd/nand/raw/hisi504_nand.c
View File

@ -738,7 +738,6 @@ static int hisi_nfc_probe(struct platform_device *pdev)
struct hinfc_host *host;
struct nand_chip *chip;
struct mtd_info *mtd;
struct resource *res;
struct device_node *np = dev->of_node;
host = devm_kzalloc(dev, sizeof(*host), GFP_KERNEL);
@ -754,13 +753,11 @@ static int hisi_nfc_probe(struct platform_device *pdev)
if (irq < 0)
return -ENXIO;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
host->iobase = devm_ioremap_resource(dev, res);
host->iobase = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(host->iobase))
return PTR_ERR(host->iobase);
res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
host->mmio = devm_ioremap_resource(dev, res);
host->mmio = devm_platform_ioremap_resource(pdev, 1);
if (IS_ERR(host->mmio))
return PTR_ERR(host->mmio);

5
drivers/mtd/nand/raw/intel-nand-controller.c
View File

@ -609,6 +609,11 @@ static int ebu_nand_probe(struct platform_device *pdev)
dev_err(dev, "failed to get chip select: %d\n", ret);
return ret;
}
if (cs >= MAX_CS) {
dev_err(dev, "got invalid chip select: %d\n", cs);
return -EINVAL;
}
ebu_host->cs_num = cs;
resname = devm_kasprintf(dev, GFP_KERNEL, "nand_cs%d", cs);

15
drivers/mtd/nand/raw/lpc32xx_slc.c
View File

@ -27,7 +27,6 @@
#include <linux/of.h>
#include <linux/of_gpio.h>
#include <linux/mtd/lpc32xx_slc.h>
#include <linux/mtd/nand-ecc-sw-hamming.h>
#define LPC32XX_MODNAME "lpc32xx-nand"
@ -345,18 +344,6 @@ static int lpc32xx_nand_ecc_calculate(struct nand_chip *chip,
return 0;
}
/*
* Corrects the data
*/
static int lpc32xx_nand_ecc_correct(struct nand_chip *chip,
unsigned char *buf,
unsigned char *read_ecc,
unsigned char *calc_ecc)
{
return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
chip->ecc.size, false);
}
/*
* Read a single byte from NAND device
*/
@ -815,7 +802,7 @@ static int lpc32xx_nand_attach_chip(struct nand_chip *chip)
chip->ecc.write_oob = lpc32xx_nand_write_oob_syndrome;
chip->ecc.read_oob = lpc32xx_nand_read_oob_syndrome;
chip->ecc.calculate = lpc32xx_nand_ecc_calculate;
chip->ecc.correct = lpc32xx_nand_ecc_correct;
chip->ecc.correct = rawnand_sw_hamming_correct;
chip->ecc.hwctl = lpc32xx_nand_ecc_enable;
/*

12
drivers/mtd/nand/raw/mpc5121_nfc.c
View File

@ -605,9 +605,8 @@ static void mpc5121_nfc_free(struct device *dev, struct mtd_info *mtd)
static int mpc5121_nfc_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;
@ -772,6 +771,13 @@ static int mpc5121_nfc_probe(struct platform_device *op)
goto error;
}
/*
* This driver assumes that the default ECC engine should be TYPE_SOFT.
* Set ->engine_type before registering the NAND devices in order to
* provide a driver specific default value.
*/
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
/* Detect NAND chips */
retval = nand_scan(chip, be32_to_cpup(chips_no));
if (retval) {

4
drivers/mtd/nand/raw/mtk_ecc.c
View File

@ -495,7 +495,6 @@ static int mtk_ecc_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct mtk_ecc *ecc;
struct resource *res;
u32 max_eccdata_size;
int irq, ret;
@ -513,8 +512,7 @@ static int mtk_ecc_probe(struct platform_device *pdev)
if (!ecc->eccdata)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ecc->regs = devm_ioremap_resource(dev, res);
ecc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ecc->regs))
return PTR_ERR(ecc->regs);

4
drivers/mtd/nand/raw/mtk_nand.c
View File

@ -1520,7 +1520,6 @@ static int mtk_nfc_probe(struct platform_device *pdev)
struct device *dev = &pdev->dev;
struct device_node *np = dev->of_node;
struct mtk_nfc *nfc;
struct resource *res;
int ret, irq;
nfc = devm_kzalloc(dev, sizeof(*nfc), GFP_KERNEL);
@ -1541,8 +1540,7 @@ static int mtk_nfc_probe(struct platform_device *pdev)
nfc->caps = of_device_get_match_data(dev);
nfc->dev = dev;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
nfc->regs = devm_ioremap_resource(dev, res);
nfc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(nfc->regs)) {
ret = PTR_ERR(nfc->regs);
goto release_ecc;

14
drivers/mtd/nand/raw/nand_hynix.c
View File

@ -686,6 +686,16 @@ h27ucg8t2atrbc_choose_interface_config(struct nand_chip *chip,
return nand_choose_best_sdr_timings(chip, iface, NULL);
}
static int h27ucg8t2etrbc_init(struct nand_chip *chip)
{
struct mtd_info *mtd = nand_to_mtd(chip);
chip->options |= NAND_NEED_SCRAMBLING;
mtd_set_pairing_scheme(mtd, &dist3_pairing_scheme);
return 0;
}
static int hynix_nand_init(struct nand_chip *chip)
{
struct hynix_nand *hynix;
@ -707,6 +717,10 @@ static int hynix_nand_init(struct nand_chip *chip)
chip->ops.choose_interface_config =
h27ucg8t2atrbc_choose_interface_config;
if (!strncmp("H27UCG8T2ETR-BC", chip->parameters.model,
sizeof("H27UCG8T2ETR-BC") - 1))
h27ucg8t2etrbc_init(chip);
ret = hynix_nand_rr_init(chip);
if (ret)
hynix_nand_cleanup(chip);

4
drivers/mtd/nand/raw/nand_ids.c
View File

@ -51,6 +51,10 @@ struct nand_flash_dev nand_flash_ids[] = {
{ .id = {0xad, 0xde, 0x94, 0xda, 0x74, 0xc4} },
SZ_8K, SZ_8K, SZ_2M, NAND_NEED_SCRAMBLING, 6, 640,
NAND_ECC_INFO(40, SZ_1K) },
{"H27UCG8T2ETR-BC 64G 3.3V 8-bit",
{ .id = {0xad, 0xde, 0x14, 0xa7, 0x42, 0x4a} },
SZ_16K, SZ_8K, SZ_4M, NAND_NEED_SCRAMBLING, 6, 1664,
NAND_ECC_INFO(40, SZ_1K) },
{"TH58NVG2S3HBAI4 4G 3.3V 8-bit",
{ .id = {0x98, 0xdc, 0x91, 0x15, 0x76} },
SZ_2K, SZ_512, SZ_128K, 0, 5, 128, NAND_ECC_INFO(8, SZ_512) },

12
drivers/mtd/nand/raw/ndfc.c
View File

@ -22,7 +22,6 @@
#include <linux/mtd/ndfc.h>
#include <linux/slab.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand-ecc-sw-hamming.h>
#include <linux/of_address.h>
#include <linux/of_platform.h>
#include <asm/io.h>
@ -101,15 +100,6 @@ static int ndfc_calculate_ecc(struct nand_chip *chip,
return 0;
}
static int ndfc_correct_ecc(struct nand_chip *chip,
unsigned char *buf,
unsigned char *read_ecc,
unsigned char *calc_ecc)
{
return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
chip->ecc.size, false);
}
/*
* Speedups for buffer read/write/verify
*
@ -155,7 +145,7 @@ static int ndfc_chip_init(struct ndfc_controller *ndfc,
chip->controller = &ndfc->ndfc_control;
chip->legacy.read_buf = ndfc_read_buf;
chip->legacy.write_buf = ndfc_write_buf;
chip->ecc.correct = ndfc_correct_ecc;
chip->ecc.correct = rawnand_sw_hamming_correct;
chip->ecc.hwctl = ndfc_enable_hwecc;
chip->ecc.calculate = ndfc_calculate_ecc;
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_ON_HOST;

5
drivers/mtd/nand/raw/omap_elm.c
View File

@ -384,7 +384,7 @@ static irqreturn_t elm_isr(int this_irq, void *dev_id)
static int elm_probe(struct platform_device *pdev)
{
int ret = 0;
struct resource *res, *irq;
struct resource *irq;
struct elm_info *info;
info = devm_kzalloc(&pdev->dev, sizeof(*info), GFP_KERNEL);
@ -399,8 +399,7 @@ static int elm_probe(struct platform_device *pdev)
return -ENODEV;
}
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
info->elm_base = devm_ioremap_resource(&pdev->dev, res);
info->elm_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(info->elm_base))
return PTR_ERR(info->elm_base);

12
drivers/mtd/nand/raw/orion_nand.c
View File

@ -85,9 +85,8 @@ static void orion_nand_read_buf(struct nand_chip *chip, uint8_t *buf, int len)
static int orion_nand_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;
@ -190,6 +189,13 @@ static int __init orion_nand_probe(struct platform_device *pdev)
return ret;
}
/*
* This driver assumes that the default ECC engine should be TYPE_SOFT.
* Set ->engine_type before registering the NAND devices in order to
* provide a driver specific default value.
*/
nc->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
ret = nand_scan(nc, 1);
if (ret)
goto no_dev;

4
drivers/mtd/nand/raw/oxnas_nand.c
View File

@ -79,7 +79,6 @@ static int oxnas_nand_probe(struct platform_device *pdev)
struct oxnas_nand_ctrl *oxnas;
struct nand_chip *chip;
struct mtd_info *mtd;
struct resource *res;
int count = 0;
int err = 0;
int i;
@ -92,8 +91,7 @@ static int oxnas_nand_probe(struct platform_device *pdev)
nand_controller_init(&oxnas->base);
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
oxnas->io_base = devm_ioremap_resource(&pdev->dev, res);
oxnas->io_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(oxnas->io_base))
return PTR_ERR(oxnas->io_base);

12
drivers/mtd/nand/raw/pasemi_nand.c
View File

@ -75,9 +75,8 @@ static int pasemi_device_ready(struct nand_chip *chip)
static int pasemi_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;
@ -154,6 +153,13 @@ static int pasemi_nand_probe(struct platform_device *ofdev)
/* Enable the following for a flash based bad block table */
chip->bbt_options = NAND_BBT_USE_FLASH;
/*
* This driver assumes that the default ECC engine should be TYPE_SOFT.
* Set ->engine_type before registering the NAND devices in order to
* provide a driver specific default value.
*/
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
/* Scan to find existence of the device */
err = nand_scan(chip, 1);
if (err)

16
drivers/mtd/nand/raw/plat_nand.c
View File

@ -21,9 +21,8 @@ struct plat_nand_data {
static int plat_nand_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;
@ -41,7 +40,6 @@ static int plat_nand_probe(struct platform_device *pdev)
struct platform_nand_data *pdata = dev_get_platdata(&pdev->dev);
struct plat_nand_data *data;
struct mtd_info *mtd;
struct resource *res;
const char **part_types;
int err = 0;
@ -65,8 +63,7 @@ static int plat_nand_probe(struct platform_device *pdev)
nand_controller_init(&data->controller);
data->chip.controller = &data->controller;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
data->io_base = devm_ioremap_resource(&pdev->dev, res);
data->io_base = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->io_base))
return PTR_ERR(data->io_base);
@ -94,6 +91,13 @@ static int plat_nand_probe(struct platform_device *pdev)
goto out;
}
/*
* This driver assumes that the default ECC engine should be TYPE_SOFT.
* Set ->engine_type before registering the NAND devices in order to
* provide a driver specific default value.
*/
data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
/* Scan to find existence of the device */
err = nand_scan(&data->chip, pdata->chip.nr_chips);
if (err)

12
drivers/mtd/nand/raw/sharpsl.c
View File

@ -11,7 +11,6 @@
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand-ecc-sw-hamming.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/mtd/sharpsl.h>
@ -97,15 +96,6 @@ static int sharpsl_nand_calculate_ecc(struct nand_chip *chip,
return readb(sharpsl->io + ECCCNTR) != 0;
}
static int sharpsl_nand_correct_ecc(struct nand_chip *chip,
unsigned char *buf,
unsigned char *read_ecc,
unsigned char *calc_ecc)
{
return ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
chip->ecc.size, false);
}
static int sharpsl_attach_chip(struct nand_chip *chip)
{
if (chip->ecc.engine_type != NAND_ECC_ENGINE_TYPE_ON_HOST)
@ -116,7 +106,7 @@ static int sharpsl_attach_chip(struct nand_chip *chip)
chip->ecc.strength = 1;
chip->ecc.hwctl = sharpsl_nand_enable_hwecc;
chip->ecc.calculate = sharpsl_nand_calculate_ecc;
chip->ecc.correct = sharpsl_nand_correct_ecc;
chip->ecc.correct = rawnand_sw_hamming_correct;
return 0;
}

12
drivers/mtd/nand/raw/socrates_nand.c
View File

@ -119,9 +119,8 @@ static int socrates_nand_device_ready(struct nand_chip *nand_chip)
static int socrates_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;
@ -175,6 +174,13 @@ static int socrates_nand_probe(struct platform_device *ofdev)
/* TODO: I have no idea what real delay is. */
nand_chip->legacy.chip_delay = 20; /* 20us command delay time */
/*
* This driver assumes that the default ECC engine should be TYPE_SOFT.
* Set ->engine_type before registering the NAND devices in order to
* provide a driver specific default value.
*/
nand_chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
dev_set_drvdata(&ofdev->dev, host);
res = nand_scan(nand_chip, 1);

8
drivers/mtd/nand/raw/stm32_fmc2_nand.c
View File

@ -1899,15 +1899,11 @@ static int stm32_fmc2_nfc_probe(struct platform_device *pdev)
nfc->data_phys_addr[chip_cs] = res->start;
res = platform_get_resource(pdev, IORESOURCE_MEM,
mem_region + 1);
nfc->cmd_base[chip_cs] = devm_ioremap_resource(dev, res);
nfc->cmd_base[chip_cs] = devm_platform_ioremap_resource(pdev, mem_region + 1);
if (IS_ERR(nfc->cmd_base[chip_cs]))
return PTR_ERR(nfc->cmd_base[chip_cs]);
res = platform_get_resource(pdev, IORESOURCE_MEM,
mem_region + 2);
nfc->addr_base[chip_cs] = devm_ioremap_resource(dev, res);
nfc->addr_base[chip_cs] = devm_platform_ioremap_resource(pdev, mem_region + 2);
if (IS_ERR(nfc->addr_base[chip_cs]))
return PTR_ERR(nfc->addr_base[chip_cs]);
}

4
drivers/mtd/nand/raw/tegra_nand.c
View File

@ -1144,7 +1144,6 @@ static int tegra_nand_probe(struct platform_device *pdev)
{
struct reset_control *rst;
struct tegra_nand_controller *ctrl;
struct resource *res;
int err = 0;
ctrl = devm_kzalloc(&pdev->dev, sizeof(*ctrl), GFP_KERNEL);
@ -1155,8 +1154,7 @@ static int tegra_nand_probe(struct platform_device *pdev)
nand_controller_init(&ctrl->controller);
ctrl->controller.ops = &tegra_nand_controller_ops;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
ctrl->regs = devm_ioremap_resource(&pdev->dev, res);
ctrl->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(ctrl->regs))
return PTR_ERR(ctrl->regs);

8
drivers/mtd/nand/raw/tmio_nand.c
View File

@ -34,7 +34,6 @@
#include <linux/interrupt.h>
#include <linux/ioport.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand-ecc-sw-hamming.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/slab.h>
@ -293,12 +292,11 @@ static int tmio_nand_correct_data(struct nand_chip *chip, unsigned char *buf,
int r0, r1;
/* assume ecc.size = 512 and ecc.bytes = 6 */
r0 = ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
chip->ecc.size, false);
r0 = rawnand_sw_hamming_correct(chip, buf, read_ecc, calc_ecc);
if (r0 < 0)
return r0;
r1 = ecc_sw_hamming_correct(buf + 256, read_ecc + 3, calc_ecc + 3,
chip->ecc.size, false);
r1 = rawnand_sw_hamming_correct(chip, buf + 256, read_ecc + 3,
calc_ecc + 3);
if (r1 < 0)
return r1;
return r0 + r1;

9
drivers/mtd/nand/raw/txx9ndfmc.c
View File

@ -13,7 +13,6 @@
#include <linux/platform_device.h>
#include <linux/delay.h>
#include <linux/mtd/mtd.h>
#include <linux/mtd/nand-ecc-sw-hamming.h>
#include <linux/mtd/rawnand.h>
#include <linux/mtd/partitions.h>
#include <linux/io.h>
@ -194,8 +193,8 @@ static int txx9ndfmc_correct_data(struct nand_chip *chip, unsigned char *buf,
int stat;
for (eccsize = chip->ecc.size; eccsize > 0; eccsize -= 256) {
stat = ecc_sw_hamming_correct(buf, read_ecc, calc_ecc,
chip->ecc.size, false);
stat = rawnand_sw_hamming_correct(chip, buf, read_ecc,
calc_ecc);
if (stat < 0)
return stat;
corrected += stat;
@ -284,13 +283,11 @@ static int __init txx9ndfmc_probe(struct platform_device *dev)
int i;
struct txx9ndfmc_drvdata *drvdata;
unsigned long gbusclk = plat->gbus_clock;
struct resource *res;
drvdata = devm_kzalloc(&dev->dev, sizeof(*drvdata), GFP_KERNEL);
if (!drvdata)
return -ENOMEM;
res = platform_get_resource(dev, IORESOURCE_MEM, 0);
drvdata->base = devm_ioremap_resource(&dev->dev, res);
drvdata->base = devm_platform_ioremap_resource(dev, 0);
if (IS_ERR(drvdata->base))
return PTR_ERR(drvdata->base);

4
drivers/mtd/nand/raw/vf610_nfc.c
View File

@ -807,7 +807,6 @@ static const struct nand_controller_ops vf610_nfc_controller_ops = {
static int vf610_nfc_probe(struct platform_device *pdev)
{
struct vf610_nfc *nfc;
struct resource *res;
struct mtd_info *mtd;
struct nand_chip *chip;
struct device_node *child;
@ -831,8 +830,7 @@ static int vf610_nfc_probe(struct platform_device *pdev)
if (irq <= 0)
return -EINVAL;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
nfc->regs = devm_ioremap_resource(nfc->dev, res);
nfc->regs = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(nfc->regs))
return PTR_ERR(nfc->regs);

16
drivers/mtd/nand/raw/xway_nand.c
View File

@ -148,9 +148,8 @@ static void xway_write_buf(struct nand_chip *chip, const u_char *buf, int len)
static int xway_attach_chip(struct nand_chip *chip)
{
chip->ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
if (chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
if (chip->ecc.engine_type == NAND_ECC_ENGINE_TYPE_SOFT &&
chip->ecc.algo == NAND_ECC_ALGO_UNKNOWN)
chip->ecc.algo = NAND_ECC_ALGO_HAMMING;
return 0;
@ -167,7 +166,6 @@ static int xway_nand_probe(struct platform_device *pdev)
{
struct xway_nand_data *data;
struct mtd_info *mtd;
struct resource *res;
int err;
u32 cs;
u32 cs_flag = 0;
@ -178,8 +176,7 @@ static int xway_nand_probe(struct platform_device *pdev)
if (!data)
return -ENOMEM;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
data->nandaddr = devm_ioremap_resource(&pdev->dev, res);
data->nandaddr = devm_platform_ioremap_resource(pdev, 0);
if (IS_ERR(data->nandaddr))
return PTR_ERR(data->nandaddr);
@ -219,6 +216,13 @@ static int xway_nand_probe(struct platform_device *pdev)
| NAND_CON_SE_P | NAND_CON_WP_P | NAND_CON_PRE_P
| cs_flag, EBU_NAND_CON);
/*
* This driver assumes that the default ECC engine should be TYPE_SOFT.
* Set ->engine_type before registering the NAND devices in order to
* provide a driver specific default value.
*/
data->chip.ecc.engine_type = NAND_ECC_ENGINE_TYPE_SOFT;
/* Scan to find existence of the device */
err = nand_scan(&data->chip, 1);
if (err)

2
include/linux/mtd/mtd.h
View File

@ -72,8 +72,6 @@ struct mtd_oob_ops {
uint8_t *oobbuf;
};
#define MTD_MAX_OOBFREE_ENTRIES_LARGE 32
#define MTD_MAX_ECCPOS_ENTRIES_LARGE 640
/**
* struct mtd_oob_region - oob region definition
* @offset: region offset