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[PATCH] powerpc: kill union tce_entry
It's been long overdue to kill the union tce_entry in the pSeries/iSeries TCE code, especially since I asked the Summit guys to do it on the code they copied from us. Also, while I was at it, I cleaned up some whitespace. Built and booted on pSeries, built on iSeries. Signed-off-by: Olof Johansson <olof@lixom.net> Signed-off-by: Paul Mackerras <paulus@samba.org>
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@ -4,6 +4,7 @@
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* Rewrite, cleanup:
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*
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
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* Copyright (C) 2006 Olof Johansson <olof@lixom.net>
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*
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* Dynamic DMA mapping support, iSeries-specific parts.
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*
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@ -42,30 +43,28 @@ static void tce_build_iSeries(struct iommu_table *tbl, long index, long npages,
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unsigned long uaddr, enum dma_data_direction direction)
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{
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u64 rc;
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union tce_entry tce;
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u64 tce, rpn;
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index <<= TCE_PAGE_FACTOR;
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npages <<= TCE_PAGE_FACTOR;
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while (npages--) {
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tce.te_word = 0;
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tce.te_bits.tb_rpn = virt_to_abs(uaddr) >> TCE_SHIFT;
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rpn = virt_to_abs(uaddr) >> TCE_SHIFT;
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tce = (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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if (tbl->it_type == TCE_VB) {
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/* Virtual Bus */
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tce.te_bits.tb_valid = 1;
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tce.te_bits.tb_allio = 1;
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tce |= TCE_VALID|TCE_ALLIO;
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if (direction != DMA_TO_DEVICE)
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tce.te_bits.tb_rdwr = 1;
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tce |= TCE_VB_WRITE;
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} else {
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/* PCI Bus */
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tce.te_bits.tb_rdwr = 1; /* Read allowed */
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tce |= TCE_PCI_READ; /* Read allowed */
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if (direction != DMA_TO_DEVICE)
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tce.te_bits.tb_pciwr = 1;
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tce |= TCE_PCI_WRITE;
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}
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rc = HvCallXm_setTce((u64)tbl->it_index, (u64)index,
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tce.te_word);
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rc = HvCallXm_setTce((u64)tbl->it_index, (u64)index, tce);
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if (rc)
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panic("PCI_DMA: HvCallXm_setTce failed, Rc: 0x%lx\n",
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rc);
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@ -123,7 +122,7 @@ void iommu_table_getparms_iSeries(unsigned long busno,
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/* itc_size is in pages worth of table, it_size is in # of entries */
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tbl->it_size = ((parms->itc_size * TCE_PAGE_SIZE) /
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sizeof(union tce_entry)) >> TCE_PAGE_FACTOR;
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TCE_ENTRY_SIZE) >> TCE_PAGE_FACTOR;
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tbl->it_busno = parms->itc_busno;
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tbl->it_offset = parms->itc_offset >> TCE_PAGE_FACTOR;
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tbl->it_index = parms->itc_index;
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@ -4,6 +4,7 @@
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* Rewrite, cleanup:
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*
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* Copyright (C) 2004 Olof Johansson <olof@lixom.net>, IBM Corporation
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* Copyright (C) 2006 Olof Johansson <olof@lixom.net>
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*
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* Dynamic DMA mapping support, pSeries-specific parts, both SMP and LPAR.
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*
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@ -53,48 +54,42 @@ static void tce_build_pSeries(struct iommu_table *tbl, long index,
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long npages, unsigned long uaddr,
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enum dma_data_direction direction)
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{
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union tce_entry t;
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union tce_entry *tp;
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u64 proto_tce;
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u64 *tcep;
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u64 rpn;
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index <<= TCE_PAGE_FACTOR;
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npages <<= TCE_PAGE_FACTOR;
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t.te_word = 0;
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t.te_rdwr = 1; // Read allowed
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proto_tce = TCE_PCI_READ; // Read allowed
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if (direction != DMA_TO_DEVICE)
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t.te_pciwr = 1;
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proto_tce |= TCE_PCI_WRITE;
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tp = ((union tce_entry *)tbl->it_base) + index;
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tcep = ((u64 *)tbl->it_base) + index;
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while (npages--) {
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/* can't move this out since we might cross LMB boundary */
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t.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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tp->te_word = t.te_word;
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rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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*tcep = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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uaddr += TCE_PAGE_SIZE;
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tp++;
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tcep++;
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}
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}
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static void tce_free_pSeries(struct iommu_table *tbl, long index, long npages)
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{
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union tce_entry t;
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union tce_entry *tp;
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u64 *tcep;
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npages <<= TCE_PAGE_FACTOR;
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index <<= TCE_PAGE_FACTOR;
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t.te_word = 0;
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tp = ((union tce_entry *)tbl->it_base) + index;
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tcep = ((u64 *)tbl->it_base) + index;
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while (npages--) {
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tp->te_word = t.te_word;
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tp++;
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}
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while (npages--)
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*(tcep++) = 0;
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}
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@ -103,43 +98,44 @@ static void tce_build_pSeriesLP(struct iommu_table *tbl, long tcenum,
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enum dma_data_direction direction)
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{
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u64 rc;
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union tce_entry tce;
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u64 proto_tce, tce;
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u64 rpn;
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tcenum <<= TCE_PAGE_FACTOR;
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npages <<= TCE_PAGE_FACTOR;
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tce.te_word = 0;
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tce.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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tce.te_rdwr = 1;
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rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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proto_tce = TCE_PCI_READ;
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if (direction != DMA_TO_DEVICE)
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tce.te_pciwr = 1;
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proto_tce |= TCE_PCI_WRITE;
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while (npages--) {
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rc = plpar_tce_put((u64)tbl->it_index,
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(u64)tcenum << 12,
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tce.te_word );
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tce = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, tce);
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if (rc && printk_ratelimit()) {
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printk("tce_build_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\ttcenum = 0x%lx\n", (u64)tcenum);
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printk("\ttce val = 0x%lx\n", tce.te_word );
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printk("\ttce val = 0x%lx\n", tce );
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show_stack(current, (unsigned long *)__get_SP());
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}
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tcenum++;
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tce.te_rpn++;
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rpn++;
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}
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}
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static DEFINE_PER_CPU(void *, tce_page) = NULL;
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static DEFINE_PER_CPU(u64 *, tce_page) = NULL;
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static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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long npages, unsigned long uaddr,
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enum dma_data_direction direction)
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{
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u64 rc;
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union tce_entry tce, *tcep;
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u64 proto_tce;
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u64 *tcep;
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u64 rpn;
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long l, limit;
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if (TCE_PAGE_FACTOR == 0 && npages == 1)
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@ -152,7 +148,7 @@ static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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* from iommu_alloc{,_sg}()
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*/
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if (!tcep) {
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tcep = (void *)__get_free_page(GFP_ATOMIC);
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tcep = (u64 *)__get_free_page(GFP_ATOMIC);
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/* If allocation fails, fall back to the loop implementation */
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if (!tcep)
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return tce_build_pSeriesLP(tbl, tcenum, npages,
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@ -163,11 +159,10 @@ static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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tcenum <<= TCE_PAGE_FACTOR;
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npages <<= TCE_PAGE_FACTOR;
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tce.te_word = 0;
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tce.te_rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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tce.te_rdwr = 1;
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rpn = (virt_to_abs(uaddr)) >> TCE_SHIFT;
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proto_tce = TCE_PCI_READ;
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if (direction != DMA_TO_DEVICE)
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tce.te_pciwr = 1;
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proto_tce |= TCE_PCI_WRITE;
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/* We can map max one pageful of TCEs at a time */
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do {
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@ -175,11 +170,11 @@ static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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* Set up the page with TCE data, looping through and setting
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* the values.
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*/
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limit = min_t(long, npages, 4096/sizeof(union tce_entry));
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limit = min_t(long, npages, 4096/TCE_ENTRY_SIZE);
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for (l = 0; l < limit; l++) {
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tcep[l] = tce;
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tce.te_rpn++;
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tcep[l] = proto_tce | (rpn & TCE_RPN_MASK) << TCE_RPN_SHIFT;
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rpn++;
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}
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rc = plpar_tce_put_indirect((u64)tbl->it_index,
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@ -195,7 +190,7 @@ static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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printk("tce_buildmulti_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\tnpages = 0x%lx\n", (u64)npages);
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printk("\ttce[0] val = 0x%lx\n", tcep[0].te_word);
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printk("\ttce[0] val = 0x%lx\n", tcep[0]);
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show_stack(current, (unsigned long *)__get_SP());
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}
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}
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@ -203,23 +198,17 @@ static void tce_buildmulti_pSeriesLP(struct iommu_table *tbl, long tcenum,
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static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
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{
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u64 rc;
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union tce_entry tce;
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tcenum <<= TCE_PAGE_FACTOR;
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npages <<= TCE_PAGE_FACTOR;
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tce.te_word = 0;
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while (npages--) {
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rc = plpar_tce_put((u64)tbl->it_index,
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(u64)tcenum << 12,
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tce.te_word);
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rc = plpar_tce_put((u64)tbl->it_index, (u64)tcenum << 12, 0);
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if (rc && printk_ratelimit()) {
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printk("tce_free_pSeriesLP: plpar_tce_put failed. rc=%ld\n", rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\ttcenum = 0x%lx\n", (u64)tcenum);
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printk("\ttce val = 0x%lx\n", tce.te_word );
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show_stack(current, (unsigned long *)__get_SP());
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}
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@ -231,24 +220,17 @@ static void tce_free_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages
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static void tce_freemulti_pSeriesLP(struct iommu_table *tbl, long tcenum, long npages)
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{
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u64 rc;
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union tce_entry tce;
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tcenum <<= TCE_PAGE_FACTOR;
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npages <<= TCE_PAGE_FACTOR;
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tce.te_word = 0;
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rc = plpar_tce_stuff((u64)tbl->it_index,
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(u64)tcenum << 12,
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tce.te_word,
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npages);
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rc = plpar_tce_stuff((u64)tbl->it_index, (u64)tcenum << 12, 0, npages);
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if (rc && printk_ratelimit()) {
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printk("tce_freemulti_pSeriesLP: plpar_tce_stuff failed\n");
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printk("\trc = %ld\n", rc);
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printk("\tindex = 0x%lx\n", (u64)tbl->it_index);
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printk("\tnpages = 0x%lx\n", (u64)npages);
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printk("\ttce val = 0x%lx\n", tce.te_word );
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show_stack(current, (unsigned long *)__get_SP());
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}
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}
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@ -35,32 +35,15 @@
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#define TCE_PAGE_SIZE (1 << TCE_SHIFT)
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#define TCE_PAGE_FACTOR (PAGE_SHIFT - TCE_SHIFT)
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#define TCE_ENTRY_SIZE 8 /* each TCE is 64 bits */
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/* tce_entry
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* Used by pSeries (SMP) and iSeries/pSeries LPAR, but there it's
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* abstracted so layout is irrelevant.
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*/
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union tce_entry {
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unsigned long te_word;
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struct {
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unsigned int tb_cacheBits :6; /* Cache hash bits - not used */
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unsigned int tb_rsvd :6;
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unsigned long tb_rpn :40; /* Real page number */
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unsigned int tb_valid :1; /* Tce is valid (vb only) */
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unsigned int tb_allio :1; /* Tce is valid for all lps (vb only) */
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unsigned int tb_lpindex :8; /* LpIndex for user of TCE (vb only) */
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unsigned int tb_pciwr :1; /* Write allowed (pci only) */
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unsigned int tb_rdwr :1; /* Read allowed (pci), Write allowed (vb) */
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} te_bits;
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#define te_cacheBits te_bits.tb_cacheBits
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#define te_rpn te_bits.tb_rpn
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#define te_valid te_bits.tb_valid
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#define te_allio te_bits.tb_allio
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#define te_lpindex te_bits.tb_lpindex
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#define te_pciwr te_bits.tb_pciwr
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#define te_rdwr te_bits.tb_rdwr
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};
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#define TCE_RPN_MASK 0xfffffffffful /* 40-bit RPN (4K pages) */
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#define TCE_RPN_SHIFT 12
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#define TCE_VALID 0x800 /* TCE valid */
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#define TCE_ALLIO 0x400 /* TCE valid for all lpars */
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#define TCE_PCI_WRITE 0x2 /* write from PCI allowed */
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#define TCE_PCI_READ 0x1 /* read from PCI allowed */
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#define TCE_VB_WRITE 0x1 /* write from VB allowed */
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#endif /* __KERNEL__ */
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#endif /* _ASM_POWERPC_TCE_H */
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