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mmc: dw_mmc: improve dw_mci_reset a bit
Too much condition iteration makes the code less readable. Slightly improve it. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
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@ -1699,6 +1699,7 @@ static bool dw_mci_reset(struct dw_mci *host)
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{
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u32 flags = SDMMC_CTRL_RESET | SDMMC_CTRL_FIFO_RESET;
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bool ret = false;
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u32 status = 0;
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/*
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* Resetting generates a block interrupt, hence setting
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@ -1714,29 +1715,30 @@ static bool dw_mci_reset(struct dw_mci *host)
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if (dw_mci_ctrl_reset(host, flags)) {
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/*
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* In all cases we clear the RAWINTS register to clear any
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* interrupts.
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* In all cases we clear the RAWINTS
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* register to clear any interrupts.
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*/
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mci_writel(host, RINTSTS, 0xFFFFFFFF);
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/* if using dma we wait for dma_req to clear */
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if (host->use_dma) {
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u32 status;
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if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
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status,
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!(status & SDMMC_STATUS_DMA_REQ),
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1, 500 * USEC_PER_MSEC)) {
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dev_err(host->dev,
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"%s: Timeout waiting for dma_req to clear during reset\n",
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__func__);
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goto ciu_out;
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}
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/* when using DMA next we reset the fifo again */
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if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
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goto ciu_out;
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if (!host->use_dma) {
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ret = true;
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goto ciu_out;
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}
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/* Wait for dma_req to be cleared */
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if (readl_poll_timeout_atomic(host->regs + SDMMC_STATUS,
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status,
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!(status & SDMMC_STATUS_DMA_REQ),
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1, 500 * USEC_PER_MSEC)) {
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dev_err(host->dev,
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"%s: Timeout waiting for dma_req to be cleared\n",
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__func__);
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goto ciu_out;
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}
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/* when using DMA next we reset the fifo again */
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if (!dw_mci_ctrl_reset(host, SDMMC_CTRL_FIFO_RESET))
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goto ciu_out;
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} else {
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/* if the controller reset bit did clear, then set clock regs */
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if (!(mci_readl(host, CTRL) & SDMMC_CTRL_RESET)) {
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