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Merge remote-tracking branch 'kumar/next' into next
From Kumar Gala: << Add support for T4 and B4 SoC families from Freescale, e6500 altivec support, some various board fixes and other minor cleanups. >>
This commit is contained in:
Benjamin Herrenschmidt
commit
bc23100a0d
22
Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
Normal file
22
Documentation/devicetree/bindings/powerpc/fsl/cpus.txt
Normal file
@ -0,0 +1,22 @@
|
||||
===================================================================
|
||||
Power Architecture CPU Binding
|
||||
Copyright 2013 Freescale Semiconductor Inc.
|
||||
|
||||
Power Architecture CPUs in Freescale SOCs are represented in device trees as
|
||||
per the definition in ePAPR.
|
||||
|
||||
In addition to the ePAPR definitions, the properties defined below may be
|
||||
present on CPU nodes.
|
||||
|
||||
PROPERTIES
|
||||
|
||||
- fsl,eref-*
|
||||
Usage: optional
|
||||
Value type: <empty>
|
||||
Definition: The EREF (EREF: A Programmer.s Reference Manual for
|
||||
Freescale Power Architecture) defines the architecture for Freescale
|
||||
Power CPUs. The EREF defines some architecture categories not defined
|
||||
by the Power ISA. For these EREF-specific categories, the existence of
|
||||
a property named fsl,eref-[CAT], where [CAT] is the abbreviated category
|
||||
name with all uppercase letters converted to lowercase, indicates that
|
||||
the category is supported by the implementation.
|
||||
@ -681,7 +681,6 @@ config SBUS
|
||||
config FSL_SOC
|
||||
bool
|
||||
select HAVE_CAN_FLEXCAN if NET && CAN
|
||||
select PPC_CLOCK
|
||||
|
||||
config FSL_PCI
|
||||
bool
|
||||
@ -769,11 +768,6 @@ config PCI_8260
|
||||
select PPC_INDIRECT_PCI
|
||||
default y
|
||||
|
||||
config 8260_PCI9
|
||||
bool "Enable workaround for MPC826x erratum PCI 9"
|
||||
depends on PCI_8260 && !8272
|
||||
default y
|
||||
|
||||
source "drivers/pci/pcie/Kconfig"
|
||||
|
||||
source "drivers/pci/Kconfig"
|
||||
|
||||
50
arch/powerpc/boot/dts/b4420qds.dts
Normal file
50
arch/powerpc/boot/dts/b4420qds.dts
Normal file
@ -0,0 +1,50 @@
|
||||
/*
|
||||
* B4420DS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/include/ "fsl/b4420si-pre.dtsi"
|
||||
/include/ "b4qds.dts"
|
||||
|
||||
/ {
|
||||
model = "fsl,B4420QDS";
|
||||
compatible = "fsl,B4420QDS";
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,b4420qds-fpga", "fsl,fpga-qixis";
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "fsl/b4420si-post.dtsi"
|
||||
61
arch/powerpc/boot/dts/b4860qds.dts
Normal file
61
arch/powerpc/boot/dts/b4860qds.dts
Normal file
@ -0,0 +1,61 @@
|
||||
/*
|
||||
* B4860DS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "fsl/b4860si-pre.dtsi"
|
||||
/include/ "b4qds.dts"
|
||||
|
||||
/ {
|
||||
model = "fsl,B4860QDS";
|
||||
compatible = "fsl,B4860QDS";
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,b4860qds-fpga", "fsl,fpga-qixis";
|
||||
};
|
||||
};
|
||||
|
||||
rio: rapidio@ffe0c0000 {
|
||||
reg = <0xf 0xfe0c0000 0 0x11000>;
|
||||
|
||||
port1 {
|
||||
ranges = <0 0 0xc 0x20000000 0 0x10000000>;
|
||||
};
|
||||
port2 {
|
||||
ranges = <0 0 0xc 0x30000000 0 0x10000000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "fsl/b4860si-post.dtsi"
|
||||
169
arch/powerpc/boot/dts/b4qds.dts
Normal file
169
arch/powerpc/boot/dts/b4qds.dts
Normal file
@ -0,0 +1,169 @@
|
||||
/*
|
||||
* B4420DS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/ {
|
||||
model = "fsl,B4QDS";
|
||||
compatible = "fsl,B4QDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
2 0 0xf 0xff800000 0x00010000
|
||||
3 0 0xf 0xffdf0000 0x00008000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x2 0x0 0x10000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NAND U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x00100000 0x00100000>;
|
||||
label = "NAND DTB Image";
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
/* 10MB for Linux Kernel Image */
|
||||
reg = <0x00200000 0x00A00000>;
|
||||
label = "NAND Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@c00000 {
|
||||
/* 500MB for Root file System Image */
|
||||
reg = <0x00c00000 0x1F400000>;
|
||||
label = "NAND RFS Image";
|
||||
};
|
||||
};
|
||||
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,b4qds-fpga", "fsl,fpga-qixis";
|
||||
reg = <3 0 0x300>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
ranges = <0x00000000 0xf 0x00000000 0x01052000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25wf040";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
};
|
||||
};
|
||||
|
||||
sdhc@114000 {
|
||||
/*Disabled as there is no sdhc connector on B4420QDS board*/
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
eeprom@50 {
|
||||
compatible = "at24,24c64";
|
||||
reg = <0x50>;
|
||||
};
|
||||
eeprom@51 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x51>;
|
||||
};
|
||||
eeprom@53 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x53>;
|
||||
};
|
||||
eeprom@57 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x57>;
|
||||
};
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
};
|
||||
};
|
||||
|
||||
usb@210000 {
|
||||
dr_mode = "host";
|
||||
phy_type = "ulpi";
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
pci0: pcie@ffe200000 {
|
||||
reg = <0xf 0xfe200000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "fsl/b4si-post.dtsi"
|
||||
98
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
Normal file
98
arch/powerpc/boot/dts/fsl/b4420si-post.dtsi
Normal file
@ -0,0 +1,98 @@
|
||||
/*
|
||||
* B4420 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/include/ "b4si-post.dtsi"
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,b4420-pcie", "fsl,qoriq-pcie-v2.4";
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,b4420-dcsr-epu", "fsl,dcsr-epu";
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,b4420-dcsr-cnpc", "fsl,dcsr-cnpc";
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,b4420-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,b4420-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,b4420-dcsr-nal", "fsl,dcsr-nal";
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,b4420-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
};
|
||||
dcsr-snpc@30000 {
|
||||
compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
};
|
||||
dcsr-snpc@31000 {
|
||||
compatible = "fsl,b4420-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
};
|
||||
dcsr-cpu-sb-proxy@108000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x108000 0x1000 0x109000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,b4420-l3-cache-controller", "cache";
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,b4420-corenet-cf";
|
||||
};
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,b4420-device-config", "fsl,qoriq-device-config-2.0";
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4420-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,b4420-rcpm", "fsl,qoriq-rcpm-2.0";
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,b4420-l2-cache-controller";
|
||||
};
|
||||
};
|
||||
73
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
Normal file
73
arch/powerpc/boot/dts/fsl/b4420si-pre.dtsi
Normal file
@ -0,0 +1,73 @@
|
||||
/*
|
||||
* B4420 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "fsl,B4420";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
};
|
||||
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
142
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
Normal file
142
arch/powerpc/boot/dts/fsl/b4860si-post.dtsi
Normal file
@ -0,0 +1,142 @@
|
||||
/*
|
||||
* B4860 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "b4si-post.dtsi"
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,b4860-pcie", "fsl,qoriq-pcie-v2.4";
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <16 2 1 11>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
fsl,liodn-reg = <&guts 0x510>; /* RIO1LIODNR */
|
||||
};
|
||||
|
||||
port2 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <2>;
|
||||
fsl,liodn-reg = <&guts 0x514>; /* RIO2LIODNR */
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,b4860-dcsr-epu", "fsl,dcsr-epu";
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,b4860-dcsr-cnpc", "fsl,dcsr-cnpc";
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,b4860-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,b4860-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
};
|
||||
dcsr-ddr@13000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr2>;
|
||||
reg = <0x13000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,b4860-dcsr-nal", "fsl,dcsr-nal";
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,b4860-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
};
|
||||
dcsr-snpc@30000 {
|
||||
compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
};
|
||||
dcsr-snpc@31000 {
|
||||
compatible = "fsl,b4860-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
};
|
||||
dcsr-cpu-sb-proxy@108000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x108000 0x1000 0x109000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@110000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu2>;
|
||||
reg = <0x110000 0x1000 0x111000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@118000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu3>;
|
||||
reg = <0x118000 0x1000 0x119000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 9>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,b4860-l3-cache-controller", "cache";
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,b4860-corenet-cf";
|
||||
};
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,b4860-device-config", "fsl,qoriq-device-config-2.0";
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4860-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,b4860-rcpm", "fsl,qoriq-rcpm-2.0";
|
||||
};
|
||||
|
||||
L2: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,b4860-l2-cache-controller";
|
||||
};
|
||||
};
|
||||
83
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
Normal file
83
arch/powerpc/boot/dts/fsl/b4860si-pre.dtsi
Normal file
@ -0,0 +1,83 @@
|
||||
/*
|
||||
* B4860 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/ {
|
||||
compatible = "fsl,B4860";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
pci0 = &pci0;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
};
|
||||
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
cpu2: PowerPC,e6500@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4 5>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
cpu3: PowerPC,e6500@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6 7>;
|
||||
next-level-cache = <&L2>;
|
||||
};
|
||||
};
|
||||
};
|
||||
268
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
Normal file
268
arch/powerpc/boot/dts/fsl/b4si-post.dtsi
Normal file
@ -0,0 +1,268 @@
|
||||
/*
|
||||
* B4420 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor, Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* This software is provided by Freescale Semiconductor "as is" and any
|
||||
* express or implied warranties, including, but not limited to, the implied
|
||||
* warranties of merchantability and fitness for a particular purpose are
|
||||
* disclaimed. In no event shall Freescale Semiconductor be liable for any
|
||||
* direct, indirect, incidental, special, exemplary, or consequential damages
|
||||
* (including, but not limited to, procurement of substitute goods or services;
|
||||
* loss of use, data, or profits; or business interruption) however caused and
|
||||
* on any theory of liability, whether in contract, strict liability, or tort
|
||||
* (including negligence or otherwise) arising in any way out of the use of
|
||||
* this software, even if advised of the possibility of such damage.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x200000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,b4-pcie", "fsl,qoriq-pcie-v2.4";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
interrupts = <20 2 0 0>;
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
pcie@0 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
reg = <0 0 0 0 0>;
|
||||
interrupts = <20 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,b4-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0
|
||||
94 2 0 0
|
||||
95 2 0 0>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,b4-dcsr-cnpc", "fsl,dcsr-cnpc";
|
||||
reg = <0x1000 0x1000 0x1002000 0x10000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0x1A000 0x1000>;
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,b4-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,b4-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,b4-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,b4-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-snpc@30000 {
|
||||
compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
reg = <0x30000 0x1000 0x1022000 0x10000>;
|
||||
};
|
||||
dcsr-snpc@31000 {
|
||||
compatible = "fsl,b4-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
reg = <0x31000 0x1000 0x1042000 0x10000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@100000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x100000 0x1000 0x101000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 2>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.5", "fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 8>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,b4-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000>;
|
||||
interrupts = <16 2 1 4>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,b4-corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 0>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x4000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 1>;
|
||||
|
||||
|
||||
/* PCIe, DMA, SRIO */
|
||||
pamu0: pamu@0 {
|
||||
reg = <0 0x1000>;
|
||||
fsl,primary-cache-geometry = <8 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
|
||||
/* AXI2, Maple */
|
||||
pamu1: pamu@1000 {
|
||||
reg = <0x1000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
|
||||
/* Q/BMan */
|
||||
pamu2: pamu@2000 {
|
||||
reg = <0x2000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
|
||||
/* AXI1, FMAN */
|
||||
pamu3: pamu@3000 {
|
||||
reg = <0x3000 0x1000>;
|
||||
fsl,primary-cache-geometry = <32 1>;
|
||||
fsl,secondary-cache-geometry = <32 2>;
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "qoriq-mpic.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,b4-device-config";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,b4-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,b4-rcpm", "fsl,qoriq-rcpm-2.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-0.dtsi"
|
||||
dma@100300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x580>; /* DMA1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-1.dtsi"
|
||||
dma@101300 {
|
||||
fsl,iommu-parent = <&pamu0>;
|
||||
fsl,liodn-reg = <&guts 0x584>; /* DMA2LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qonverge-usb2-dr-0.dtsi"
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x520>; /* USB1LIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-espi-0.dtsi"
|
||||
spi@110000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-esdhc-0.dtsi"
|
||||
sdhc@114000 {
|
||||
sdhci,auto-cmd12;
|
||||
fsl,iommu-parent = <&pamu1>;
|
||||
fsl,liodn-reg = <&guts 0x530>; /* eSDHCLIODNR */
|
||||
};
|
||||
|
||||
/include/ "qoriq-i2c-0.dtsi"
|
||||
/include/ "qoriq-i2c-1.dtsi"
|
||||
/include/ "qoriq-duart-0.dtsi"
|
||||
/include/ "qoriq-duart-1.dtsi"
|
||||
/include/ "qoriq-sec5.3-0.dtsi"
|
||||
|
||||
L2: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,b4-l2-cache-controller";
|
||||
reg = <0xc20000 0x1000>;
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
@ -53,6 +53,7 @@
|
||||
power-isa-mmc; // Memory Coherence
|
||||
power-isa-scpm; // Store Conditional Page Mobility
|
||||
power-isa-wt; // Wait
|
||||
fsl,eref-deo; // Data Cache Extended Operations
|
||||
mmu-type = "power-embedded";
|
||||
};
|
||||
};
|
||||
|
||||
@ -54,6 +54,7 @@
|
||||
power-isa-scpm; // Store Conditional Page Mobility
|
||||
power-isa-wt; // Wait
|
||||
power-isa-64; // 64-bit
|
||||
fsl,eref-deo; // Data Cache Extended Operations
|
||||
mmu-type = "power-embedded";
|
||||
};
|
||||
};
|
||||
|
||||
65
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
Normal file
65
arch/powerpc/boot/dts/fsl/e6500_power_isa.dtsi
Normal file
@ -0,0 +1,65 @@
|
||||
/*
|
||||
* e6500 Power ISA Device Tree Source (include)
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor "AS IS" AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/ {
|
||||
cpus {
|
||||
power-isa-version = "2.06";
|
||||
power-isa-b; // Base
|
||||
power-isa-e; // Embedded
|
||||
power-isa-atb; // Alternate Time Base
|
||||
power-isa-cs; // Cache Specification
|
||||
power-isa-ds; // Decorated Storage
|
||||
power-isa-e.ed; // Embedded.Enhanced Debug
|
||||
power-isa-e.pd; // Embedded.External PID
|
||||
power-isa-e.hv; // Embedded.Hypervisor
|
||||
power-isa-e.le; // Embedded.Little-Endian
|
||||
power-isa-e.pm; // Embedded.Performance Monitor
|
||||
power-isa-e.pc; // Embedded.Processor Control
|
||||
power-isa-ecl; // Embedded Cache Locking
|
||||
power-isa-exp; // External Proxy
|
||||
power-isa-fp; // Floating Point
|
||||
power-isa-fp.r; // Floating Point.Record
|
||||
power-isa-mmc; // Memory Coherence
|
||||
power-isa-scpm; // Store Conditional Page Mobility
|
||||
power-isa-wt; // Wait
|
||||
power-isa-64; // 64-bit
|
||||
power-isa-e.pt; // Embedded.Page Table
|
||||
power-isa-e.hv.lrat; // Embedded.Hypervisor.LRAT
|
||||
power-isa-e.em; // Embedded Multi-Threading
|
||||
power-isa-v; // Vector (AltiVec)
|
||||
fsl,eref-er; // Enhanced Reservations (Load and Reserve and Store Cond.)
|
||||
fsl,eref-deo; // Data Cache Extended Operations
|
||||
mmu-type = "power-embedded";
|
||||
};
|
||||
};
|
||||
@ -148,6 +148,7 @@
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
|
||||
fsl,sec-era = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x30000 0x10000>;
|
||||
|
||||
@ -155,7 +155,7 @@
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,dcsr-epu";
|
||||
compatible = "fsl,p2041-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
|
||||
@ -182,7 +182,7 @@
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,dcsr-epu";
|
||||
compatible = "fsl,p3041-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
|
||||
@ -156,7 +156,7 @@
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,dcsr-epu";
|
||||
compatible = "fsl,p4080-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
|
||||
@ -184,7 +184,7 @@
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,dcsr-epu";
|
||||
compatible = "fsl,p5020-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
|
||||
@ -129,7 +129,7 @@
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,dcsr-epu";
|
||||
compatible = "fsl,p5040-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0>;
|
||||
|
||||
@ -34,6 +34,7 @@
|
||||
|
||||
crypto@30000 {
|
||||
compatible = "fsl,sec-v4.4", "fsl,sec-v4.0";
|
||||
fsl,sec-era = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
ranges = <0x0 0x30000 0x10000>;
|
||||
|
||||
41
arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi
Normal file
41
arch/powerpc/boot/dts/fsl/qonverge-usb2-dr-0.dtsi
Normal file
@ -0,0 +1,41 @@
|
||||
/*
|
||||
* QorIQ Qonverge USB Host device tree stub [ controller @ offset 0x210000 ]
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
usb@210000 {
|
||||
compatible = "fsl-usb2-dr";
|
||||
reg = <0x210000 0x1000>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
interrupts = <44 0x2 0 0>;
|
||||
};
|
||||
41
arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi
Normal file
41
arch/powerpc/boot/dts/fsl/qoriq-gpio-1.dtsi
Normal file
@ -0,0 +1,41 @@
|
||||
/*
|
||||
* QorIQ GPIO device tree stub [ controller @ offset 0x131000 ]
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
gpio1: gpio@131000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x131000 0x1000>;
|
||||
interrupts = <54 2 0 0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
41
arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi
Normal file
41
arch/powerpc/boot/dts/fsl/qoriq-gpio-2.dtsi
Normal file
@ -0,0 +1,41 @@
|
||||
/*
|
||||
* QorIQ GPIO device tree stub [ controller @ offset 0x132000 ]
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
gpio2: gpio@132000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x132000 0x1000>;
|
||||
interrupts = <86 2 0 0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
41
arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi
Normal file
41
arch/powerpc/boot/dts/fsl/qoriq-gpio-3.dtsi
Normal file
@ -0,0 +1,41 @@
|
||||
/*
|
||||
* QorIQ GPIO device tree stub [ controller @ offset 0x133000 ]
|
||||
*
|
||||
* Copyright 2013 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
gpio3: gpio@133000 {
|
||||
compatible = "fsl,qoriq-gpio";
|
||||
reg = <0x133000 0x1000>;
|
||||
interrupts = <87 2 0 0>;
|
||||
#gpio-cells = <2>;
|
||||
gpio-controller;
|
||||
};
|
||||
@ -34,6 +34,7 @@
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.0";
|
||||
fsl,sec-era = <1>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
|
||||
@ -34,6 +34,7 @@
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.2", "fsl,sec-v4.0";
|
||||
fsl,sec-era = <3>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
|
||||
@ -1,7 +1,7 @@
|
||||
/*
|
||||
* QorIQ Sec/Crypto 4.1 device tree stub [ controller @ offset 0x300000 ]
|
||||
* QorIQ Sec/Crypto 5.0 device tree stub [ controller @ offset 0x300000 ]
|
||||
*
|
||||
* Copyright 2011 Freescale Semiconductor Inc.
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
@ -33,7 +33,8 @@
|
||||
*/
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v4.1", "fsl,sec-v4.0";
|
||||
compatible = "fsl,sec-v5.0", "fsl,sec-v4.0";
|
||||
fsl,sec-era = <5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
@ -41,35 +42,35 @@ crypto: crypto@300000 {
|
||||
interrupts = <92 2 0 0>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v4.1-job-ring",
|
||||
compatible = "fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <88 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v4.1-job-ring",
|
||||
compatible = "fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <89 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v4.1-job-ring",
|
||||
compatible = "fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <90 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
compatible = "fsl,sec-v4.1-job-ring",
|
||||
compatible = "fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupts = <91 2 0 0>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v4.1-rtic",
|
||||
compatible = "fsl,sec-v5.0-rtic",
|
||||
"fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
@ -77,25 +78,25 @@ crypto: crypto@300000 {
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
|
||||
rtic_a: rtic-a@0 {
|
||||
compatible = "fsl,sec-v4.1-rtic-memory",
|
||||
compatible = "fsl,sec-v5.0-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x80>;
|
||||
};
|
||||
|
||||
rtic_b: rtic-b@20 {
|
||||
compatible = "fsl,sec-v4.1-rtic-memory",
|
||||
compatible = "fsl,sec-v5.0-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20 0x200 0x80>;
|
||||
};
|
||||
|
||||
rtic_c: rtic-c@40 {
|
||||
compatible = "fsl,sec-v4.1-rtic-memory",
|
||||
compatible = "fsl,sec-v5.0-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20 0x300 0x80>;
|
||||
};
|
||||
|
||||
rtic_d: rtic-d@60 {
|
||||
compatible = "fsl,sec-v4.1-rtic-memory",
|
||||
compatible = "fsl,sec-v5.0-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20 0x500 0x80>;
|
||||
};
|
||||
@ -103,7 +104,7 @@ crypto: crypto@300000 {
|
||||
};
|
||||
|
||||
sec_mon: sec_mon@314000 {
|
||||
compatible = "fsl,sec-v4.1-mon", "fsl,sec-v4.0-mon";
|
||||
compatible = "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
|
||||
reg = <0x314000 0x1000>;
|
||||
interrupts = <93 2 0 0>;
|
||||
};
|
||||
@ -34,6 +34,7 @@
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v5.2", "fsl,sec-v5.0", "fsl,sec-v4.0";
|
||||
fsl,sec-era = <5>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
|
||||
119
arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi
Normal file
119
arch/powerpc/boot/dts/fsl/qoriq-sec5.3-0.dtsi
Normal file
@ -0,0 +1,119 @@
|
||||
/*
|
||||
* QorIQ Sec/Crypto 5.3 device tree stub [ controller @ offset 0x300000 ]
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
crypto: crypto@300000 {
|
||||
compatible = "fsl,sec-v5.3", "fsl,sec-v5.0", "fsl,sec-v4.0";
|
||||
fsl,sec-era = <4>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x300000 0x10000>;
|
||||
ranges = <0 0x300000 0x10000>;
|
||||
interrupts = <92 2 0 0>;
|
||||
|
||||
sec_jr0: jr@1000 {
|
||||
compatible = "fsl,sec-v5.3-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x1000 0x1000>;
|
||||
interrupts = <88 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr1: jr@2000 {
|
||||
compatible = "fsl,sec-v5.3-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x2000 0x1000>;
|
||||
interrupts = <89 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr2: jr@3000 {
|
||||
compatible = "fsl,sec-v5.3-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x3000 0x1000>;
|
||||
interrupts = <90 2 0 0>;
|
||||
};
|
||||
|
||||
sec_jr3: jr@4000 {
|
||||
compatible = "fsl,sec-v5.3-job-ring",
|
||||
"fsl,sec-v5.0-job-ring",
|
||||
"fsl,sec-v4.0-job-ring";
|
||||
reg = <0x4000 0x1000>;
|
||||
interrupts = <91 2 0 0>;
|
||||
};
|
||||
|
||||
rtic@6000 {
|
||||
compatible = "fsl,sec-v5.3-rtic",
|
||||
"fsl,sec-v5.0-rtic",
|
||||
"fsl,sec-v4.0-rtic";
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
reg = <0x6000 0x100>;
|
||||
ranges = <0x0 0x6100 0xe00>;
|
||||
|
||||
rtic_a: rtic-a@0 {
|
||||
compatible = "fsl,sec-v5.3-rtic-memory",
|
||||
"fsl,sec-v5.0-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x00 0x20 0x100 0x80>;
|
||||
};
|
||||
|
||||
rtic_b: rtic-b@20 {
|
||||
compatible = "fsl,sec-v5.3-rtic-memory",
|
||||
"fsl,sec-v5.0-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x20 0x20 0x200 0x80>;
|
||||
};
|
||||
|
||||
rtic_c: rtic-c@40 {
|
||||
compatible = "fsl,sec-v5.3-rtic-memory",
|
||||
"fsl,sec-v5.0-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x40 0x20 0x300 0x80>;
|
||||
};
|
||||
|
||||
rtic_d: rtic-d@60 {
|
||||
compatible = "fsl,sec-v5.3-rtic-memory",
|
||||
"fsl,sec-v5.0-rtic-memory",
|
||||
"fsl,sec-v4.0-rtic-memory";
|
||||
reg = <0x60 0x20 0x500 0x80>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
sec_mon: sec_mon@314000 {
|
||||
compatible = "fsl,sec-v5.3-mon", "fsl,sec-v5.0-mon", "fsl,sec-v4.0-mon";
|
||||
reg = <0x314000 0x1000>;
|
||||
interrupts = <93 2 0 0>;
|
||||
};
|
||||
442
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
Normal file
442
arch/powerpc/boot/dts/fsl/t4240si-post.dtsi
Normal file
@ -0,0 +1,442 @@
|
||||
/*
|
||||
* T4240 Silicon/SoC Device Tree Source (post include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
&ifc {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc", "simple-bus";
|
||||
interrupts = <25 2 0 0>;
|
||||
};
|
||||
|
||||
/* controller at 0x240000 */
|
||||
&pci0 {
|
||||
compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
interrupts = <20 2 0 0>;
|
||||
pcie@0 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
reg = <0 0 0 0 0>;
|
||||
interrupts = <20 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 40 1 0 0
|
||||
0000 0 0 2 &mpic 1 1 0 0
|
||||
0000 0 0 3 &mpic 2 1 0 0
|
||||
0000 0 0 4 &mpic 3 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x250000 */
|
||||
&pci1 {
|
||||
compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0 0xff>;
|
||||
interrupts = <21 2 0 0>;
|
||||
pcie@0 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
reg = <0 0 0 0 0>;
|
||||
interrupts = <21 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 41 1 0 0
|
||||
0000 0 0 2 &mpic 5 1 0 0
|
||||
0000 0 0 3 &mpic 6 1 0 0
|
||||
0000 0 0 4 &mpic 7 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x260000 */
|
||||
&pci2 {
|
||||
compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
interrupts = <22 2 0 0>;
|
||||
pcie@0 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
reg = <0 0 0 0 0>;
|
||||
interrupts = <22 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 42 1 0 0
|
||||
0000 0 0 2 &mpic 9 1 0 0
|
||||
0000 0 0 3 &mpic 10 1 0 0
|
||||
0000 0 0 4 &mpic 11 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
/* controller at 0x270000 */
|
||||
&pci3 {
|
||||
compatible = "fsl,t4240-pcie", "fsl,qoriq-pcie-v3.0";
|
||||
device_type = "pci";
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
bus-range = <0x0 0xff>;
|
||||
interrupts = <23 2 0 0>;
|
||||
pcie@0 {
|
||||
#interrupt-cells = <1>;
|
||||
#size-cells = <2>;
|
||||
#address-cells = <3>;
|
||||
device_type = "pci";
|
||||
reg = <0 0 0 0 0>;
|
||||
interrupts = <23 2 0 0>;
|
||||
interrupt-map-mask = <0xf800 0 0 7>;
|
||||
interrupt-map = <
|
||||
/* IDSEL 0x0 */
|
||||
0000 0 0 1 &mpic 43 1 0 0
|
||||
0000 0 0 2 &mpic 0 1 0 0
|
||||
0000 0 0 3 &mpic 4 1 0 0
|
||||
0000 0 0 4 &mpic 8 1 0 0
|
||||
>;
|
||||
};
|
||||
};
|
||||
|
||||
&rio {
|
||||
compatible = "fsl,srio";
|
||||
interrupts = <16 2 1 11>;
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
ranges;
|
||||
|
||||
port1 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <1>;
|
||||
};
|
||||
|
||||
port2 {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
cell-index = <2>;
|
||||
};
|
||||
};
|
||||
|
||||
&dcsr {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,dcsr", "simple-bus";
|
||||
|
||||
dcsr-epu@0 {
|
||||
compatible = "fsl,t4240-dcsr-epu", "fsl,dcsr-epu";
|
||||
interrupts = <52 2 0 0
|
||||
84 2 0 0
|
||||
85 2 0 0
|
||||
94 2 0 0
|
||||
95 2 0 0>;
|
||||
reg = <0x0 0x1000>;
|
||||
};
|
||||
dcsr-npc {
|
||||
compatible = "fsl,t4240-dcsr-cnpc", "fsl,dcsr-cnpc";
|
||||
reg = <0x1000 0x1000 0x1002000 0x10000>;
|
||||
};
|
||||
dcsr-nxc@2000 {
|
||||
compatible = "fsl,dcsr-nxc";
|
||||
reg = <0x2000 0x1000>;
|
||||
};
|
||||
dcsr-corenet {
|
||||
compatible = "fsl,dcsr-corenet";
|
||||
reg = <0x8000 0x1000 0x1A000 0x1000>;
|
||||
};
|
||||
dcsr-dpaa@9000 {
|
||||
compatible = "fsl,t4240-dcsr-dpaa", "fsl,dcsr-dpaa";
|
||||
reg = <0x9000 0x1000>;
|
||||
};
|
||||
dcsr-ocn@11000 {
|
||||
compatible = "fsl,t4240-dcsr-ocn", "fsl,dcsr-ocn";
|
||||
reg = <0x11000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@12000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr1>;
|
||||
reg = <0x12000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@13000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr2>;
|
||||
reg = <0x13000 0x1000>;
|
||||
};
|
||||
dcsr-ddr@14000 {
|
||||
compatible = "fsl,dcsr-ddr";
|
||||
dev-handle = <&ddr3>;
|
||||
reg = <0x14000 0x1000>;
|
||||
};
|
||||
dcsr-nal@18000 {
|
||||
compatible = "fsl,t4240-dcsr-nal", "fsl,dcsr-nal";
|
||||
reg = <0x18000 0x1000>;
|
||||
};
|
||||
dcsr-rcpm@22000 {
|
||||
compatible = "fsl,t4240-dcsr-rcpm", "fsl,dcsr-rcpm";
|
||||
reg = <0x22000 0x1000>;
|
||||
};
|
||||
dcsr-snpc@30000 {
|
||||
compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
reg = <0x30000 0x1000 0x1022000 0x10000>;
|
||||
};
|
||||
dcsr-snpc@31000 {
|
||||
compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
reg = <0x31000 0x1000 0x1042000 0x10000>;
|
||||
};
|
||||
dcsr-snpc@32000 {
|
||||
compatible = "fsl,t4240-dcsr-snpc", "fsl,dcsr-snpc";
|
||||
reg = <0x32000 0x1000 0x1062000 0x10000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@100000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu0>;
|
||||
reg = <0x100000 0x1000 0x101000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@108000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu1>;
|
||||
reg = <0x108000 0x1000 0x109000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@110000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu2>;
|
||||
reg = <0x110000 0x1000 0x111000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@118000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu3>;
|
||||
reg = <0x118000 0x1000 0x119000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@120000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu4>;
|
||||
reg = <0x120000 0x1000 0x121000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@128000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu5>;
|
||||
reg = <0x128000 0x1000 0x129000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@130000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu6>;
|
||||
reg = <0x130000 0x1000 0x131000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@138000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu7>;
|
||||
reg = <0x138000 0x1000 0x139000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@140000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu8>;
|
||||
reg = <0x140000 0x1000 0x141000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@148000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu9>;
|
||||
reg = <0x148000 0x1000 0x149000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@150000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu10>;
|
||||
reg = <0x150000 0x1000 0x151000 0x1000>;
|
||||
};
|
||||
dcsr-cpu-sb-proxy@158000 {
|
||||
compatible = "fsl,dcsr-e6500-sb-proxy", "fsl,dcsr-cpu-sb-proxy";
|
||||
cpu-handle = <&cpu11>;
|
||||
reg = <0x158000 0x1000 0x159000 0x1000>;
|
||||
};
|
||||
};
|
||||
|
||||
&soc {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
device_type = "soc";
|
||||
compatible = "simple-bus";
|
||||
|
||||
soc-sram-error {
|
||||
compatible = "fsl,soc-sram-error";
|
||||
interrupts = <16 2 1 29>;
|
||||
};
|
||||
|
||||
corenet-law@0 {
|
||||
compatible = "fsl,corenet-law";
|
||||
reg = <0x0 0x1000>;
|
||||
fsl,num-laws = <32>;
|
||||
};
|
||||
|
||||
ddr1: memory-controller@8000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.7",
|
||||
"fsl,qoriq-memory-controller";
|
||||
reg = <0x8000 0x1000>;
|
||||
interrupts = <16 2 1 23>;
|
||||
};
|
||||
|
||||
ddr2: memory-controller@9000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.7",
|
||||
"fsl,qoriq-memory-controller";
|
||||
reg = <0x9000 0x1000>;
|
||||
interrupts = <16 2 1 22>;
|
||||
};
|
||||
|
||||
ddr3: memory-controller@a000 {
|
||||
compatible = "fsl,qoriq-memory-controller-v4.7",
|
||||
"fsl,qoriq-memory-controller";
|
||||
reg = <0xa000 0x1000>;
|
||||
interrupts = <16 2 1 21>;
|
||||
};
|
||||
|
||||
cpc: l3-cache-controller@10000 {
|
||||
compatible = "fsl,t4240-l3-cache-controller", "cache";
|
||||
reg = <0x10000 0x1000
|
||||
0x11000 0x1000
|
||||
0x12000 0x1000>;
|
||||
interrupts = <16 2 1 27
|
||||
16 2 1 26
|
||||
16 2 1 25>;
|
||||
};
|
||||
|
||||
corenet-cf@18000 {
|
||||
compatible = "fsl,corenet-cf";
|
||||
reg = <0x18000 0x1000>;
|
||||
interrupts = <16 2 1 31>;
|
||||
fsl,ccf-num-csdids = <32>;
|
||||
fsl,ccf-num-snoopids = <32>;
|
||||
};
|
||||
|
||||
iommu@20000 {
|
||||
compatible = "fsl,pamu-v1.0", "fsl,pamu";
|
||||
reg = <0x20000 0x6000>;
|
||||
interrupts = <
|
||||
24 2 0 0
|
||||
16 2 1 30>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-mpic.dtsi"
|
||||
|
||||
guts: global-utilities@e0000 {
|
||||
compatible = "fsl,t4240-device-config", "fsl,qoriq-device-config-2.0";
|
||||
reg = <0xe0000 0xe00>;
|
||||
fsl,has-rstcr;
|
||||
fsl,liodn-bits = <12>;
|
||||
};
|
||||
|
||||
clockgen: global-utilities@e1000 {
|
||||
compatible = "fsl,t4240-clockgen", "fsl,qoriq-clockgen-2.0";
|
||||
reg = <0xe1000 0x1000>;
|
||||
};
|
||||
|
||||
rcpm: global-utilities@e2000 {
|
||||
compatible = "fsl,t4240-rcpm", "fsl,qoriq-rcpm-2.0";
|
||||
reg = <0xe2000 0x1000>;
|
||||
};
|
||||
|
||||
sfp: sfp@e8000 {
|
||||
compatible = "fsl,t4240-sfp";
|
||||
reg = <0xe8000 0x1000>;
|
||||
};
|
||||
|
||||
serdes: serdes@ea000 {
|
||||
compatible = "fsl,t4240-serdes";
|
||||
reg = <0xea000 0x4000>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-dma-0.dtsi"
|
||||
/include/ "qoriq-dma-1.dtsi"
|
||||
|
||||
/include/ "qoriq-espi-0.dtsi"
|
||||
spi@110000 {
|
||||
fsl,espi-num-chipselects = <4>;
|
||||
};
|
||||
|
||||
/include/ "qoriq-esdhc-0.dtsi"
|
||||
sdhc@114000 {
|
||||
compatible = "fsl,t4240-esdhc", "fsl,esdhc";
|
||||
sdhci,auto-cmd12;
|
||||
};
|
||||
/include/ "qoriq-i2c-0.dtsi"
|
||||
/include/ "qoriq-i2c-1.dtsi"
|
||||
/include/ "qoriq-duart-0.dtsi"
|
||||
/include/ "qoriq-duart-1.dtsi"
|
||||
/include/ "qoriq-gpio-0.dtsi"
|
||||
/include/ "qoriq-gpio-1.dtsi"
|
||||
/include/ "qoriq-gpio-2.dtsi"
|
||||
/include/ "qoriq-gpio-3.dtsi"
|
||||
/include/ "qoriq-usb2-mph-0.dtsi"
|
||||
usb0: usb@210000 {
|
||||
compatible = "fsl-usb2-mph-v2.4", "fsl-usb2-mph";
|
||||
phy_type = "utmi";
|
||||
port0;
|
||||
};
|
||||
/include/ "qoriq-usb2-dr-0.dtsi"
|
||||
usb1: usb@211000 {
|
||||
compatible = "fsl-usb2-dr-v2.4", "fsl-usb2-dr";
|
||||
dr_mode = "host";
|
||||
phy_type = "utmi";
|
||||
};
|
||||
/include/ "qoriq-sata2-0.dtsi"
|
||||
/include/ "qoriq-sata2-1.dtsi"
|
||||
/include/ "qoriq-sec5.0-0.dtsi"
|
||||
|
||||
L2_1: l2-cache-controller@c20000 {
|
||||
compatible = "fsl,t4240-l2-cache-controller";
|
||||
reg = <0xc20000 0x40000>;
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
L2_2: l2-cache-controller@c60000 {
|
||||
compatible = "fsl,t4240-l2-cache-controller";
|
||||
reg = <0xc60000 0x40000>;
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
L2_3: l2-cache-controller@ca0000 {
|
||||
compatible = "fsl,t4240-l2-cache-controller";
|
||||
reg = <0xca0000 0x40000>;
|
||||
next-level-cache = <&cpc>;
|
||||
};
|
||||
};
|
||||
128
arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
Normal file
128
arch/powerpc/boot/dts/fsl/t4240si-pre.dtsi
Normal file
@ -0,0 +1,128 @@
|
||||
/*
|
||||
* T4240 Silicon/SoC Device Tree Source (pre include)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/dts-v1/;
|
||||
|
||||
/include/ "e6500_power_isa.dtsi"
|
||||
|
||||
/ {
|
||||
compatible = "fsl,T4240";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
aliases {
|
||||
ccsr = &soc;
|
||||
dcsr = &dcsr;
|
||||
|
||||
serial0 = &serial0;
|
||||
serial1 = &serial1;
|
||||
serial2 = &serial2;
|
||||
serial3 = &serial3;
|
||||
crypto = &crypto;
|
||||
pci0 = &pci0;
|
||||
pci1 = &pci1;
|
||||
pci2 = &pci2;
|
||||
pci3 = &pci3;
|
||||
dma0 = &dma0;
|
||||
dma1 = &dma1;
|
||||
sdhc = &sdhc;
|
||||
};
|
||||
|
||||
cpus {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
|
||||
cpu0: PowerPC,e6500@0 {
|
||||
device_type = "cpu";
|
||||
reg = <0 1>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
cpu1: PowerPC,e6500@2 {
|
||||
device_type = "cpu";
|
||||
reg = <2 3>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
cpu2: PowerPC,e6500@4 {
|
||||
device_type = "cpu";
|
||||
reg = <4 5>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
cpu3: PowerPC,e6500@6 {
|
||||
device_type = "cpu";
|
||||
reg = <6 7>;
|
||||
next-level-cache = <&L2_1>;
|
||||
};
|
||||
cpu4: PowerPC,e6500@8 {
|
||||
device_type = "cpu";
|
||||
reg = <8 9>;
|
||||
next-level-cache = <&L2_2>;
|
||||
};
|
||||
cpu5: PowerPC,e6500@10 {
|
||||
device_type = "cpu";
|
||||
reg = <10 11>;
|
||||
next-level-cache = <&L2_2>;
|
||||
};
|
||||
cpu6: PowerPC,e6500@12 {
|
||||
device_type = "cpu";
|
||||
reg = <12 13>;
|
||||
next-level-cache = <&L2_2>;
|
||||
};
|
||||
cpu7: PowerPC,e6500@14 {
|
||||
device_type = "cpu";
|
||||
reg = <14 15>;
|
||||
next-level-cache = <&L2_2>;
|
||||
};
|
||||
cpu8: PowerPC,e6500@16 {
|
||||
device_type = "cpu";
|
||||
reg = <16 17>;
|
||||
next-level-cache = <&L2_3>;
|
||||
};
|
||||
cpu9: PowerPC,e6500@18 {
|
||||
device_type = "cpu";
|
||||
reg = <18 19>;
|
||||
next-level-cache = <&L2_3>;
|
||||
};
|
||||
cpu10: PowerPC,e6500@20 {
|
||||
device_type = "cpu";
|
||||
reg = <20 21>;
|
||||
next-level-cache = <&L2_3>;
|
||||
};
|
||||
cpu11: PowerPC,e6500@22 {
|
||||
device_type = "cpu";
|
||||
reg = <22 23>;
|
||||
next-level-cache = <&L2_3>;
|
||||
};
|
||||
};
|
||||
};
|
||||
@ -32,7 +32,7 @@
|
||||
reg = <0 0 0 0>; // Filled by U-Boot
|
||||
};
|
||||
|
||||
lbc: localbus@ffe05000 {
|
||||
lbc: localbus@fffe05000 {
|
||||
reg = <0xf 0xffe05000 0 0x1000>;
|
||||
|
||||
ranges = <0x0 0x0 0xf 0xe8000000 0x08000000
|
||||
@ -44,7 +44,7 @@
|
||||
ranges = <0x0 0xf 0xffe00000 0x100000>;
|
||||
};
|
||||
|
||||
pci0: pci@ffe08000 {
|
||||
pci0: pci@fffe08000 {
|
||||
reg = <0xf 0xffe08000 0 0x1000>;
|
||||
ranges = <0x02000000 0 0xf0000000 0xc 0x00000000 0 0x10000000
|
||||
0x01000000 0 0x00000000 0xf 0xffc00000 0 0x00010000>;
|
||||
@ -59,7 +59,7 @@
|
||||
0x8800 0 0 4 &mpic 4 1 0 0>;
|
||||
};
|
||||
|
||||
pci1: pcie@ffe09000 {
|
||||
pci1: pcie@fffe09000 {
|
||||
reg = <0xf 0xffe09000 0 0x1000>;
|
||||
ranges = <0x02000000 0 0xf8000000 0xc 0x18000000 0 0x08000000
|
||||
0x01000000 0 0x00000000 0xf 0xffc20000 0 0x00010000>;
|
||||
|
||||
@ -62,11 +62,19 @@
|
||||
};
|
||||
|
||||
partition@400000 {
|
||||
/* 11MB for JFFS2 based Root file System */
|
||||
reg = <0x00400000 0x00b00000>;
|
||||
/* 10.75MB for JFFS2 based Root file System */
|
||||
reg = <0x00400000 0x00ac0000>;
|
||||
label = "NOR JFFS2 Root File System";
|
||||
};
|
||||
|
||||
partition@ec0000 {
|
||||
/* This location must not be altered */
|
||||
/* 256KB for QE ucode firmware*/
|
||||
reg = <0x00ec0000 0x00040000>;
|
||||
label = "NOR QE microcode firmware";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@f00000 {
|
||||
/* This location must not be altered */
|
||||
/* 512KB for u-boot Bootloader Image */
|
||||
|
||||
@ -82,6 +82,11 @@
|
||||
0x0 0x100000>;
|
||||
};
|
||||
};
|
||||
|
||||
qe: qe@fffe80000 {
|
||||
status = "disabled"; /* no firmware loaded */
|
||||
};
|
||||
|
||||
};
|
||||
|
||||
/include/ "p1025rdb.dtsi"
|
||||
|
||||
224
arch/powerpc/boot/dts/t4240qds.dts
Normal file
224
arch/powerpc/boot/dts/t4240qds.dts
Normal file
@ -0,0 +1,224 @@
|
||||
/*
|
||||
* T4240QDS Device Tree Source
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* Redistribution and use in source and binary forms, with or without
|
||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of Freescale Semiconductor nor the
|
||||
* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
|
||||
*
|
||||
* ALTERNATIVELY, this software may be distributed under the terms of the
|
||||
* GNU General Public License ("GPL") as published by the Free Software
|
||||
* Foundation, either version 2 of that License or (at your option) any
|
||||
* later version.
|
||||
*
|
||||
* THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
|
||||
* EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
|
||||
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
|
||||
* DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
||||
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
*/
|
||||
|
||||
/include/ "fsl/t4240si-pre.dtsi"
|
||||
|
||||
/ {
|
||||
model = "fsl,T4240QDS";
|
||||
compatible = "fsl,T4240QDS";
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
interrupt-parent = <&mpic>;
|
||||
|
||||
ifc: localbus@ffe124000 {
|
||||
reg = <0xf 0xfe124000 0 0x2000>;
|
||||
ranges = <0 0 0xf 0xe8000000 0x08000000
|
||||
2 0 0xf 0xff800000 0x00010000
|
||||
3 0 0xf 0xffdf0000 0x00008000>;
|
||||
|
||||
nor@0,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "cfi-flash";
|
||||
reg = <0x0 0x0 0x8000000>;
|
||||
|
||||
bank-width = <2>;
|
||||
device-width = <1>;
|
||||
};
|
||||
|
||||
nand@2,0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "fsl,ifc-nand";
|
||||
reg = <0x2 0x0 0x10000>;
|
||||
|
||||
partition@0 {
|
||||
/* This location must not be altered */
|
||||
/* 1MB for u-boot Bootloader Image */
|
||||
reg = <0x0 0x00100000>;
|
||||
label = "NAND U-Boot Image";
|
||||
read-only;
|
||||
};
|
||||
|
||||
partition@100000 {
|
||||
/* 1MB for DTB Image */
|
||||
reg = <0x00100000 0x00100000>;
|
||||
label = "NAND DTB Image";
|
||||
};
|
||||
|
||||
partition@200000 {
|
||||
/* 10MB for Linux Kernel Image */
|
||||
reg = <0x00200000 0x00A00000>;
|
||||
label = "NAND Linux Kernel Image";
|
||||
};
|
||||
|
||||
partition@C00000 {
|
||||
/* 500MB for Root file System Image */
|
||||
reg = <0x00c00000 0x1F400000>;
|
||||
label = "NAND RFS Image";
|
||||
};
|
||||
};
|
||||
|
||||
board-control@3,0 {
|
||||
compatible = "fsl,t4240qds-fpga", "fsl,fpga-qixis";
|
||||
reg = <3 0 0x300>;
|
||||
};
|
||||
};
|
||||
|
||||
memory {
|
||||
device_type = "memory";
|
||||
};
|
||||
|
||||
dcsr: dcsr@f00000000 {
|
||||
ranges = <0x00000000 0xf 0x00000000 0x01072000>;
|
||||
};
|
||||
|
||||
soc: soc@ffe000000 {
|
||||
ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
|
||||
reg = <0xf 0xfe000000 0 0x00001000>;
|
||||
spi@110000 {
|
||||
flash@0 {
|
||||
#address-cells = <1>;
|
||||
#size-cells = <1>;
|
||||
compatible = "sst,sst25wf040";
|
||||
reg = <0>;
|
||||
spi-max-frequency = <40000000>; /* input clock */
|
||||
};
|
||||
};
|
||||
|
||||
i2c@118000 {
|
||||
eeprom@51 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x51>;
|
||||
};
|
||||
eeprom@52 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x52>;
|
||||
};
|
||||
eeprom@53 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x53>;
|
||||
};
|
||||
eeprom@54 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x54>;
|
||||
};
|
||||
eeprom@55 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x55>;
|
||||
};
|
||||
eeprom@56 {
|
||||
compatible = "at24,24c256";
|
||||
reg = <0x56>;
|
||||
};
|
||||
rtc@68 {
|
||||
compatible = "dallas,ds3232";
|
||||
reg = <0x68>;
|
||||
interrupts = <0x1 0x1 0 0>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
pci0: pcie@ffe240000 {
|
||||
reg = <0xf 0xfe240000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci1: pcie@ffe250000 {
|
||||
reg = <0xf 0xfe250000 0 0x10000>;
|
||||
ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000
|
||||
0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci2: pcie@ffe260000 {
|
||||
reg = <0xf 0xfe260000 0 0x1000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
|
||||
pci3: pcie@ffe270000 {
|
||||
reg = <0xf 0xfe270000 0 0x10000>;
|
||||
ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000
|
||||
0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>;
|
||||
pcie@0 {
|
||||
ranges = <0x02000000 0 0xe0000000
|
||||
0x02000000 0 0xe0000000
|
||||
0 0x20000000
|
||||
|
||||
0x01000000 0 0x00000000
|
||||
0x01000000 0 0x00000000
|
||||
0 0x00010000>;
|
||||
};
|
||||
};
|
||||
rio: rapidio@ffe0c0000 {
|
||||
reg = <0xf 0xfe0c0000 0 0x11000>;
|
||||
|
||||
port1 {
|
||||
ranges = <0 0 0xc 0x20000000 0 0x10000000>;
|
||||
};
|
||||
port2 {
|
||||
ranges = <0 0 0xc 0x30000000 0 0x10000000>;
|
||||
};
|
||||
};
|
||||
};
|
||||
|
||||
/include/ "fsl/t4240si-post.dtsi"
|
||||
@ -1,14 +1,13 @@
|
||||
CONFIG_PPC64=y
|
||||
CONFIG_PPC_BOOK3E_64=y
|
||||
# CONFIG_VIRT_CPU_ACCOUNTING_NATIVE is not set
|
||||
CONFIG_ALTIVEC=y
|
||||
CONFIG_SMP=y
|
||||
CONFIG_NR_CPUS=2
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_NR_CPUS=24
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_IRQ_DOMAIN_DEBUG=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
@ -22,10 +21,13 @@ CONFIG_MODVERSIONS=y
|
||||
# CONFIG_BLK_DEV_BSG is not set
|
||||
CONFIG_PARTITION_ADVANCED=y
|
||||
CONFIG_MAC_PARTITION=y
|
||||
CONFIG_B4_QDS=y
|
||||
CONFIG_P5020_DS=y
|
||||
CONFIG_P5040_DS=y
|
||||
CONFIG_T4240_QDS=y
|
||||
# CONFIG_PPC_OF_BOOT_TRAMPOLINE is not set
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_FSL_IFC=y
|
||||
CONFIG_PCIEPORTBUS=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_RAPIDIO=y
|
||||
@ -58,16 +60,33 @@ CONFIG_IP_SCTP=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLKDEVS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_FTL=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_GEN_PROBE=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_1=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_2=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_4=y
|
||||
CONFIG_MTD_CFI_I1=y
|
||||
CONFIG_MTD_CFI_I2=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_CFI_UTIL=y
|
||||
CONFIG_MTD_NAND_ECC=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_IDS=y
|
||||
CONFIG_MTD_NAND_FSL_ELBC=y
|
||||
CONFIG_MTD_NAND_FSL_IFC=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MTD_UBI_BEB_RESERVE=1
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_RAM=y
|
||||
@ -78,6 +97,7 @@ CONFIG_SATA_FSL=y
|
||||
CONFIG_SATA_SIL24=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
CONFIG_E1000E=y
|
||||
CONFIG_INPUT_FF_MEMLESS=m
|
||||
# CONFIG_INPUT_MOUSEDEV is not set
|
||||
# CONFIG_INPUT_KEYBOARD is not set
|
||||
@ -121,7 +141,16 @@ CONFIG_NTFS_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_HUGETLBFS=y
|
||||
# CONFIG_MISC_FILESYSTEMS is not set
|
||||
CONFIG_MISC_FILESYSTEMS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_FS_DEBUG=1
|
||||
CONFIG_JFFS2_FS_WRITEBUFFER=y
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
CONFIG_JFFS2_RTIME=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_UBIFS_FS_XATTR=y
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
CONFIG_NFS_FS=y
|
||||
CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
@ -129,6 +158,12 @@ CONFIG_NFSD=m
|
||||
CONFIG_NLS_ISO8859_1=y
|
||||
CONFIG_NLS_UTF8=m
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CRC16=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
CONFIG_CRYPTO_LZO=y
|
||||
CONFIG_FRAME_WARN=1024
|
||||
CONFIG_MAGIC_SYSRQ=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
@ -140,6 +175,5 @@ CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_MD4=y
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA512=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRYPTO_DEV_FSL_CAAM=y
|
||||
|
||||
@ -1,13 +1,12 @@
|
||||
CONFIG_PPC_85xx=y
|
||||
CONFIG_PHYS_64BIT=y
|
||||
CONFIG_EXPERIMENTAL=y
|
||||
CONFIG_SYSVIPC=y
|
||||
CONFIG_POSIX_MQUEUE=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_AUDIT=y
|
||||
CONFIG_IRQ_DOMAIN_DEBUG=y
|
||||
CONFIG_NO_HZ=y
|
||||
CONFIG_HIGH_RES_TIMERS=y
|
||||
CONFIG_BSD_PROCESS_ACCT=y
|
||||
CONFIG_IKCONFIG=y
|
||||
CONFIG_IKCONFIG_PROC=y
|
||||
CONFIG_LOG_BUF_SHIFT=14
|
||||
@ -48,6 +47,7 @@ CONFIG_HIGHMEM=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_MATH_EMULATION=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=12
|
||||
CONFIG_FSL_IFC=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_RAPIDIO=y
|
||||
@ -79,18 +79,33 @@ CONFIG_IP_SCTP=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLKDEVS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_FTL=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_GEN_PROBE=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_1=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_2=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_4=y
|
||||
CONFIG_MTD_CFI_I1=y
|
||||
CONFIG_MTD_CFI_I2=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_CFI_UTIL=y
|
||||
CONFIG_MTD_NAND_ECC=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_IDS=y
|
||||
CONFIG_MTD_NAND_FSL_ELBC=y
|
||||
CONFIG_MTD_NAND_FSL_IFC=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MTD_UBI_BEB_RESERVE=1
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
@ -106,6 +121,7 @@ CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_AHCI=y
|
||||
CONFIG_SATA_FSL=y
|
||||
CONFIG_SATA_SIL24=y
|
||||
CONFIG_PATA_ALI=y
|
||||
CONFIG_PATA_VIA=y
|
||||
CONFIG_NETDEVICES=y
|
||||
@ -113,6 +129,9 @@ CONFIG_DUMMY=y
|
||||
CONFIG_FS_ENET=y
|
||||
CONFIG_UCC_GETH=y
|
||||
CONFIG_GIANFAR=y
|
||||
CONFIG_E1000=y
|
||||
CONFIG_E1000E=y
|
||||
CONFIG_IGB=y
|
||||
CONFIG_MARVELL_PHY=y
|
||||
CONFIG_DAVICOM_PHY=y
|
||||
CONFIG_CICADA_PHY=y
|
||||
@ -132,7 +151,6 @@ CONFIG_SERIAL_8250_DETECT_IRQ=y
|
||||
CONFIG_SERIAL_8250_RSA=y
|
||||
CONFIG_SERIAL_QE=m
|
||||
CONFIG_NVRAM=y
|
||||
CONFIG_I2C=y
|
||||
CONFIG_I2C_CHARDEV=y
|
||||
CONFIG_I2C_CPM=m
|
||||
CONFIG_I2C_MPC=y
|
||||
@ -206,6 +224,15 @@ CONFIG_NTFS_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_FS_DEBUG=1
|
||||
CONFIG_JFFS2_FS_WRITEBUFFER=y
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
CONFIG_JFFS2_RTIME=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_UBIFS_FS_XATTR=y
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
CONFIG_ADFS_FS=m
|
||||
CONFIG_AFFS_FS=m
|
||||
CONFIG_HFS_FS=m
|
||||
@ -224,13 +251,18 @@ CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NFSD=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CRC16=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
CONFIG_CRYPTO_LZO=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
CONFIG_CRYPTO_PCBC=m
|
||||
CONFIG_CRYPTO_SHA256=y
|
||||
CONFIG_CRYPTO_SHA512=y
|
||||
CONFIG_CRYPTO_AES=y
|
||||
# CONFIG_CRYPTO_ANSI_CPRNG is not set
|
||||
CONFIG_CRYPTO_DEV_FSL_CAAM=y
|
||||
CONFIG_CRYPTO_DEV_TALITOS=y
|
||||
|
||||
@ -50,6 +50,7 @@ CONFIG_HIGHMEM=y
|
||||
CONFIG_BINFMT_MISC=m
|
||||
CONFIG_MATH_EMULATION=y
|
||||
CONFIG_FORCE_MAX_ZONEORDER=12
|
||||
CONFIG_FSL_IFC=y
|
||||
CONFIG_PCI=y
|
||||
CONFIG_PCI_MSI=y
|
||||
CONFIG_RAPIDIO=y
|
||||
@ -81,18 +82,33 @@ CONFIG_IP_SCTP=m
|
||||
CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug"
|
||||
CONFIG_DEVTMPFS=y
|
||||
CONFIG_MTD=y
|
||||
CONFIG_MTD_PARTITIONS=y
|
||||
CONFIG_MTD_OF_PARTS=y
|
||||
CONFIG_MTD_CMDLINE_PARTS=y
|
||||
CONFIG_MTD_CHAR=y
|
||||
CONFIG_MTD_BLKDEVS=y
|
||||
CONFIG_MTD_BLOCK=y
|
||||
CONFIG_FTL=y
|
||||
CONFIG_MTD_CFI=y
|
||||
CONFIG_MTD_GEN_PROBE=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_1=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_2=y
|
||||
CONFIG_MTD_MAP_BANK_WIDTH_4=y
|
||||
CONFIG_MTD_CFI_I1=y
|
||||
CONFIG_MTD_CFI_I2=y
|
||||
CONFIG_MTD_CFI_INTELEXT=y
|
||||
CONFIG_MTD_CFI_AMDSTD=y
|
||||
CONFIG_MTD_PHYSMAP_OF=y
|
||||
CONFIG_MTD_M25P80=y
|
||||
CONFIG_MTD_CFI_UTIL=y
|
||||
CONFIG_MTD_NAND_ECC=y
|
||||
CONFIG_MTD_NAND=y
|
||||
CONFIG_MTD_NAND_IDS=y
|
||||
CONFIG_MTD_NAND_FSL_ELBC=y
|
||||
CONFIG_MTD_NAND_FSL_IFC=y
|
||||
CONFIG_MTD_UBI=y
|
||||
CONFIG_MTD_UBI_WL_THRESHOLD=4096
|
||||
CONFIG_MTD_UBI_BEB_RESERVE=1
|
||||
CONFIG_PROC_DEVICETREE=y
|
||||
CONFIG_BLK_DEV_LOOP=y
|
||||
CONFIG_BLK_DEV_NBD=y
|
||||
@ -108,6 +124,7 @@ CONFIG_SCSI_LOGGING=y
|
||||
CONFIG_ATA=y
|
||||
CONFIG_SATA_AHCI=y
|
||||
CONFIG_SATA_FSL=y
|
||||
CONFIG_SATA_SIL24=y
|
||||
CONFIG_PATA_ALI=y
|
||||
CONFIG_NETDEVICES=y
|
||||
CONFIG_DUMMY=y
|
||||
@ -207,6 +224,15 @@ CONFIG_NTFS_FS=y
|
||||
CONFIG_PROC_KCORE=y
|
||||
CONFIG_TMPFS=y
|
||||
CONFIG_HUGETLBFS=y
|
||||
CONFIG_JFFS2_FS=y
|
||||
CONFIG_JFFS2_FS_DEBUG=1
|
||||
CONFIG_JFFS2_FS_WRITEBUFFER=y
|
||||
CONFIG_JFFS2_ZLIB=y
|
||||
CONFIG_JFFS2_RTIME=y
|
||||
CONFIG_UBIFS_FS=y
|
||||
CONFIG_UBIFS_FS_XATTR=y
|
||||
CONFIG_UBIFS_FS_LZO=y
|
||||
CONFIG_UBIFS_FS_ZLIB=y
|
||||
CONFIG_ADFS_FS=m
|
||||
CONFIG_AFFS_FS=m
|
||||
CONFIG_HFS_FS=m
|
||||
@ -225,6 +251,12 @@ CONFIG_NFS_V4=y
|
||||
CONFIG_ROOT_NFS=y
|
||||
CONFIG_NFSD=y
|
||||
CONFIG_CRC_T10DIF=y
|
||||
CONFIG_CRC16=y
|
||||
CONFIG_ZLIB_DEFLATE=y
|
||||
CONFIG_LZO_COMPRESS=y
|
||||
CONFIG_LZO_DECOMPRESS=y
|
||||
CONFIG_CRYPTO_DEFLATE=y
|
||||
CONFIG_CRYPTO_LZO=y
|
||||
CONFIG_DEBUG_FS=y
|
||||
CONFIG_DETECT_HUNG_TASK=y
|
||||
CONFIG_DEBUG_INFO=y
|
||||
|
||||
@ -375,7 +375,7 @@ extern const char *powerpc_base_platform;
|
||||
#define CPU_FTRS_E6500 (CPU_FTR_USE_TB | CPU_FTR_NODSISRALIGN | \
|
||||
CPU_FTR_L2CSR | CPU_FTR_LWSYNC | CPU_FTR_NOEXECUTE | \
|
||||
CPU_FTR_DBELL | CPU_FTR_POPCNTB | CPU_FTR_POPCNTD | \
|
||||
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV)
|
||||
CPU_FTR_DEBUG_LVL_EXC | CPU_FTR_EMB_HV | CPU_FTR_ALTIVEC_COMP)
|
||||
#define CPU_FTRS_GENERIC_32 (CPU_FTR_COMMON | CPU_FTR_NODSISRALIGN)
|
||||
|
||||
/* 64-bit CPUs */
|
||||
|
||||
@ -67,6 +67,10 @@
|
||||
#define BOOKE_INTERRUPT_HV_SYSCALL 40
|
||||
#define BOOKE_INTERRUPT_HV_PRIV 41
|
||||
|
||||
/* altivec */
|
||||
#define BOOKE_INTERRUPT_ALTIVEC_UNAVAIL 42
|
||||
#define BOOKE_INTERRUPT_ALTIVEC_ASSIST 43
|
||||
|
||||
/* book3s */
|
||||
|
||||
#define BOOK3S_INTERRUPT_SYSTEM_RESET 0x100
|
||||
|
||||
@ -70,6 +70,8 @@ struct pci_controller {
|
||||
* BIG_ENDIAN - cfg_addr is a big endian register
|
||||
* BROKEN_MRM - the 440EPx/GRx chips have an errata that causes hangs on
|
||||
* the PLB4. Effectively disable MRM commands by setting this.
|
||||
* FSL_CFG_REG_LINK - Freescale controller version in which the PCIe
|
||||
* link status is in a RC PCIe cfg register (vs being a SoC register)
|
||||
*/
|
||||
#define PPC_INDIRECT_TYPE_SET_CFG_TYPE 0x00000001
|
||||
#define PPC_INDIRECT_TYPE_EXT_REG 0x00000002
|
||||
@ -77,6 +79,7 @@ struct pci_controller {
|
||||
#define PPC_INDIRECT_TYPE_NO_PCIE_LINK 0x00000008
|
||||
#define PPC_INDIRECT_TYPE_BIG_ENDIAN 0x00000010
|
||||
#define PPC_INDIRECT_TYPE_BROKEN_MRM 0x00000020
|
||||
#define PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK 0x00000040
|
||||
u32 indirect_type;
|
||||
/* Currently, we limit ourselves to 1 IO range and 3 mem
|
||||
* ranges since the common pci_bus structure can't handle more
|
||||
@ -90,9 +93,9 @@ struct pci_controller {
|
||||
|
||||
#ifdef CONFIG_PPC64
|
||||
unsigned long buid;
|
||||
#endif /* CONFIG_PPC64 */
|
||||
|
||||
void *private_data;
|
||||
#endif /* CONFIG_PPC64 */
|
||||
};
|
||||
|
||||
/* These are used for config access before all the PCI probing
|
||||
@ -117,6 +120,12 @@ extern void setup_indirect_pci(struct pci_controller* hose,
|
||||
resource_size_t cfg_addr,
|
||||
resource_size_t cfg_data, u32 flags);
|
||||
|
||||
extern int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int offset, int len, u32 *val);
|
||||
|
||||
extern int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int offset, int len, u32 val);
|
||||
|
||||
static inline struct pci_controller *pci_bus_to_host(const struct pci_bus *bus)
|
||||
{
|
||||
return bus->sysdata;
|
||||
|
||||
@ -53,6 +53,15 @@ _GLOBAL(__e500_dcache_setup)
|
||||
isync
|
||||
blr
|
||||
|
||||
_GLOBAL(__setup_cpu_e6500)
|
||||
mflr r6
|
||||
#ifdef CONFIG_PPC64
|
||||
bl .setup_altivec_ivors
|
||||
#endif
|
||||
bl __setup_cpu_e5500
|
||||
mtlr r6
|
||||
blr
|
||||
|
||||
#ifdef CONFIG_PPC32
|
||||
_GLOBAL(__setup_cpu_e200)
|
||||
/* enable dedicated debug exception handling resources (Debug APU) */
|
||||
@ -107,6 +116,13 @@ _GLOBAL(__setup_cpu_e5500)
|
||||
#endif
|
||||
|
||||
#ifdef CONFIG_PPC_BOOK3E_64
|
||||
_GLOBAL(__restore_cpu_e6500)
|
||||
mflr r5
|
||||
bl .setup_altivec_ivors
|
||||
bl __restore_cpu_e5500
|
||||
mtlr r5
|
||||
blr
|
||||
|
||||
_GLOBAL(__restore_cpu_e5500)
|
||||
mflr r4
|
||||
bl __e500_icache_setup
|
||||
|
||||
@ -74,7 +74,9 @@ extern void __restore_cpu_a2(void);
|
||||
#endif /* CONFIG_PPC64 */
|
||||
#if defined(CONFIG_E500)
|
||||
extern void __setup_cpu_e5500(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __setup_cpu_e6500(unsigned long offset, struct cpu_spec* spec);
|
||||
extern void __restore_cpu_e5500(void);
|
||||
extern void __restore_cpu_e6500(void);
|
||||
#endif /* CONFIG_E500 */
|
||||
|
||||
/* This table only contains "desktop" CPUs, it need to be filled with embedded
|
||||
@ -2065,7 +2067,8 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.pvr_value = 0x80400000,
|
||||
.cpu_name = "e6500",
|
||||
.cpu_features = CPU_FTRS_E6500,
|
||||
.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU,
|
||||
.cpu_user_features = COMMON_USER_BOOKE | PPC_FEATURE_HAS_FPU |
|
||||
PPC_FEATURE_HAS_ALTIVEC_COMP,
|
||||
.mmu_features = MMU_FTR_TYPE_FSL_E | MMU_FTR_BIG_PHYS |
|
||||
MMU_FTR_USE_TLBILX,
|
||||
.icache_bsize = 64,
|
||||
@ -2073,9 +2076,9 @@ static struct cpu_spec __initdata cpu_specs[] = {
|
||||
.num_pmcs = 4,
|
||||
.oprofile_cpu_type = "ppc/e6500",
|
||||
.oprofile_type = PPC_OPROFILE_FSL_EMB,
|
||||
.cpu_setup = __setup_cpu_e5500,
|
||||
.cpu_setup = __setup_cpu_e6500,
|
||||
#ifndef CONFIG_PPC32
|
||||
.cpu_restore = __restore_cpu_e5500,
|
||||
.cpu_restore = __restore_cpu_e6500,
|
||||
#endif
|
||||
.machine_check = machine_check_e500mc,
|
||||
.platform = "ppce6500",
|
||||
|
||||
@ -17,6 +17,7 @@
|
||||
#include <asm/asm-compat.h>
|
||||
#include <asm/asm-offsets.h>
|
||||
|
||||
#ifndef CONFIG_PPC64
|
||||
/* epapr_ev_idle() was derived from e500_idle() */
|
||||
_GLOBAL(epapr_ev_idle)
|
||||
CURRENT_THREAD_INFO(r3, r1)
|
||||
@ -42,6 +43,7 @@ epapr_ev_idle_start:
|
||||
* _TLF_NAPPING.
|
||||
*/
|
||||
b idle_loop
|
||||
#endif
|
||||
|
||||
/* Hypercall entry point. Will be patched with device tree instructions. */
|
||||
.global epapr_hypercall_start
|
||||
|
||||
@ -299,6 +299,8 @@ interrupt_base_book3e: /* fake trap */
|
||||
EXCEPTION_STUB(0x1a0, watchdog) /* 0x09f0 */
|
||||
EXCEPTION_STUB(0x1c0, data_tlb_miss)
|
||||
EXCEPTION_STUB(0x1e0, instruction_tlb_miss)
|
||||
EXCEPTION_STUB(0x200, altivec_unavailable) /* 0x0f20 */
|
||||
EXCEPTION_STUB(0x220, altivec_assist) /* 0x1700 */
|
||||
EXCEPTION_STUB(0x260, perfmon)
|
||||
EXCEPTION_STUB(0x280, doorbell)
|
||||
EXCEPTION_STUB(0x2a0, doorbell_crit)
|
||||
@ -395,6 +397,45 @@ interrupt_end_book3e:
|
||||
bl .kernel_fp_unavailable_exception
|
||||
b .ret_from_except
|
||||
|
||||
/* Altivec Unavailable Interrupt */
|
||||
START_EXCEPTION(altivec_unavailable);
|
||||
NORMAL_EXCEPTION_PROLOG(0x200, BOOKE_INTERRUPT_ALTIVEC_UNAVAIL,
|
||||
PROLOG_ADDITION_NONE)
|
||||
/* we can probably do a shorter exception entry for that one... */
|
||||
EXCEPTION_COMMON(0x200, PACA_EXGEN, INTS_KEEP)
|
||||
#ifdef CONFIG_ALTIVEC
|
||||
BEGIN_FTR_SECTION
|
||||
ld r12,_MSR(r1)
|
||||
andi. r0,r12,MSR_PR;
|
||||
beq- 1f
|
||||
bl .load_up_altivec
|
||||
b fast_exception_return
|
||||
1:
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
||||
#endif
|
||||
INTS_DISABLE
|
||||
bl .save_nvgprs
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
bl .altivec_unavailable_exception
|
||||
b .ret_from_except
|
||||
|
||||
/* AltiVec Assist */
|
||||
START_EXCEPTION(altivec_assist);
|
||||
NORMAL_EXCEPTION_PROLOG(0x220, BOOKE_INTERRUPT_ALTIVEC_ASSIST,
|
||||
PROLOG_ADDITION_NONE)
|
||||
EXCEPTION_COMMON(0x220, PACA_EXGEN, INTS_DISABLE)
|
||||
bl .save_nvgprs
|
||||
addi r3,r1,STACK_FRAME_OVERHEAD
|
||||
#ifdef CONFIG_ALTIVEC
|
||||
BEGIN_FTR_SECTION
|
||||
bl .altivec_assist_exception
|
||||
END_FTR_SECTION_IFSET(CPU_FTR_ALTIVEC)
|
||||
#else
|
||||
bl .unknown_exception
|
||||
#endif
|
||||
b .ret_from_except
|
||||
|
||||
|
||||
/* Decrementer Interrupt */
|
||||
MASKABLE_EXCEPTION(0x900, BOOKE_INTERRUPT_DECREMENTER,
|
||||
decrementer, .timer_interrupt, ACK_DEC)
|
||||
@ -807,6 +848,7 @@ fast_exception_return:
|
||||
BAD_STACK_TRAMPOLINE(0x000)
|
||||
BAD_STACK_TRAMPOLINE(0x100)
|
||||
BAD_STACK_TRAMPOLINE(0x200)
|
||||
BAD_STACK_TRAMPOLINE(0x220)
|
||||
BAD_STACK_TRAMPOLINE(0x260)
|
||||
BAD_STACK_TRAMPOLINE(0x280)
|
||||
BAD_STACK_TRAMPOLINE(0x2a0)
|
||||
@ -1350,6 +1392,11 @@ _GLOBAL(__setup_base_ivors)
|
||||
|
||||
blr
|
||||
|
||||
_GLOBAL(setup_altivec_ivors)
|
||||
SET_IVOR(32, 0x200) /* AltiVec Unavailable */
|
||||
SET_IVOR(33, 0x220) /* AltiVec Assist */
|
||||
blr
|
||||
|
||||
_GLOBAL(setup_perfmon_ivor)
|
||||
SET_IVOR(35, 0x260) /* Performance Monitor */
|
||||
blr
|
||||
|
||||
@ -16,11 +16,13 @@
|
||||
#include <asm/ppc-opcode.h>
|
||||
#include <asm/processor.h>
|
||||
#include <asm/thread_info.h>
|
||||
#include <asm/epapr_hcalls.h>
|
||||
|
||||
/* 64-bit version only for now */
|
||||
#ifdef CONFIG_PPC64
|
||||
|
||||
_GLOBAL(book3e_idle)
|
||||
.macro BOOK3E_IDLE name loop
|
||||
_GLOBAL(\name)
|
||||
/* Save LR for later */
|
||||
mflr r0
|
||||
std r0,16(r1)
|
||||
@ -67,7 +69,33 @@ _GLOBAL(book3e_idle)
|
||||
|
||||
/* We can now re-enable hard interrupts and go to sleep */
|
||||
wrteei 1
|
||||
1: PPC_WAIT(0)
|
||||
\loop
|
||||
|
||||
.endm
|
||||
|
||||
.macro BOOK3E_IDLE_LOOP
|
||||
1:
|
||||
PPC_WAIT(0)
|
||||
b 1b
|
||||
.endm
|
||||
|
||||
/* epapr_ev_idle_start below is patched with the proper hcall
|
||||
opcodes during kernel initialization */
|
||||
.macro EPAPR_EV_IDLE_LOOP
|
||||
idle_loop:
|
||||
LOAD_REG_IMMEDIATE(r11, EV_HCALL_TOKEN(EV_IDLE))
|
||||
|
||||
.global epapr_ev_idle_start
|
||||
epapr_ev_idle_start:
|
||||
li r3, -1
|
||||
nop
|
||||
nop
|
||||
nop
|
||||
b idle_loop
|
||||
.endm
|
||||
|
||||
BOOK3E_IDLE epapr_ev_idle EPAPR_EV_IDLE_LOOP
|
||||
|
||||
BOOK3E_IDLE book3e_idle BOOK3E_IDLE_LOOP
|
||||
|
||||
#endif /* CONFIG_PPC64 */
|
||||
|
||||
@ -414,9 +414,9 @@ static void setup_page_sizes(void)
|
||||
|
||||
#ifdef CONFIG_PPC_FSL_BOOK3E
|
||||
unsigned int mmucfg = mfspr(SPRN_MMUCFG);
|
||||
int fsl_mmu = mmu_has_feature(MMU_FTR_TYPE_FSL_E);
|
||||
|
||||
if (((mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) &&
|
||||
(mmu_has_feature(MMU_FTR_TYPE_FSL_E))) {
|
||||
if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V1) {
|
||||
unsigned int tlb1cfg = mfspr(SPRN_TLB1CFG);
|
||||
unsigned int min_pg, max_pg;
|
||||
|
||||
@ -442,6 +442,20 @@ static void setup_page_sizes(void)
|
||||
|
||||
goto no_indirect;
|
||||
}
|
||||
|
||||
if (fsl_mmu && (mmucfg & MMUCFG_MAVN) == MMUCFG_MAVN_V2) {
|
||||
u32 tlb1ps = mfspr(SPRN_TLB1PS);
|
||||
|
||||
for (psize = 0; psize < MMU_PAGE_COUNT; ++psize) {
|
||||
struct mmu_psize_def *def = &mmu_psize_defs[psize];
|
||||
|
||||
if (tlb1ps & (1U << (def->shift - 10))) {
|
||||
def->flags |= MMU_PAGE_SIZE_DIRECT;
|
||||
}
|
||||
}
|
||||
|
||||
goto no_indirect;
|
||||
}
|
||||
#endif
|
||||
|
||||
tlb0cfg = mfspr(SPRN_TLB0CFG);
|
||||
|
||||
@ -305,6 +305,40 @@ config PPC_QEMU_E500
|
||||
unset based on the emulated CPU (or actual host CPU in the case
|
||||
of KVM).
|
||||
|
||||
if PPC64
|
||||
|
||||
config T4240_QDS
|
||||
bool "Freescale T4240 QDS"
|
||||
select DEFAULT_UIMAGE
|
||||
select E500
|
||||
select PPC_E500MC
|
||||
select PHYS_64BIT
|
||||
select SWIOTLB
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select GPIO_MPC8XXX
|
||||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the T4240 QDS board
|
||||
|
||||
config B4_QDS
|
||||
bool "Freescale B4 QDS"
|
||||
select DEFAULT_UIMAGE
|
||||
select E500
|
||||
select PPC_E500MC
|
||||
select PHYS_64BIT
|
||||
select SWIOTLB
|
||||
select GENERIC_GPIO
|
||||
select ARCH_REQUIRE_GPIOLIB
|
||||
select HAS_RAPIDIO
|
||||
select PPC_EPAPR_HV_PIC
|
||||
help
|
||||
This option enables support for the B4 QDS board
|
||||
The B4 application development system B4 QDS is a complete
|
||||
debugging environment intended for engineers developing
|
||||
applications for the B4.
|
||||
|
||||
endif
|
||||
endif # FSL_SOC_BOOKE
|
||||
|
||||
config TQM85xx
|
||||
|
||||
@ -22,6 +22,8 @@ obj-$(CONFIG_P3041_DS) += p3041_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_P4080_DS) += p4080_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_P5020_DS) += p5020_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_P5040_DS) += p5040_ds.o corenet_ds.o
|
||||
obj-$(CONFIG_T4240_QDS) += t4240_qds.o corenet_ds.o
|
||||
obj-$(CONFIG_B4_QDS) += b4_qds.o corenet_ds.o
|
||||
obj-$(CONFIG_STX_GP3) += stx_gp3.o
|
||||
obj-$(CONFIG_TQM85xx) += tqm85xx.o
|
||||
obj-$(CONFIG_SBC8548) += sbc8548.o
|
||||
|
||||
102
arch/powerpc/platforms/85xx/b4_qds.c
Normal file
102
arch/powerpc/platforms/85xx/b4_qds.c
Normal file
@ -0,0 +1,102 @@
|
||||
/*
|
||||
* B4 QDS Setup
|
||||
* Should apply for QDS platform of B4860 and it's personalities.
|
||||
* viz B4860/B4420/B4220QDS
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include <asm/ehv_pic.h>
|
||||
|
||||
#include "corenet_ds.h"
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init b4_qds_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
#ifdef CONFIG_SMP
|
||||
extern struct smp_ops_t smp_85xx_ops;
|
||||
#endif
|
||||
|
||||
if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS")) ||
|
||||
(of_flat_dt_is_compatible(root, "fsl,B4420QDS")) ||
|
||||
(of_flat_dt_is_compatible(root, "fsl,B4220QDS")))
|
||||
return 1;
|
||||
|
||||
/* Check if we're running under the Freescale hypervisor */
|
||||
if ((of_flat_dt_is_compatible(root, "fsl,B4860QDS-hv")) ||
|
||||
(of_flat_dt_is_compatible(root, "fsl,B4420QDS-hv")) ||
|
||||
(of_flat_dt_is_compatible(root, "fsl,B4220QDS-hv"))) {
|
||||
ppc_md.init_IRQ = ehv_pic_init;
|
||||
ppc_md.get_irq = ehv_pic_get_irq;
|
||||
ppc_md.restart = fsl_hv_restart;
|
||||
ppc_md.power_off = fsl_hv_halt;
|
||||
ppc_md.halt = fsl_hv_halt;
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Disable the timebase sync operations because we can't write
|
||||
* to the timebase registers under the hypervisor.
|
||||
*/
|
||||
smp_85xx_ops.give_timebase = NULL;
|
||||
smp_85xx_ops.take_timebase = NULL;
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
define_machine(b4_qds) {
|
||||
.name = "B4 QDS",
|
||||
.probe = b4_qds_probe,
|
||||
.setup_arch = corenet_ds_setup_arch,
|
||||
.init_IRQ = corenet_ds_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
|
||||
#ifdef CONFIG_PPC64
|
||||
.get_irq = mpic_get_irq,
|
||||
#else
|
||||
.get_irq = mpic_get_coreint_irq,
|
||||
#endif
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
#ifdef CONFIG_PPC64
|
||||
.power_save = book3e_idle,
|
||||
#else
|
||||
.power_save = e500_idle,
|
||||
#endif
|
||||
};
|
||||
|
||||
machine_arch_initcall(b4_qds, corenet_ds_publish_devices);
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
machine_arch_initcall(b4_qds, swiotlb_setup_bus_notifier);
|
||||
#endif
|
||||
@ -40,7 +40,7 @@ void __init corenet_ds_pic_init(void)
|
||||
if (ppc_md.get_irq == mpic_get_coreint_irq)
|
||||
flags |= MPIC_ENABLE_COREINT;
|
||||
|
||||
mpic = mpic_alloc(NULL, 0, flags, 0, 256, " OpenPIC ");
|
||||
mpic = mpic_alloc(NULL, 0, flags, 0, 512, " OpenPIC ");
|
||||
BUG_ON(mpic == NULL);
|
||||
|
||||
mpic_init(mpic);
|
||||
@ -83,6 +83,9 @@ static const struct of_device_id of_device_ids[] = {
|
||||
{
|
||||
.compatible = "fsl,qoriq-pcie-v2.4",
|
||||
},
|
||||
{
|
||||
.compatible = "fsl,qoriq-pcie-v3.0",
|
||||
},
|
||||
/* The following two are for the Freescale hypervisor */
|
||||
{
|
||||
.name = "hypervisor",
|
||||
|
||||
@ -201,7 +201,7 @@ static int __cpuinit smp_85xx_kick_cpu(int nr)
|
||||
* We don't set the BPTR register here since it already points
|
||||
* to the boot page properly.
|
||||
*/
|
||||
mpic_reset_core(hw_cpu);
|
||||
mpic_reset_core(nr);
|
||||
|
||||
/*
|
||||
* wait until core is ready...
|
||||
|
||||
98
arch/powerpc/platforms/85xx/t4240_qds.c
Normal file
98
arch/powerpc/platforms/85xx/t4240_qds.c
Normal file
@ -0,0 +1,98 @@
|
||||
/*
|
||||
* T4240 QDS Setup
|
||||
*
|
||||
* Maintained by Kumar Gala (see MAINTAINERS for contact information)
|
||||
*
|
||||
* Copyright 2012 Freescale Semiconductor Inc.
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify it
|
||||
* under the terms of the GNU General Public License as published by the
|
||||
* Free Software Foundation; either version 2 of the License, or (at your
|
||||
* option) any later version.
|
||||
*/
|
||||
|
||||
#include <linux/kernel.h>
|
||||
#include <linux/pci.h>
|
||||
#include <linux/kdev_t.h>
|
||||
#include <linux/delay.h>
|
||||
#include <linux/interrupt.h>
|
||||
#include <linux/phy.h>
|
||||
|
||||
#include <asm/time.h>
|
||||
#include <asm/machdep.h>
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <mm/mmu_decl.h>
|
||||
#include <asm/prom.h>
|
||||
#include <asm/udbg.h>
|
||||
#include <asm/mpic.h>
|
||||
|
||||
#include <linux/of_platform.h>
|
||||
#include <sysdev/fsl_soc.h>
|
||||
#include <sysdev/fsl_pci.h>
|
||||
#include <asm/ehv_pic.h>
|
||||
|
||||
#include "corenet_ds.h"
|
||||
|
||||
/*
|
||||
* Called very early, device-tree isn't unflattened
|
||||
*/
|
||||
static int __init t4240_qds_probe(void)
|
||||
{
|
||||
unsigned long root = of_get_flat_dt_root();
|
||||
#ifdef CONFIG_SMP
|
||||
extern struct smp_ops_t smp_85xx_ops;
|
||||
#endif
|
||||
|
||||
if (of_flat_dt_is_compatible(root, "fsl,T4240QDS"))
|
||||
return 1;
|
||||
|
||||
/* Check if we're running under the Freescale hypervisor */
|
||||
if (of_flat_dt_is_compatible(root, "fsl,T4240QDS-hv")) {
|
||||
ppc_md.init_IRQ = ehv_pic_init;
|
||||
ppc_md.get_irq = ehv_pic_get_irq;
|
||||
ppc_md.restart = fsl_hv_restart;
|
||||
ppc_md.power_off = fsl_hv_halt;
|
||||
ppc_md.halt = fsl_hv_halt;
|
||||
#ifdef CONFIG_SMP
|
||||
/*
|
||||
* Disable the timebase sync operations because we can't write
|
||||
* to the timebase registers under the hypervisor.
|
||||
*/
|
||||
smp_85xx_ops.give_timebase = NULL;
|
||||
smp_85xx_ops.take_timebase = NULL;
|
||||
#endif
|
||||
return 1;
|
||||
}
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
define_machine(t4240_qds) {
|
||||
.name = "T4240 QDS",
|
||||
.probe = t4240_qds_probe,
|
||||
.setup_arch = corenet_ds_setup_arch,
|
||||
.init_IRQ = corenet_ds_pic_init,
|
||||
#ifdef CONFIG_PCI
|
||||
.pcibios_fixup_bus = fsl_pcibios_fixup_bus,
|
||||
#endif
|
||||
/* coreint doesn't play nice with lazy EE, use legacy mpic for now */
|
||||
#ifdef CONFIG_PPC64
|
||||
.get_irq = mpic_get_irq,
|
||||
#else
|
||||
.get_irq = mpic_get_coreint_irq,
|
||||
#endif
|
||||
.restart = fsl_rstcr_restart,
|
||||
.calibrate_decr = generic_calibrate_decr,
|
||||
.progress = udbg_progress,
|
||||
#ifdef CONFIG_PPC64
|
||||
.power_save = book3e_idle,
|
||||
#else
|
||||
.power_save = e500_idle,
|
||||
#endif
|
||||
};
|
||||
|
||||
machine_arch_initcall(t4240_qds, corenet_ds_publish_devices);
|
||||
|
||||
#ifdef CONFIG_SWIOTLB
|
||||
machine_arch_initcall(t4240_qds, swiotlb_setup_bus_notifier);
|
||||
#endif
|
||||
@ -343,7 +343,6 @@ config FSL_ULI1575
|
||||
|
||||
config CPM
|
||||
bool
|
||||
select PPC_CLOCK
|
||||
|
||||
config OF_RTC
|
||||
bool
|
||||
|
||||
@ -230,7 +230,7 @@ config PHYS_64BIT
|
||||
|
||||
config ALTIVEC
|
||||
bool "AltiVec Support"
|
||||
depends on 6xx || POWER4
|
||||
depends on 6xx || POWER4 || (PPC_E500MC && PPC64)
|
||||
---help---
|
||||
This option enables kernel support for the Altivec extensions to the
|
||||
PowerPC processor. The kernel currently supports saving and restoring
|
||||
|
||||
@ -333,6 +333,8 @@ static int fsl_of_msi_remove(struct platform_device *ofdev)
|
||||
return 0;
|
||||
}
|
||||
|
||||
static struct lock_class_key fsl_msi_irq_class;
|
||||
|
||||
static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
|
||||
int offset, int irq_index)
|
||||
{
|
||||
@ -351,7 +353,7 @@ static int fsl_msi_setup_hwirq(struct fsl_msi *msi, struct platform_device *dev,
|
||||
dev_err(&dev->dev, "No memory for MSI cascade data\n");
|
||||
return -ENOMEM;
|
||||
}
|
||||
|
||||
irq_set_lockdep_class(virt_msir, &fsl_msi_irq_class);
|
||||
msi->msi_virqs[irq_index] = virt_msir;
|
||||
cascade_data->index = offset;
|
||||
cascade_data->msi_data = msi;
|
||||
|
||||
@ -54,16 +54,63 @@ static void quirk_fsl_pcie_header(struct pci_dev *dev)
|
||||
return;
|
||||
}
|
||||
|
||||
static int __init fsl_pcie_check_link(struct pci_controller *hose)
|
||||
{
|
||||
u32 val;
|
||||
static int fsl_indirect_read_config(struct pci_bus *, unsigned int,
|
||||
int, int, u32 *);
|
||||
|
||||
static int fsl_pcie_check_link(struct pci_controller *hose)
|
||||
{
|
||||
u32 val = 0;
|
||||
|
||||
if (hose->indirect_type & PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK) {
|
||||
if (hose->ops->read == fsl_indirect_read_config) {
|
||||
struct pci_bus bus;
|
||||
bus.number = 0;
|
||||
bus.sysdata = hose;
|
||||
bus.ops = hose->ops;
|
||||
indirect_read_config(&bus, 0, PCIE_LTSSM, 4, &val);
|
||||
} else
|
||||
early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
|
||||
if (val < PCIE_LTSSM_L0)
|
||||
return 1;
|
||||
} else {
|
||||
struct ccsr_pci __iomem *pci = hose->private_data;
|
||||
/* for PCIe IP rev 3.0 or greater use CSR0 for link state */
|
||||
val = (in_be32(&pci->pex_csr0) & PEX_CSR0_LTSSM_MASK)
|
||||
>> PEX_CSR0_LTSSM_SHIFT;
|
||||
if (val != PEX_CSR0_LTSSM_L0)
|
||||
return 1;
|
||||
}
|
||||
|
||||
early_read_config_dword(hose, 0, 0, PCIE_LTSSM, &val);
|
||||
if (val < PCIE_LTSSM_L0)
|
||||
return 1;
|
||||
return 0;
|
||||
}
|
||||
|
||||
static int fsl_indirect_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int offset, int len, u32 *val)
|
||||
{
|
||||
struct pci_controller *hose = pci_bus_to_host(bus);
|
||||
|
||||
if (fsl_pcie_check_link(hose))
|
||||
hose->indirect_type |= PPC_INDIRECT_TYPE_NO_PCIE_LINK;
|
||||
else
|
||||
hose->indirect_type &= ~PPC_INDIRECT_TYPE_NO_PCIE_LINK;
|
||||
|
||||
return indirect_read_config(bus, devfn, offset, len, val);
|
||||
}
|
||||
|
||||
static struct pci_ops fsl_indirect_pci_ops =
|
||||
{
|
||||
.read = fsl_indirect_read_config,
|
||||
.write = indirect_write_config,
|
||||
};
|
||||
|
||||
static void __init fsl_setup_indirect_pci(struct pci_controller* hose,
|
||||
resource_size_t cfg_addr,
|
||||
resource_size_t cfg_data, u32 flags)
|
||||
{
|
||||
setup_indirect_pci(hose, cfg_addr, cfg_data, flags);
|
||||
hose->ops = &fsl_indirect_pci_ops;
|
||||
}
|
||||
|
||||
#if defined(CONFIG_FSL_SOC_BOOKE) || defined(CONFIG_PPC_86xx)
|
||||
|
||||
#define MAX_PHYS_ADDR_BITS 40
|
||||
@ -106,7 +153,7 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
|
||||
flags |= 0x10000000; /* enable relaxed ordering */
|
||||
|
||||
for (i = 0; size > 0; i++) {
|
||||
unsigned int bits = min(__ilog2(size),
|
||||
unsigned int bits = min(ilog2(size),
|
||||
__ffs(pci_addr | phys_addr));
|
||||
|
||||
if (index + i >= 5)
|
||||
@ -126,10 +173,9 @@ static int setup_one_atmu(struct ccsr_pci __iomem *pci,
|
||||
}
|
||||
|
||||
/* atmu setup for fsl pci/pcie controller */
|
||||
static void setup_pci_atmu(struct pci_controller *hose,
|
||||
struct resource *rsrc)
|
||||
static void setup_pci_atmu(struct pci_controller *hose)
|
||||
{
|
||||
struct ccsr_pci __iomem *pci;
|
||||
struct ccsr_pci __iomem *pci = hose->private_data;
|
||||
int i, j, n, mem_log, win_idx = 3, start_idx = 1, end_idx = 4;
|
||||
u64 mem, sz, paddr_hi = 0;
|
||||
u64 paddr_lo = ULLONG_MAX;
|
||||
@ -140,15 +186,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
|
||||
const u64 *reg;
|
||||
int len;
|
||||
|
||||
pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
|
||||
(u64)rsrc->start, (u64)resource_size(rsrc));
|
||||
|
||||
pci = ioremap(rsrc->start, resource_size(rsrc));
|
||||
if (!pci) {
|
||||
dev_err(hose->parent, "Unable to map ATMU registers\n");
|
||||
return;
|
||||
}
|
||||
|
||||
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
|
||||
if (in_be32(&pci->block_rev1) >= PCIE_IP_REV_2_2) {
|
||||
win_idx = 2;
|
||||
@ -196,7 +233,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
|
||||
out_be32(&pci->pow[j].powbar, (hose->io_base_phys >> 12));
|
||||
/* Enable, IO R/W */
|
||||
out_be32(&pci->pow[j].powar, 0x80088000
|
||||
| (__ilog2(hose->io_resource.end
|
||||
| (ilog2(hose->io_resource.end
|
||||
- hose->io_resource.start + 1) - 1));
|
||||
}
|
||||
}
|
||||
@ -207,12 +244,12 @@ static void setup_pci_atmu(struct pci_controller *hose,
|
||||
|
||||
if (paddr_hi == paddr_lo) {
|
||||
pr_err("%s: No outbound window space\n", name);
|
||||
goto out;
|
||||
return;
|
||||
}
|
||||
|
||||
if (paddr_lo == 0) {
|
||||
pr_err("%s: No space for inbound window\n", name);
|
||||
goto out;
|
||||
return;
|
||||
}
|
||||
|
||||
/* setup PCSRBAR/PEXCSRBAR */
|
||||
@ -261,7 +298,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
|
||||
}
|
||||
|
||||
sz = min(mem, paddr_lo);
|
||||
mem_log = __ilog2_u64(sz);
|
||||
mem_log = ilog2(sz);
|
||||
|
||||
/* PCIe can overmap inbound & outbound since RX & TX are separated */
|
||||
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
|
||||
@ -290,7 +327,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
|
||||
* SWIOTLB and access the full range of memory
|
||||
*/
|
||||
if (sz != mem) {
|
||||
mem_log = __ilog2_u64(mem);
|
||||
mem_log = ilog2(mem);
|
||||
|
||||
/* Size window up if we dont fit in exact power-of-2 */
|
||||
if ((1ull << mem_log) != mem)
|
||||
@ -327,7 +364,7 @@ static void setup_pci_atmu(struct pci_controller *hose,
|
||||
sz -= 1ull << mem_log;
|
||||
|
||||
if (sz) {
|
||||
mem_log = __ilog2_u64(sz);
|
||||
mem_log = ilog2(sz);
|
||||
piwar |= (mem_log - 1);
|
||||
|
||||
out_be32(&pci->piw[win_idx].pitar, paddr >> 12);
|
||||
@ -358,9 +395,6 @@ static void setup_pci_atmu(struct pci_controller *hose,
|
||||
pr_info("%s: DMA window size is 0x%llx\n", name,
|
||||
(u64)hose->dma_window_size);
|
||||
}
|
||||
|
||||
out:
|
||||
iounmap(pci);
|
||||
}
|
||||
|
||||
static void __init setup_pci_cmd(struct pci_controller *hose)
|
||||
@ -429,6 +463,7 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
|
||||
const int *bus_range;
|
||||
u8 hdr_type, progif;
|
||||
struct device_node *dev;
|
||||
struct ccsr_pci __iomem *pci;
|
||||
|
||||
dev = pdev->dev.of_node;
|
||||
|
||||
@ -461,8 +496,18 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
|
||||
hose->first_busno = bus_range ? bus_range[0] : 0x0;
|
||||
hose->last_busno = bus_range ? bus_range[1] : 0xff;
|
||||
|
||||
setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
|
||||
PPC_INDIRECT_TYPE_BIG_ENDIAN);
|
||||
pr_debug("PCI memory map start 0x%016llx, size 0x%016llx\n",
|
||||
(u64)rsrc.start, (u64)resource_size(&rsrc));
|
||||
|
||||
pci = hose->private_data = ioremap(rsrc.start, resource_size(&rsrc));
|
||||
if (!hose->private_data)
|
||||
goto no_bridge;
|
||||
|
||||
fsl_setup_indirect_pci(hose, rsrc.start, rsrc.start + 0x4,
|
||||
PPC_INDIRECT_TYPE_BIG_ENDIAN);
|
||||
|
||||
if (in_be32(&pci->block_rev1) < PCIE_IP_REV_3_0)
|
||||
hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
|
||||
|
||||
if (early_find_capability(hose, 0, 0, PCI_CAP_ID_EXP)) {
|
||||
/* For PCIE read HEADER_TYPE to identify controler mode */
|
||||
@ -500,11 +545,12 @@ int __init fsl_add_bridge(struct platform_device *pdev, int is_primary)
|
||||
pci_process_bridge_OF_ranges(hose, dev, is_primary);
|
||||
|
||||
/* Setup PEX window registers */
|
||||
setup_pci_atmu(hose, &rsrc);
|
||||
setup_pci_atmu(hose);
|
||||
|
||||
return 0;
|
||||
|
||||
no_bridge:
|
||||
iounmap(hose->private_data);
|
||||
/* unmap cfg_data & cfg_addr separately if not on same page */
|
||||
if (((unsigned long)hose->cfg_data & PAGE_MASK) !=
|
||||
((unsigned long)hose->cfg_addr & PAGE_MASK))
|
||||
@ -681,6 +727,7 @@ static int __init mpc83xx_pcie_setup(struct pci_controller *hose,
|
||||
WARN_ON(hose->dn->data);
|
||||
hose->dn->data = pcie;
|
||||
hose->ops = &mpc83xx_pcie_ops;
|
||||
hose->indirect_type |= PPC_INDIRECT_TYPE_FSL_CFG_REG_LINK;
|
||||
|
||||
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAH, 0);
|
||||
out_le32(pcie->cfg_type0 + PEX_OUTWIN0_TAL, 0);
|
||||
@ -766,8 +813,8 @@ int __init mpc83xx_add_bridge(struct device_node *dev)
|
||||
if (ret)
|
||||
goto err0;
|
||||
} else {
|
||||
setup_indirect_pci(hose, rsrc_cfg.start,
|
||||
rsrc_cfg.start + 4, 0);
|
||||
fsl_setup_indirect_pci(hose, rsrc_cfg.start,
|
||||
rsrc_cfg.start + 4, 0);
|
||||
}
|
||||
|
||||
printk(KERN_INFO "Found FSL PCI host bridge at 0x%016llx. "
|
||||
@ -836,6 +883,7 @@ static const struct of_device_id pci_ids[] = {
|
||||
{ .compatible = "fsl,qoriq-pcie-v2.2", },
|
||||
{ .compatible = "fsl,qoriq-pcie-v2.3", },
|
||||
{ .compatible = "fsl,qoriq-pcie-v2.4", },
|
||||
{ .compatible = "fsl,qoriq-pcie-v3.0", },
|
||||
|
||||
/*
|
||||
* The following entries are for compatibility with older device
|
||||
|
||||
@ -14,9 +14,12 @@
|
||||
#ifndef __POWERPC_FSL_PCI_H
|
||||
#define __POWERPC_FSL_PCI_H
|
||||
|
||||
struct platform_device;
|
||||
|
||||
#define PCIE_LTSSM 0x0404 /* PCIE Link Training and Status */
|
||||
#define PCIE_LTSSM_L0 0x16 /* L0 state */
|
||||
#define PCIE_IP_REV_2_2 0x02080202 /* PCIE IP block version Rev2.2 */
|
||||
#define PCIE_IP_REV_3_0 0x02080300 /* PCIE IP block version Rev3.0 */
|
||||
#define PIWAR_EN 0x80000000 /* Enable */
|
||||
#define PIWAR_PF 0x20000000 /* prefetch */
|
||||
#define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */
|
||||
@ -89,6 +92,16 @@ struct ccsr_pci {
|
||||
__be32 pex_err_cap_r1; /* 0x.e2c - PCIE error capture register 0 */
|
||||
__be32 pex_err_cap_r2; /* 0x.e30 - PCIE error capture register 0 */
|
||||
__be32 pex_err_cap_r3; /* 0x.e34 - PCIE error capture register 0 */
|
||||
u8 res_e38[200];
|
||||
__be32 pdb_stat; /* 0x.f00 - PCIE Debug Status */
|
||||
u8 res_f04[16];
|
||||
__be32 pex_csr0; /* 0x.f14 - PEX Control/Status register 0*/
|
||||
#define PEX_CSR0_LTSSM_MASK 0xFC
|
||||
#define PEX_CSR0_LTSSM_SHIFT 2
|
||||
#define PEX_CSR0_LTSSM_L0 0x11
|
||||
__be32 pex_csr1; /* 0x.f18 - PEX Control/Status register 1*/
|
||||
u8 res_f1c[228];
|
||||
|
||||
};
|
||||
|
||||
extern int fsl_add_bridge(struct platform_device *pdev, int is_primary);
|
||||
|
||||
@ -20,9 +20,8 @@
|
||||
#include <asm/pci-bridge.h>
|
||||
#include <asm/machdep.h>
|
||||
|
||||
static int
|
||||
indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
|
||||
int len, u32 *val)
|
||||
int indirect_read_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int offset, int len, u32 *val)
|
||||
{
|
||||
struct pci_controller *hose = pci_bus_to_host(bus);
|
||||
volatile void __iomem *cfg_data;
|
||||
@ -78,9 +77,8 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
|
||||
return PCIBIOS_SUCCESSFUL;
|
||||
}
|
||||
|
||||
static int
|
||||
indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
|
||||
int len, u32 val)
|
||||
int indirect_write_config(struct pci_bus *bus, unsigned int devfn,
|
||||
int offset, int len, u32 val)
|
||||
{
|
||||
struct pci_controller *hose = pci_bus_to_host(bus);
|
||||
volatile void __iomem *cfg_data;
|
||||
|
||||
@ -22,6 +22,6 @@ config UCC
|
||||
|
||||
config QE_USB
|
||||
bool
|
||||
default y if USB_GADGET_FSL_QE
|
||||
default y if USB_FSL_QE
|
||||
help
|
||||
QE USB Controller support
|
||||
|
||||
Loading…
Reference in New Issue
Block a user