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drm/amd/powerplay: add new Fiji function for not setting same ps.
Add comparison function used by powerplay to determine which power state to select. Signed-off-by: Rex Zhu <Rex.Zhu@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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@ -5195,6 +5195,67 @@ static int fiji_print_clock_levels(struct pp_hwmgr *hwmgr,
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return size;
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}
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static inline bool fiji_are_power_levels_equal(const struct fiji_performance_level *pl1,
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const struct fiji_performance_level *pl2)
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{
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return ((pl1->memory_clock == pl2->memory_clock) &&
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(pl1->engine_clock == pl2->engine_clock) &&
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(pl1->pcie_gen == pl2->pcie_gen) &&
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(pl1->pcie_lane == pl2->pcie_lane));
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}
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int fiji_check_states_equal(struct pp_hwmgr *hwmgr, const struct pp_hw_power_state *pstate1, const struct pp_hw_power_state *pstate2, bool *equal)
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{
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const struct fiji_power_state *psa = cast_const_phw_fiji_power_state(pstate1);
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const struct fiji_power_state *psb = cast_const_phw_fiji_power_state(pstate2);
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int i;
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if (equal == NULL || psa == NULL || psb == NULL)
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return -EINVAL;
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/* If the two states don't even have the same number of performance levels they cannot be the same state. */
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if (psa->performance_level_count != psb->performance_level_count) {
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*equal = false;
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return 0;
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}
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for (i = 0; i < psa->performance_level_count; i++) {
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if (!fiji_are_power_levels_equal(&(psa->performance_levels[i]), &(psb->performance_levels[i]))) {
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/* If we have found even one performance level pair that is different the states are different. */
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*equal = false;
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return 0;
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}
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}
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/* If all performance levels are the same try to use the UVD clocks to break the tie.*/
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*equal = ((psa->uvd_clks.vclk == psb->uvd_clks.vclk) && (psa->uvd_clks.dclk == psb->uvd_clks.dclk));
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*equal &= ((psa->vce_clks.evclk == psb->vce_clks.evclk) && (psa->vce_clks.ecclk == psb->vce_clks.ecclk));
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*equal &= (psa->sclk_threshold == psb->sclk_threshold);
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*equal &= (psa->acp_clk == psb->acp_clk);
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return 0;
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}
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bool fiji_check_smc_update_required_for_display_configuration(struct pp_hwmgr *hwmgr)
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{
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struct fiji_hwmgr *data = (struct fiji_hwmgr *)(hwmgr->backend);
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bool is_update_required = false;
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struct cgs_display_info info = {0,0,NULL};
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cgs_get_active_displays_info(hwmgr->device, &info);
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if (data->display_timing.num_existing_displays != info.display_count)
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is_update_required = true;
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/* TO DO NEED TO GET DEEP SLEEP CLOCK FROM DAL
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if (phm_cap_enabled(hwmgr->hwmgr->platform_descriptor.platformCaps, PHM_PlatformCaps_SclkDeepSleep)) {
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cgs_get_min_clock_settings(hwmgr->device, &min_clocks);
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if(min_clocks.engineClockInSR != data->display_timing.minClockInSR)
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is_update_required = true;
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*/
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return is_update_required;
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}
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static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
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.backend_init = &fiji_hwmgr_backend_init,
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.backend_fini = &tonga_hwmgr_backend_fini,
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@ -5230,6 +5291,8 @@ static const struct pp_hwmgr_func fiji_hwmgr_funcs = {
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.register_internal_thermal_interrupt = fiji_register_internal_thermal_interrupt,
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.set_fan_control_mode = fiji_set_fan_control_mode,
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.get_fan_control_mode = fiji_get_fan_control_mode,
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.check_states_equal = fiji_check_states_equal,
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.check_smc_update_required_for_display_configuration = fiji_check_smc_update_required_for_display_configuration,
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.get_pp_table = fiji_get_pp_table,
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.set_pp_table = fiji_set_pp_table,
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.force_clock_level = fiji_force_clock_level,
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