mirror of
https://mirrors.bfsu.edu.cn/git/linux.git
synced 2024-11-19 18:24:14 +08:00
tty: serial: samsung: add byte-order aware bit functions
This driver makes use of the __set_bit() and __clear_bit() functions. When running under big-endian, these functions don't convert the bit indexes when working with peripheral registers, leading to the incorrect bits being set and cleared when running big-endian. Add two new driver functions for setting and clearing bits that are byte-order aware. Signed-off-by: Matthew Leach <matthew@mattleach.net> Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This commit is contained in:
parent
e37697b3f7
commit
bbb5ff9122
@ -169,8 +169,7 @@ static void s3c24xx_serial_stop_tx(struct uart_port *port)
|
||||
return;
|
||||
|
||||
if (s3c24xx_serial_has_interrupt_mask(port))
|
||||
__set_bit(S3C64XX_UINTM_TXD,
|
||||
portaddrl(port, S3C64XX_UINTM));
|
||||
s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
|
||||
else
|
||||
disable_irq_nosync(ourport->tx_irq);
|
||||
|
||||
@ -235,8 +234,7 @@ static void enable_tx_dma(struct s3c24xx_uart_port *ourport)
|
||||
|
||||
/* Mask Tx interrupt */
|
||||
if (s3c24xx_serial_has_interrupt_mask(port))
|
||||
__set_bit(S3C64XX_UINTM_TXD,
|
||||
portaddrl(port, S3C64XX_UINTM));
|
||||
s3c24xx_set_bit(port, S3C64XX_UINTM_TXD, S3C64XX_UINTM);
|
||||
else
|
||||
disable_irq_nosync(ourport->tx_irq);
|
||||
|
||||
@ -269,8 +267,8 @@ static void enable_tx_pio(struct s3c24xx_uart_port *ourport)
|
||||
|
||||
/* Unmask Tx interrupt */
|
||||
if (s3c24xx_serial_has_interrupt_mask(port))
|
||||
__clear_bit(S3C64XX_UINTM_TXD,
|
||||
portaddrl(port, S3C64XX_UINTM));
|
||||
s3c24xx_clear_bit(port, S3C64XX_UINTM_TXD,
|
||||
S3C64XX_UINTM);
|
||||
else
|
||||
enable_irq(ourport->tx_irq);
|
||||
|
||||
@ -397,8 +395,8 @@ static void s3c24xx_serial_stop_rx(struct uart_port *port)
|
||||
if (rx_enabled(port)) {
|
||||
dbg("s3c24xx_serial_stop_rx: port=%p\n", port);
|
||||
if (s3c24xx_serial_has_interrupt_mask(port))
|
||||
__set_bit(S3C64XX_UINTM_RXD,
|
||||
portaddrl(port, S3C64XX_UINTM));
|
||||
s3c24xx_set_bit(port, S3C64XX_UINTM_RXD,
|
||||
S3C64XX_UINTM);
|
||||
else
|
||||
disable_irq_nosync(ourport->rx_irq);
|
||||
rx_enabled(port) = 0;
|
||||
@ -1069,7 +1067,7 @@ static int s3c64xx_serial_startup(struct uart_port *port)
|
||||
spin_unlock_irqrestore(&port->lock, flags);
|
||||
|
||||
/* Enable Rx Interrupt */
|
||||
__clear_bit(S3C64XX_UINTM_RXD, portaddrl(port, S3C64XX_UINTM));
|
||||
s3c24xx_clear_bit(port, S3C64XX_UINTM_RXD, S3C64XX_UINTM);
|
||||
|
||||
dbg("s3c64xx_serial_startup ok\n");
|
||||
return ret;
|
||||
|
@ -123,4 +123,32 @@ struct s3c24xx_uart_port {
|
||||
#define wr_regb(port, reg, val) writeb_relaxed(val, portaddr(port, reg))
|
||||
#define wr_regl(port, reg, val) writel_relaxed(val, portaddr(port, reg))
|
||||
|
||||
/* Byte-order aware bit setting/clearing functions. */
|
||||
|
||||
static inline void s3c24xx_set_bit(struct uart_port *port, int idx,
|
||||
unsigned int reg)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
local_irq_save(flags);
|
||||
val = rd_regl(port, reg);
|
||||
val |= (1 << idx);
|
||||
wr_regl(port, reg, val);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
static inline void s3c24xx_clear_bit(struct uart_port *port, int idx,
|
||||
unsigned int reg)
|
||||
{
|
||||
unsigned long flags;
|
||||
u32 val;
|
||||
|
||||
local_irq_save(flags);
|
||||
val = rd_regl(port, reg);
|
||||
val &= ~(1 << idx);
|
||||
wr_regl(port, reg, val);
|
||||
local_irq_restore(flags);
|
||||
}
|
||||
|
||||
#endif
|
||||
|
Loading…
Reference in New Issue
Block a user