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[MIPS] MIPS64 R2 optimizations for 64-bit endianess swapping.

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Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
This commit is contained in:
Ralf Baechle 2006-02-15 13:06:34 +00:00
parent e87dddeb92
commit bbad8123f3
1 changed files with 18 additions and 0 deletions
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18
include/asm-mips/byteorder.h
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@ -39,6 +39,24 @@ static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
}
#define __arch__swab32(x) ___arch__swab32(x)
#ifdef CONFIG_CPU_MIPS64_R2
static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
{
__asm__(
" dsbh %0, %1 \n"
" dshd %0, %0 \n"
" drotr %0, %0, 32 \n"
: "=r" (x)
: "r" (x));
return x;
}
#define __arch__swab64(x) ___arch__swab64(x)
#endif /* CONFIG_CPU_MIPS64_R2 */
#endif /* CONFIG_CPU_MIPSR2 */
#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)