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mei: me: d0i3: add flag to indicate D0i3 support
Detect d0i3 low power state during hw configuration, the value is set in HFS_1 pci config reigister. Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com> Signed-off-by: Tomas Winkler <tomas.winkler@intel.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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@ -123,6 +123,7 @@
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/* Host Firmware Status Registers in PCI Config Space */
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#define PCI_CFG_HFS_1 0x40
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# define PCI_CFG_HFS_1_D0I3_MSK 0x80000000
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#define PCI_CFG_HFS_2 0x48
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#define PCI_CFG_HFS_3 0x60
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#define PCI_CFG_HFS_4 0x64
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@ -176,12 +176,20 @@ static int mei_me_fw_status(struct mei_device *dev,
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*/
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static void mei_me_hw_config(struct mei_device *dev)
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{
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struct pci_dev *pdev = to_pci_dev(dev->dev);
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struct mei_me_hw *hw = to_me_hw(dev);
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u32 hcsr = mei_hcsr_read(dev);
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u32 hcsr, reg;
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/* Doesn't change in runtime */
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hcsr = mei_hcsr_read(dev);
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dev->hbuf_depth = (hcsr & H_CBD) >> 24;
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hw->pg_state = MEI_PG_OFF;
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reg = 0;
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pci_read_config_dword(pdev, PCI_CFG_HFS_1, ®);
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hw->d0i3_supported =
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((reg & PCI_CFG_HFS_1_D0I3_MSK) == PCI_CFG_HFS_1_D0I3_MSK);
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}
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/**
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@ -50,13 +50,15 @@ struct mei_cfg {
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* struct mei_me_hw - me hw specific data
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*
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* @cfg: per device generation config and ops
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* @mem_addr: io memory address
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* @pg_state: power gating state
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* @mem_addr: io memory address
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* @pg_state: power gating state
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* @d0i3_supported: di03 support
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*/
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struct mei_me_hw {
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const struct mei_cfg *cfg;
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void __iomem *mem_addr;
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enum mei_pg_state pg_state;
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bool d0i3_supported;
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};
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#define to_me_hw(dev) (struct mei_me_hw *)((dev)->hw)
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