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Merge branch 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/drm-intel into drm-fixes
* 'drm-intel-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/jbarnes/drm-intel: drm/i915: do not enable RC6p on Sandy Bridge drm/i915: gen7: Disable the RHWO optimization as it can cause GPU hangs. drm/i915: gen7: work around a system hang on IVB drm/i915: gen7: Implement an L3 caching workaround. drm/i915: gen7: implement rczunit workaround
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commit
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@ -3028,6 +3028,20 @@
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#define DISP_TILE_SURFACE_SWIZZLING (1<<13)
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#define DISP_FBC_WM_DIS (1<<15)
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/* GEN7 chicken */
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#define GEN7_COMMON_SLICE_CHICKEN1 0x7010
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# define GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC ((1<<10) | (1<<26))
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#define GEN7_L3CNTLREG1 0xB01C
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#define GEN7_WA_FOR_GEN7_L3_CONTROL 0x3C4FFF8C
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#define GEN7_L3_CHICKEN_MODE_REGISTER 0xB030
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#define GEN7_WA_L3_CHICKEN_MODE 0x20000000
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/* WaCatErrorRejectionIssue */
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#define GEN7_SQ_CHICKEN_MBCUNIT_CONFIG 0x9030
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#define GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB (1<<11)
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/* PCH */
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/* south display engine interrupt */
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@ -3618,6 +3632,7 @@
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#define GT_FIFO_NUM_RESERVED_ENTRIES 20
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#define GEN6_UCGCTL2 0x9404
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# define GEN6_RCZUNIT_CLOCK_GATE_DISABLE (1 << 13)
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# define GEN6_RCPBUNIT_CLOCK_GATE_DISABLE (1 << 12)
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# define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11)
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@ -8184,8 +8184,8 @@ void gen6_enable_rps(struct drm_i915_private *dev_priv)
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I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
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if (intel_enable_rc6(dev_priv->dev))
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rc6_mask = GEN6_RC_CTL_RC6p_ENABLE |
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GEN6_RC_CTL_RC6_ENABLE;
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rc6_mask = GEN6_RC_CTL_RC6_ENABLE |
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(IS_GEN7(dev_priv->dev)) ? GEN6_RC_CTL_RC6p_ENABLE : 0;
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I915_WRITE(GEN6_RC_CONTROL,
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rc6_mask |
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@ -8463,12 +8463,32 @@ static void ivybridge_init_clock_gating(struct drm_device *dev)
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I915_WRITE(WM2_LP_ILK, 0);
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I915_WRITE(WM1_LP_ILK, 0);
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/* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
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* This implements the WaDisableRCZUnitClockGating workaround.
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*/
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I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
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I915_WRITE(ILK_DSPCLK_GATE, IVB_VRHUNIT_CLK_GATE);
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I915_WRITE(IVB_CHICKEN3,
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CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
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CHICKEN3_DGMG_DONE_FIX_DISABLE);
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/* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
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I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
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GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
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/* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
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I915_WRITE(GEN7_L3CNTLREG1,
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GEN7_WA_FOR_GEN7_L3_CONTROL);
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I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
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GEN7_WA_L3_CHICKEN_MODE);
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/* This is required by WaCatErrorRejectionIssue */
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I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
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I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
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GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
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for_each_pipe(pipe) {
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I915_WRITE(DSPCNTR(pipe),
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I915_READ(DSPCNTR(pipe)) |
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