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drm/radeon: convert fence to uint64_t v4
This convert fence to use uint64_t sequence number intention is
to use the fact that uin64_t is big enough that we don't need to
care about wrap around.
Tested with and without writeback using 0xFFFFF000 as initial
fence sequence and thus allowing to test the wrap around from
32bits to 64bits.
v2: Add comment about possible race btw CPU & GPU, add comment
stressing that we need 2 dword aligned for R600_WB_EVENT_OFFSET
Read fence sequenc in reverse order of GPU write them so we
mitigate the race btw CPU and GPU.
v3: Drop the need for ring to emit the 64bits fence, and just have
each ring emit the lower 32bits of the fence sequence. We
handle the wrap over 32bits in fence_process.
v4: Just a small optimization: Don't reread the last_seq value
if loop restarts, since we already know its value anyway.
Also start at zero not one for seq value and use pre instead
of post increment in emmit, otherwise wait_empty will deadlock.
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
Signed-off-by: Christian König <deathsimple@vodafone.de>
Signed-off-by: Dave Airlie <airlied@redhat.com>
This commit is contained in:
Jerome Glisse
Dave Airlie
parent
d6999bc7b5
commit
bb63556729
@ -100,28 +100,32 @@ extern int radeon_lockup_timeout;
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* Copy from radeon_drv.h so we don't have to include both and have conflicting
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* symbol;
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*/
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#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
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#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
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#define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */
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#define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2)
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/* RADEON_IB_POOL_SIZE must be a power of 2 */
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#define RADEON_IB_POOL_SIZE 16
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#define RADEON_DEBUGFS_MAX_COMPONENTS 32
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#define RADEONFB_CONN_LIMIT 4
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#define RADEON_BIOS_NUM_SCRATCH 8
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#define RADEON_IB_POOL_SIZE 16
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#define RADEON_DEBUGFS_MAX_COMPONENTS 32
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#define RADEONFB_CONN_LIMIT 4
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#define RADEON_BIOS_NUM_SCRATCH 8
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/* max number of rings */
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#define RADEON_NUM_RINGS 3
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#define RADEON_NUM_RINGS 3
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/* fence seq are set to this number when signaled */
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#define RADEON_FENCE_SIGNALED_SEQ 0LL
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#define RADEON_FENCE_NOTEMITED_SEQ (~0LL)
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/* internal ring indices */
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/* r1xx+ has gfx CP ring */
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#define RADEON_RING_TYPE_GFX_INDEX 0
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#define RADEON_RING_TYPE_GFX_INDEX 0
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/* cayman has 2 compute CP rings */
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#define CAYMAN_RING_TYPE_CP1_INDEX 1
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#define CAYMAN_RING_TYPE_CP2_INDEX 2
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#define CAYMAN_RING_TYPE_CP1_INDEX 1
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#define CAYMAN_RING_TYPE_CP2_INDEX 2
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/* hardcode those limit for now */
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#define RADEON_VA_RESERVED_SIZE (8 << 20)
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#define RADEON_IB_VM_MAX_SIZE (64 << 10)
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#define RADEON_VA_RESERVED_SIZE (8 << 20)
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#define RADEON_IB_VM_MAX_SIZE (64 << 10)
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/*
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* Errata workarounds.
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@ -254,8 +258,9 @@ struct radeon_fence_driver {
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uint32_t scratch_reg;
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uint64_t gpu_addr;
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volatile uint32_t *cpu_addr;
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atomic_t seq;
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uint32_t last_seq;
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/* seq is protected by ring emission lock */
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uint64_t seq;
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atomic64_t last_seq;
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unsigned long last_activity;
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wait_queue_head_t queue;
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struct list_head emitted;
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@ -268,11 +273,9 @@ struct radeon_fence {
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struct kref kref;
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struct list_head list;
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/* protected by radeon_fence.lock */
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uint32_t seq;
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bool emitted;
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bool signaled;
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uint64_t seq;
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/* RB, DMA, etc. */
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int ring;
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unsigned ring;
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struct radeon_semaphore *semaphore;
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};
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@ -66,14 +66,14 @@ int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence)
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unsigned long irq_flags;
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write_lock_irqsave(&rdev->fence_lock, irq_flags);
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if (fence->emitted) {
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if (fence->seq && fence->seq < RADEON_FENCE_NOTEMITED_SEQ) {
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write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
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return 0;
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}
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fence->seq = atomic_add_return(1, &rdev->fence_drv[fence->ring].seq);
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/* we are protected by the ring emission mutex */
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fence->seq = ++rdev->fence_drv[fence->ring].seq;
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radeon_fence_ring_emit(rdev, fence->ring, fence);
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trace_radeon_fence_emit(rdev->ddev, fence->seq);
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fence->emitted = true;
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/* are we the first fence on a previusly idle ring? */
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if (list_empty(&rdev->fence_drv[fence->ring].emitted)) {
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rdev->fence_drv[fence->ring].last_activity = jiffies;
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@ -87,14 +87,60 @@ static bool radeon_fence_poll_locked(struct radeon_device *rdev, int ring)
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{
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struct radeon_fence *fence;
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struct list_head *i, *n;
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uint32_t seq;
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uint64_t seq, last_seq;
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unsigned count_loop = 0;
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bool wake = false;
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seq = radeon_fence_read(rdev, ring);
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if (seq == rdev->fence_drv[ring].last_seq)
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return false;
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/* Note there is a scenario here for an infinite loop but it's
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* very unlikely to happen. For it to happen, the current polling
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* process need to be interrupted by another process and another
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* process needs to update the last_seq btw the atomic read and
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* xchg of the current process.
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*
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* More over for this to go in infinite loop there need to be
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* continuously new fence signaled ie radeon_fence_read needs
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* to return a different value each time for both the currently
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* polling process and the other process that xchg the last_seq
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* btw atomic read and xchg of the current process. And the
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* value the other process set as last seq must be higher than
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* the seq value we just read. Which means that current process
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* need to be interrupted after radeon_fence_read and before
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* atomic xchg.
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*
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* To be even more safe we count the number of time we loop and
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* we bail after 10 loop just accepting the fact that we might
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* have temporarly set the last_seq not to the true real last
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* seq but to an older one.
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*/
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last_seq = atomic64_read(&rdev->fence_drv[ring].last_seq);
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do {
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seq = radeon_fence_read(rdev, ring);
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seq |= last_seq & 0xffffffff00000000LL;
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if (seq < last_seq) {
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seq += 0x100000000LL;
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}
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rdev->fence_drv[ring].last_seq = seq;
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if (!wake && seq == last_seq) {
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return false;
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}
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/* If we loop over we don't want to return without
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* checking if a fence is signaled as it means that the
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* seq we just read is different from the previous on.
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*/
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wake = true;
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if ((count_loop++) > 10) {
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/* We looped over too many time leave with the
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* fact that we might have set an older fence
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* seq then the current real last seq as signaled
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* by the hw.
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*/
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break;
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}
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last_seq = seq;
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} while (atomic64_xchg(&rdev->fence_drv[ring].last_seq, seq) > seq);
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/* reset wake to false */
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wake = false;
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rdev->fence_drv[ring].last_activity = jiffies;
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n = NULL;
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@ -112,7 +158,7 @@ static bool radeon_fence_poll_locked(struct radeon_device *rdev, int ring)
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n = i->prev;
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list_move_tail(i, &rdev->fence_drv[ring].signaled);
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fence = list_entry(i, struct radeon_fence, list);
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fence->signaled = true;
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fence->seq = RADEON_FENCE_SIGNALED_SEQ;
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i = n;
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} while (i != &rdev->fence_drv[ring].emitted);
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wake = true;
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@ -128,7 +174,7 @@ static void radeon_fence_destroy(struct kref *kref)
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fence = container_of(kref, struct radeon_fence, kref);
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write_lock_irqsave(&fence->rdev->fence_lock, irq_flags);
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list_del(&fence->list);
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fence->emitted = false;
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fence->seq = RADEON_FENCE_NOTEMITED_SEQ;
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write_unlock_irqrestore(&fence->rdev->fence_lock, irq_flags);
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if (fence->semaphore)
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radeon_semaphore_free(fence->rdev, fence->semaphore);
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@ -145,9 +191,7 @@ int radeon_fence_create(struct radeon_device *rdev,
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}
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kref_init(&((*fence)->kref));
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(*fence)->rdev = rdev;
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(*fence)->emitted = false;
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(*fence)->signaled = false;
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(*fence)->seq = 0;
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(*fence)->seq = RADEON_FENCE_NOTEMITED_SEQ;
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(*fence)->ring = ring;
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(*fence)->semaphore = NULL;
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INIT_LIST_HEAD(&(*fence)->list);
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@ -163,18 +207,18 @@ bool radeon_fence_signaled(struct radeon_fence *fence)
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return true;
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write_lock_irqsave(&fence->rdev->fence_lock, irq_flags);
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signaled = fence->signaled;
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signaled = (fence->seq == RADEON_FENCE_SIGNALED_SEQ);
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/* if we are shuting down report all fence as signaled */
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if (fence->rdev->shutdown) {
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signaled = true;
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}
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if (!fence->emitted) {
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if (fence->seq == RADEON_FENCE_NOTEMITED_SEQ) {
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WARN(1, "Querying an unemitted fence : %p !\n", fence);
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signaled = true;
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}
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if (!signaled) {
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radeon_fence_poll_locked(fence->rdev, fence->ring);
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signaled = fence->signaled;
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signaled = (fence->seq == RADEON_FENCE_SIGNALED_SEQ);
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}
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write_unlock_irqrestore(&fence->rdev->fence_lock, irq_flags);
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return signaled;
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@ -183,8 +227,8 @@ bool radeon_fence_signaled(struct radeon_fence *fence)
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int radeon_fence_wait(struct radeon_fence *fence, bool intr)
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{
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struct radeon_device *rdev;
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unsigned long irq_flags, timeout;
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u32 seq;
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unsigned long irq_flags, timeout, last_activity;
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uint64_t seq;
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int i, r;
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bool signaled;
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@ -207,7 +251,9 @@ int radeon_fence_wait(struct radeon_fence *fence, bool intr)
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timeout = 1;
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}
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/* save current sequence value used to check for GPU lockups */
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seq = rdev->fence_drv[fence->ring].last_seq;
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seq = atomic64_read(&rdev->fence_drv[fence->ring].last_seq);
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/* Save current last activity valuee, used to check for GPU lockups */
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last_activity = rdev->fence_drv[fence->ring].last_activity;
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read_unlock_irqrestore(&rdev->fence_lock, irq_flags);
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trace_radeon_fence_wait_begin(rdev->ddev, seq);
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@ -235,24 +281,23 @@ int radeon_fence_wait(struct radeon_fence *fence, bool intr)
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}
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write_lock_irqsave(&rdev->fence_lock, irq_flags);
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/* check if sequence value has changed since last_activity */
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if (seq != rdev->fence_drv[fence->ring].last_seq) {
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/* test if somebody else has already decided that this is a lockup */
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if (last_activity != rdev->fence_drv[fence->ring].last_activity) {
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write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
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continue;
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}
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/* change sequence value on all rings, so nobody else things there is a lockup */
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for (i = 0; i < RADEON_NUM_RINGS; ++i)
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rdev->fence_drv[i].last_seq -= 0x10000;
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rdev->fence_drv[fence->ring].last_activity = jiffies;
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write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
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if (radeon_ring_is_lockup(rdev, fence->ring, &rdev->ring[fence->ring])) {
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/* good news we believe it's a lockup */
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printk(KERN_WARNING "GPU lockup (waiting for 0x%08X last fence id 0x%08X)\n",
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fence->seq, seq);
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dev_warn(rdev->dev, "GPU lockup (waiting for 0x%016llx last fence id 0x%016llx)\n",
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fence->seq, seq);
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/* change last activity so nobody else think there is a lockup */
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for (i = 0; i < RADEON_NUM_RINGS; ++i) {
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rdev->fence_drv[i].last_activity = jiffies;
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}
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/* mark the ring as not ready any more */
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rdev->ring[fence->ring].ready = false;
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@ -387,9 +432,9 @@ int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring)
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}
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rdev->fence_drv[ring].cpu_addr = &rdev->wb.wb[index/4];
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rdev->fence_drv[ring].gpu_addr = rdev->wb.gpu_addr + index;
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radeon_fence_write(rdev, atomic_read(&rdev->fence_drv[ring].seq), ring);
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radeon_fence_write(rdev, rdev->fence_drv[ring].seq, ring);
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rdev->fence_drv[ring].initialized = true;
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DRM_INFO("fence driver on ring %d use gpu addr 0x%08Lx and cpu addr 0x%p\n",
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DRM_INFO("fence driver on ring %d use gpu addr 0x%016llx and cpu addr 0x%p\n",
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ring, rdev->fence_drv[ring].gpu_addr, rdev->fence_drv[ring].cpu_addr);
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write_unlock_irqrestore(&rdev->fence_lock, irq_flags);
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return 0;
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@ -400,7 +445,8 @@ static void radeon_fence_driver_init_ring(struct radeon_device *rdev, int ring)
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rdev->fence_drv[ring].scratch_reg = -1;
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rdev->fence_drv[ring].cpu_addr = NULL;
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rdev->fence_drv[ring].gpu_addr = 0;
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atomic_set(&rdev->fence_drv[ring].seq, 0);
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rdev->fence_drv[ring].seq = 0;
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atomic64_set(&rdev->fence_drv[ring].last_seq, 0);
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INIT_LIST_HEAD(&rdev->fence_drv[ring].emitted);
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INIT_LIST_HEAD(&rdev->fence_drv[ring].signaled);
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init_waitqueue_head(&rdev->fence_drv[ring].queue);
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@ -458,12 +504,12 @@ static int radeon_debugfs_fence_info(struct seq_file *m, void *data)
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continue;
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seq_printf(m, "--- ring %d ---\n", i);
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seq_printf(m, "Last signaled fence 0x%08X\n",
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radeon_fence_read(rdev, i));
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seq_printf(m, "Last signaled fence 0x%016lx\n",
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atomic64_read(&rdev->fence_drv[i].last_seq));
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if (!list_empty(&rdev->fence_drv[i].emitted)) {
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fence = list_entry(rdev->fence_drv[i].emitted.prev,
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struct radeon_fence, list);
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seq_printf(m, "Last emitted fence %p with 0x%08X\n",
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seq_printf(m, "Last emitted fence %p with 0x%016llx\n",
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fence, fence->seq);
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}
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}
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@ -82,7 +82,7 @@ bool radeon_ib_try_free(struct radeon_device *rdev, struct radeon_ib *ib)
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bool done = false;
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/* only free ib which have been emited */
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if (ib->fence && ib->fence->emitted) {
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if (ib->fence && ib->fence->seq < RADEON_FENCE_NOTEMITED_SEQ) {
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if (radeon_fence_signaled(ib->fence)) {
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radeon_fence_unref(&ib->fence);
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radeon_sa_bo_free(rdev, &ib->sa_bo);
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@ -149,8 +149,9 @@ retry:
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/* this should be rare event, ie all ib scheduled none signaled yet.
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*/
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for (i = 0; i < RADEON_IB_POOL_SIZE; i++) {
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if (rdev->ib_pool.ibs[idx].fence && rdev->ib_pool.ibs[idx].fence->emitted) {
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r = radeon_fence_wait(rdev->ib_pool.ibs[idx].fence, false);
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struct radeon_fence *fence = rdev->ib_pool.ibs[idx].fence;
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if (fence && fence->seq < RADEON_FENCE_NOTEMITED_SEQ) {
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r = radeon_fence_wait(fence, false);
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if (!r) {
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goto retry;
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}
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@ -173,7 +174,7 @@ void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib)
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return;
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}
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radeon_mutex_lock(&rdev->ib_pool.mutex);
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if (tmp->fence && !tmp->fence->emitted) {
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if (tmp->fence && tmp->fence->seq == RADEON_FENCE_NOTEMITED_SEQ) {
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radeon_sa_bo_free(rdev, &tmp->sa_bo);
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radeon_fence_unref(&tmp->fence);
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}
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