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[ARM] 5258/1: [AT91] PWM controller initialization
Add platform_devices and configuration of the PWM controller found on Atmel AT91CAP9, SAM9263 and SAM9RL processors. SAM9263 support by Sedji Gaouaou. Signed-off-by: Andrew Victor <linux@maxim.org.za> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
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@ -141,8 +141,8 @@ static struct clk tcb_clk = {
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.pmc_mask = 1 << AT91CAP9_ID_TCB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwmc_clk = {
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.name = "pwmc_clk",
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91CAP9_ID_PWMC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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@ -207,7 +207,7 @@ static struct clk *periph_clocks[] __initdata = {
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&ssc1_clk,
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&ac97_clk,
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&tcb_clk,
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&pwmc_clk,
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&pwm_clk,
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&macb_clk,
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&aestdes_clk,
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&adc_clk,
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@ -718,6 +718,60 @@ static void __init at91_add_device_watchdog(void) {}
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#endif
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/* --------------------------------------------------------------------
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* PWM
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* --------------------------------------------------------------------*/
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#if defined(CONFIG_ATMEL_PWM)
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static u32 pwm_mask;
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static struct resource pwm_resources[] = {
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[0] = {
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.start = AT91CAP9_BASE_PWMC,
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.end = AT91CAP9_BASE_PWMC + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AT91CAP9_ID_PWMC,
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.end = AT91CAP9_ID_PWMC,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device at91cap9_pwm0_device = {
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.name = "atmel_pwm",
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.id = -1,
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.dev = {
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.platform_data = &pwm_mask,
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},
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.resource = pwm_resources,
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.num_resources = ARRAY_SIZE(pwm_resources),
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};
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void __init at91_add_device_pwm(u32 mask)
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{
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if (mask & (1 << AT91_PWM0))
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at91_set_A_periph(AT91_PIN_PB19, 1); /* enable PWM0 */
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if (mask & (1 << AT91_PWM1))
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at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
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if (mask & (1 << AT91_PWM2))
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at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
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if (mask & (1 << AT91_PWM3))
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at91_set_B_periph(AT91_PIN_PA11, 1); /* enable PWM3 */
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pwm_mask = mask;
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platform_device_register(&at91cap9_pwm0_device);
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}
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#else
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void __init at91_add_device_pwm(u32 mask) {}
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#endif
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/* --------------------------------------------------------------------
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* AC97
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* -------------------------------------------------------------------- */
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@ -129,8 +129,8 @@ static struct clk tcb_clk = {
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.pmc_mask = 1 << AT91SAM9263_ID_TCB,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwmc_clk = {
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.name = "pwmc_clk",
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91SAM9263_ID_PWMC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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@ -187,7 +187,7 @@ static struct clk *periph_clocks[] __initdata = {
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&ssc1_clk,
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&ac97_clk,
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&tcb_clk,
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&pwmc_clk,
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&pwm_clk,
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&macb_clk,
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&twodge_clk,
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&udc_clk,
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@ -885,6 +885,59 @@ static void __init at91_add_device_watchdog(void) {}
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#endif
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/* --------------------------------------------------------------------
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* PWM
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* --------------------------------------------------------------------*/
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#if defined(CONFIG_ATMEL_PWM)
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static u32 pwm_mask;
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static struct resource pwm_resources[] = {
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[0] = {
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.start = AT91SAM9263_BASE_PWMC,
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.end = AT91SAM9263_BASE_PWMC + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AT91SAM9263_ID_PWMC,
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.end = AT91SAM9263_ID_PWMC,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device at91sam9263_pwm0_device = {
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.name = "atmel_pwm",
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.id = -1,
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.dev = {
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.platform_data = &pwm_mask,
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},
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.resource = pwm_resources,
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.num_resources = ARRAY_SIZE(pwm_resources),
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};
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void __init at91_add_device_pwm(u32 mask)
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{
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if (mask & (1 << AT91_PWM0))
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at91_set_B_periph(AT91_PIN_PB7, 1); /* enable PWM0 */
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if (mask & (1 << AT91_PWM1))
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at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM1 */
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if (mask & (1 << AT91_PWM2))
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at91_set_B_periph(AT91_PIN_PC29, 1); /* enable PWM2 */
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if (mask & (1 << AT91_PWM3))
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at91_set_B_periph(AT91_PIN_PB29, 1); /* enable PWM3 */
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pwm_mask = mask;
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platform_device_register(&at91sam9263_pwm0_device);
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}
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#else
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void __init at91_add_device_pwm(u32 mask) {}
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#endif
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/* --------------------------------------------------------------------
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* SSC -- Synchronous Serial Controller
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* -------------------------------------------------------------------- */
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@ -131,8 +131,8 @@ static struct clk tc2_clk = {
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.pmc_mask = 1 << AT91SAM9RL_ID_TC2,
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.type = CLK_TYPE_PERIPHERAL,
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};
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static struct clk pwmc_clk = {
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.name = "pwmc_clk",
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static struct clk pwm_clk = {
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.name = "pwm_clk",
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.pmc_mask = 1 << AT91SAM9RL_ID_PWMC,
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.type = CLK_TYPE_PERIPHERAL,
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};
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@ -180,7 +180,7 @@ static struct clk *periph_clocks[] __initdata = {
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&tc0_clk,
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&tc1_clk,
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&tc2_clk,
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&pwmc_clk,
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&pwm_clk,
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&tsc_clk,
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&dma_clk,
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&udphs_clk,
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@ -591,6 +591,59 @@ static void __init at91_add_device_watchdog(void) {}
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#endif
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/* --------------------------------------------------------------------
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* PWM
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* --------------------------------------------------------------------*/
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#if defined(CONFIG_ATMEL_PWM)
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static u32 pwm_mask;
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static struct resource pwm_resources[] = {
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[0] = {
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.start = AT91SAM9RL_BASE_PWMC,
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.end = AT91SAM9RL_BASE_PWMC + SZ_16K - 1,
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.flags = IORESOURCE_MEM,
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},
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[1] = {
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.start = AT91SAM9RL_ID_PWMC,
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.end = AT91SAM9RL_ID_PWMC,
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct platform_device at91sam9rl_pwm0_device = {
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.name = "atmel_pwm",
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.id = -1,
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.dev = {
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.platform_data = &pwm_mask,
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},
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.resource = pwm_resources,
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.num_resources = ARRAY_SIZE(pwm_resources),
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};
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void __init at91_add_device_pwm(u32 mask)
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{
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if (mask & (1 << AT91_PWM0))
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at91_set_B_periph(AT91_PIN_PB8, 1); /* enable PWM0 */
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if (mask & (1 << AT91_PWM1))
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at91_set_B_periph(AT91_PIN_PB9, 1); /* enable PWM1 */
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if (mask & (1 << AT91_PWM2))
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at91_set_B_periph(AT91_PIN_PD5, 1); /* enable PWM2 */
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if (mask & (1 << AT91_PWM3))
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at91_set_B_periph(AT91_PIN_PD8, 1); /* enable PWM3 */
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pwm_mask = mask;
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platform_device_register(&at91sam9rl_pwm0_device);
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}
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#else
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void __init at91_add_device_pwm(u32 mask) {}
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#endif
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/* --------------------------------------------------------------------
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* SSC -- Synchronous Serial Controller
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* -------------------------------------------------------------------- */
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@ -132,6 +132,16 @@ struct atmel_uart_data {
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};
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extern void __init at91_add_device_serial(void);
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/*
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* PWM
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*/
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#define AT91_PWM0 0
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#define AT91_PWM1 1
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#define AT91_PWM2 2
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#define AT91_PWM3 3
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extern void __init at91_add_device_pwm(u32 mask);
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/*
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* SSC -- accessed through ssc_request(id). Drivers don't bind to SSC
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* platform devices. Their SSC ID is part of their configuration data,
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