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Merge remote-tracking branches 'asoc/topic/hdac_hdmi', 'asoc/topic/hisilicon', 'asoc/topic/iio' and 'asoc/topic/max98373' into asoc-next

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Mark Brown 2018-01-12 12:29:11 +00:00
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16
Documentation/ABI/testing/sysfs-bus-iio-dfsdm-adc-stm32 Normal file
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@ -0,0 +1,16 @@
What: /sys/bus/iio/devices/iio:deviceX/in_voltage_spi_clk_freq
KernelVersion: 4.14
Contact: arnaud.pouliquen@st.com
Description:
For audio purpose only.
Used by audio driver to set/get the spi input frequency.
This is mandatory if DFSDM is slave on SPI bus, to
provide information on the SPI clock frequency during runtime
Notice that the SPI frequency should be a multiple of sample
frequency to ensure the precision.
if DFSDM input is SPI master
Reading SPI clkout frequency,
error on writing
If DFSDM input is SPI Slave:
Reading returns value previously set.
Writing value before starting conversions.

13
Documentation/devicetree/bindings/iio/adc/sigma-delta-modulator.txt Normal file
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@ -0,0 +1,13 @@
Device-Tree bindings for sigma delta modulator
Required properties:
- compatible: should be "ads1201", "sd-modulator". "sd-modulator" can be use
as a generic SD modulator if modulator not specified in compatible list.
- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers".
Example node:
ads1202: adc@0 {
compatible = "sd-modulator";
#io-channel-cells = <1>;
};

128
Documentation/devicetree/bindings/iio/adc/st,stm32-dfsdm-adc.txt Normal file
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@ -0,0 +1,128 @@
STMicroelectronics STM32 DFSDM ADC device driver
STM32 DFSDM ADC is a sigma delta analog-to-digital converter dedicated to
interface external sigma delta modulators to STM32 micro controllers.
It is mainly targeted for:
- Sigma delta modulators (motor control, metering...)
- PDM microphones (audio digital microphone)
It features up to 8 serial digital interfaces (SPI or Manchester) and
up to 4 filters on stm32h7.
Each child node match with a filter instance.
Contents of a STM32 DFSDM root node:
------------------------------------
Required properties:
- compatible: Should be "st,stm32h7-dfsdm".
- reg: Offset and length of the DFSDM block register set.
- clocks: IP and serial interfaces clocking. Should be set according
to rcc clock ID and "clock-names".
- clock-names: Input clock name "dfsdm" must be defined,
"audio" is optional. If defined CLKOUT is based on the audio
clock, else "dfsdm" is used.
- #interrupt-cells = <1>;
- #address-cells = <1>;
- #size-cells = <0>;
Optional properties:
- spi-max-frequency: Requested only for SPI master mode.
SPI clock OUT frequency (Hz). This clock must be set according
to "clock" property. Frequency must be a multiple of the rcc
clock frequency. If not, SPI CLKOUT frequency will not be
accurate.
Contents of a STM32 DFSDM child nodes:
--------------------------------------
Required properties:
- compatible: Must be:
"st,stm32-dfsdm-adc" for sigma delta ADCs
"st,stm32-dfsdm-dmic" for audio digital microphone.
- reg: Specifies the DFSDM filter instance used.
- interrupts: IRQ lines connected to each DFSDM filter instance.
- st,adc-channels: List of single-ended channels muxed for this ADC.
valid values:
"st,stm32h7-dfsdm" compatibility: 0 to 7.
- st,adc-channel-names: List of single-ended channel names.
- st,filter-order: SinC filter order from 0 to 5.
0: FastSinC
[1-5]: order 1 to 5.
For audio purpose it is recommended to use order 3 to 5.
- #io-channel-cells = <1>: See the IIO bindings section "IIO consumers".
Required properties for "st,stm32-dfsdm-adc" compatibility:
- io-channels: From common IIO binding. Used to pipe external sigma delta
modulator or internal ADC output to DFSDM channel.
This is not required for "st,stm32-dfsdm-pdm" compatibility as
PDM microphone is binded in Audio DT node.
Required properties for "st,stm32-dfsdm-pdm" compatibility:
- #sound-dai-cells: Must be set to 0.
- dma: DMA controller phandle and DMA request line associated to the
filter instance (specified by the field "reg")
- dma-names: Must be "rx"
Optional properties:
- st,adc-channel-types: Single-ended channel input type.
- "SPI_R": SPI with data on rising edge (default)
- "SPI_F": SPI with data on falling edge
- "MANCH_R": manchester codec, rising edge = logic 0
- "MANCH_F": manchester codec, falling edge = logic 1
- st,adc-channel-clk-src: Conversion clock source.
- "CLKIN": external SPI clock (CLKIN x)
- "CLKOUT": internal SPI clock (CLKOUT) (default)
- "CLKOUT_F": internal SPI clock divided by 2 (falling edge).
- "CLKOUT_R": internal SPI clock divided by 2 (rising edge).
- st,adc-alt-channel: Must be defined if two sigma delta modulator are
connected on same SPI input.
If not set, channel n is connected to SPI input n.
If set, channel n is connected to SPI input n + 1.
- st,filter0-sync: Set to 1 to synchronize with DFSDM filter instance 0.
Used for multi microphones synchronization.
Example of a sigma delta adc connected on DFSDM SPI port 0
and a pdm microphone connected on DFSDM SPI port 1:
ads1202: simple_sd_adc@0 {
compatible = "ads1202";
#io-channel-cells = <1>;
};
dfsdm: dfsdm@40017000 {
compatible = "st,stm32h7-dfsdm";
reg = <0x40017000 0x400>;
clocks = <&rcc DFSDM1_CK>;
clock-names = "dfsdm";
#interrupt-cells = <1>;
#address-cells = <1>;
#size-cells = <0>;
dfsdm_adc0: filter@0 {
compatible = "st,stm32-dfsdm-adc";
#io-channel-cells = <1>;
reg = <0>;
interrupts = <110>;
st,adc-channels = <0>;
st,adc-channel-names = "sd_adc0";
st,adc-channel-types = "SPI_F";
st,adc-channel-clk-src = "CLKOUT";
io-channels = <&ads1202 0>;
st,filter-order = <3>;
};
dfsdm_pdm1: filter@1 {
compatible = "st,stm32-dfsdm-dmic";
reg = <1>;
interrupts = <111>;
dmas = <&dmamux1 102 0x400 0x00>;
dma-names = "rx";
st,adc-channels = <1>;
st,adc-channel-names = "dmic1";
st,adc-channel-types = "SPI_R";
st,adc-channel-clk-src = "CLKOUT";
st,filter-order = <5>;
};
}

40
Documentation/devicetree/bindings/sound/max98373.txt Normal file
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@ -0,0 +1,40 @@
Maxim Integrated MAX98373 Speaker Amplifier
This device supports I2C.
Required properties:
- compatible : "maxim,max98373"
- reg : the I2C address of the device.
Optional properties:
- maxim,vmon-slot-no : slot number used to send voltage information
or in inteleave mode this will be used as
interleave slot.
slot range : 0 ~ 15, Default : 0
- maxim,imon-slot-no : slot number used to send current information
slot range : 0 ~ 15, Default : 0
- maxim,spkfb-slot-no : slot number used to send speaker feedback information
slot range : 0 ~ 15, Default : 0
- maxim,interleave-mode : For cases where a single combined channel
for the I/V sense data is not sufficient, the device can also be configured
to share a single data output channel on alternating frames.
In this configuration, the current and voltage data will be frame interleaved
on a single output channel.
Boolean, define to enable the interleave mode, Default : false
Example:
codec: max98373@31 {
compatible = "maxim,max98373";
reg = <0x31>;
maxim,vmon-slot-no = <0>;
maxim,imon-slot-no = <1>;
maxim,spkfb-slot-no = <2>;
maxim,interleave-mode;
};

51
Documentation/driver-api/iio/hw-consumer.rst Normal file
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@ -0,0 +1,51 @@
===========
HW consumer
===========
An IIO device can be directly connected to another device in hardware. in this
case the buffers between IIO provider and IIO consumer are handled by hardware.
The Industrial I/O HW consumer offers a way to bond these IIO devices without
software buffer for data. The implementation can be found under
:file:`drivers/iio/buffer/hw-consumer.c`
* struct :c:type:`iio_hw_consumer` — Hardware consumer structure
* :c:func:`iio_hw_consumer_alloc` — Allocate IIO hardware consumer
* :c:func:`iio_hw_consumer_free` — Free IIO hardware consumer
* :c:func:`iio_hw_consumer_enable` — Enable IIO hardware consumer
* :c:func:`iio_hw_consumer_disable` — Disable IIO hardware consumer
HW consumer setup
=================
As standard IIO device the implementation is based on IIO provider/consumer.
A typical IIO HW consumer setup looks like this::
static struct iio_hw_consumer *hwc;
static const struct iio_info adc_info = {
.read_raw = adc_read_raw,
};
static int adc_read_raw(struct iio_dev *indio_dev,
struct iio_chan_spec const *chan, int *val,
int *val2, long mask)
{
ret = iio_hw_consumer_enable(hwc);
/* Acquire data */
ret = iio_hw_consumer_disable(hwc);
}
static int adc_probe(struct platform_device *pdev)
{
hwc = devm_iio_hw_consumer_alloc(&iio->dev);
}
More details
============
.. kernel-doc:: include/linux/iio/hw-consumer.h
.. kernel-doc:: drivers/iio/buffer/industrialio-hw-consumer.c
:export:

1
Documentation/driver-api/iio/index.rst
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@ -15,3 +15,4 @@ Contents:
buffers buffers
triggers triggers
triggered-buffers triggered-buffers
hw-consumer

37
drivers/iio/adc/Kconfig
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@ -629,6 +629,18 @@ config SPEAR_ADC
To compile this driver as a module, choose M here: the To compile this driver as a module, choose M here: the
module will be called spear_adc. module will be called spear_adc.
config SD_ADC_MODULATOR
tristate "Generic sigma delta modulator"
depends on OF
select IIO_BUFFER
select IIO_TRIGGERED_BUFFER
help
Select this option to enables sigma delta modulator. This driver can
support generic sigma delta modulators.
This driver can also be built as a module. If so, the module
will be called sd_adc_modulator.
config STM32_ADC_CORE config STM32_ADC_CORE
tristate "STMicroelectronics STM32 adc core" tristate "STMicroelectronics STM32 adc core"
depends on ARCH_STM32 || COMPILE_TEST depends on ARCH_STM32 || COMPILE_TEST
@ -656,6 +668,31 @@ config STM32_ADC
This driver can also be built as a module. If so, the module This driver can also be built as a module. If so, the module
will be called stm32-adc. will be called stm32-adc.
config STM32_DFSDM_CORE
tristate "STMicroelectronics STM32 DFSDM core"
depends on (ARCH_STM32 && OF) || COMPILE_TEST
select REGMAP
select REGMAP_MMIO
help
Select this option to enable the driver for STMicroelectronics
STM32 digital filter for sigma delta converter.
This driver can also be built as a module. If so, the module
will be called stm32-dfsdm-core.
config STM32_DFSDM_ADC
tristate "STMicroelectronics STM32 dfsdm adc"
depends on (ARCH_STM32 && OF) || COMPILE_TEST
select STM32_DFSDM_CORE
select REGMAP_MMIO
select IIO_BUFFER_HW_CONSUMER
help
Select this option to support ADCSigma delta modulator for
STMicroelectronics STM32 digital filter for sigma delta converter.
This driver can also be built as a module. If so, the module
will be called stm32-dfsdm-adc.
config STX104 config STX104
tristate "Apex Embedded Systems STX104 driver" tristate "Apex Embedded Systems STX104 driver"
depends on PC104 && X86 && ISA_BUS_API depends on PC104 && X86 && ISA_BUS_API

3
drivers/iio/adc/Makefile
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@ -64,6 +64,8 @@ obj-$(CONFIG_STX104) += stx104.o
obj-$(CONFIG_SUN4I_GPADC) += sun4i-gpadc-iio.o obj-$(CONFIG_SUN4I_GPADC) += sun4i-gpadc-iio.o
obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o obj-$(CONFIG_STM32_ADC_CORE) += stm32-adc-core.o
obj-$(CONFIG_STM32_ADC) += stm32-adc.o obj-$(CONFIG_STM32_ADC) += stm32-adc.o
obj-$(CONFIG_STM32_DFSDM_CORE) += stm32-dfsdm-core.o
obj-$(CONFIG_STM32_DFSDM_ADC) += stm32-dfsdm-adc.o
obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o obj-$(CONFIG_TI_ADC081C) += ti-adc081c.o
obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o obj-$(CONFIG_TI_ADC0832) += ti-adc0832.o
obj-$(CONFIG_TI_ADC084S021) += ti-adc084s021.o obj-$(CONFIG_TI_ADC084S021) += ti-adc084s021.o
@ -82,3 +84,4 @@ obj-$(CONFIG_VF610_ADC) += vf610_adc.o
obj-$(CONFIG_VIPERBOARD_ADC) += viperboard_adc.o obj-$(CONFIG_VIPERBOARD_ADC) += viperboard_adc.o
xilinx-xadc-y := xilinx-xadc-core.o xilinx-xadc-events.o xilinx-xadc-y := xilinx-xadc-core.o xilinx-xadc-events.o
obj-$(CONFIG_XILINX_XADC) += xilinx-xadc.o obj-$(CONFIG_XILINX_XADC) += xilinx-xadc.o
obj-$(CONFIG_SD_ADC_MODULATOR) += sd_adc_modulator.o

68
drivers/iio/adc/sd_adc_modulator.c Normal file
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@ -0,0 +1,68 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Generic sigma delta modulator driver
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author: Arnaud Pouliquen <arnaud.pouliquen@st.com>.
*/
#include <linux/iio/iio.h>
#include <linux/iio/triggered_buffer.h>
#include <linux/module.h>
#include <linux/of_device.h>
static const struct iio_info iio_sd_mod_iio_info;
static const struct iio_chan_spec iio_sd_mod_ch = {
.type = IIO_VOLTAGE,
.indexed = 1,
.scan_type = {
.sign = 'u',
.realbits = 1,
.shift = 0,
},
};
static int iio_sd_mod_probe(struct platform_device *pdev)
{
struct device *dev = &pdev->dev;
struct iio_dev *iio;
iio = devm_iio_device_alloc(dev, 0);
if (!iio)
return -ENOMEM;
iio->dev.parent = dev;
iio->dev.of_node = dev->of_node;
iio->name = dev_name(dev);
iio->info = &iio_sd_mod_iio_info;
iio->modes = INDIO_BUFFER_HARDWARE;
iio->num_channels = 1;
iio->channels = &iio_sd_mod_ch;
platform_set_drvdata(pdev, iio);
return devm_iio_device_register(&pdev->dev, iio);
}
static const struct of_device_id sd_adc_of_match[] = {
{ .compatible = "sd-modulator" },
{ .compatible = "ads1201" },
{ }
};
MODULE_DEVICE_TABLE(of, sd_adc_of_match);
static struct platform_driver iio_sd_mod_adc = {
.driver = {
.name = "iio_sd_adc_mod",
.of_match_table = of_match_ptr(sd_adc_of_match),
},
.probe = iio_sd_mod_probe,
};
module_platform_driver(iio_sd_mod_adc);
MODULE_DESCRIPTION("Basic sigma delta modulator");
MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
MODULE_LICENSE("GPL v2");

1216
drivers/iio/adc/stm32-dfsdm-adc.c Normal file
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308
drivers/iio/adc/stm32-dfsdm-core.c Normal file
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@ -0,0 +1,308 @@
// SPDX-License-Identifier: GPL-2.0
/*
* This file is part the core part STM32 DFSDM driver
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com> for STMicroelectronics.
*/
#include <linux/clk.h>
#include <linux/iio/iio.h>
#include <linux/iio/sysfs.h>
#include <linux/interrupt.h>
#include <linux/module.h>
#include <linux/of_device.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include "stm32-dfsdm.h"
struct stm32_dfsdm_dev_data {
unsigned int num_filters;
unsigned int num_channels;
const struct regmap_config *regmap_cfg;
};
#define STM32H7_DFSDM_NUM_FILTERS 4
#define STM32H7_DFSDM_NUM_CHANNELS 8
static bool stm32_dfsdm_volatile_reg(struct device *dev, unsigned int reg)
{
if (reg < DFSDM_FILTER_BASE_ADR)
return false;
/*
* Mask is done on register to avoid to list registers of all
* filter instances.
*/
switch (reg & DFSDM_FILTER_REG_MASK) {
case DFSDM_CR1(0) & DFSDM_FILTER_REG_MASK:
case DFSDM_ISR(0) & DFSDM_FILTER_REG_MASK:
case DFSDM_JDATAR(0) & DFSDM_FILTER_REG_MASK:
case DFSDM_RDATAR(0) & DFSDM_FILTER_REG_MASK:
return true;
}
return false;
}
static const struct regmap_config stm32h7_dfsdm_regmap_cfg = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = sizeof(u32),
.max_register = 0x2B8,
.volatile_reg = stm32_dfsdm_volatile_reg,
.fast_io = true,
};
static const struct stm32_dfsdm_dev_data stm32h7_dfsdm_data = {
.num_filters = STM32H7_DFSDM_NUM_FILTERS,
.num_channels = STM32H7_DFSDM_NUM_CHANNELS,
.regmap_cfg = &stm32h7_dfsdm_regmap_cfg,
};
struct dfsdm_priv {
struct platform_device *pdev; /* platform device */
struct stm32_dfsdm dfsdm; /* common data exported for all instances */
unsigned int spi_clk_out_div; /* SPI clkout divider value */
atomic_t n_active_ch; /* number of current active channels */
struct clk *clk; /* DFSDM clock */
struct clk *aclk; /* audio clock */
};
/**
* stm32_dfsdm_start_dfsdm - start global dfsdm interface.
*
* Enable interface if n_active_ch is not null.
* @dfsdm: Handle used to retrieve dfsdm context.
*/
int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm)
{
struct dfsdm_priv *priv = container_of(dfsdm, struct dfsdm_priv, dfsdm);
struct device *dev = &priv->pdev->dev;
unsigned int clk_div = priv->spi_clk_out_div;
int ret;
if (atomic_inc_return(&priv->n_active_ch) == 1) {
ret = clk_prepare_enable(priv->clk);
if (ret < 0) {
dev_err(dev, "Failed to start clock\n");
goto error_ret;
}
if (priv->aclk) {
ret = clk_prepare_enable(priv->aclk);
if (ret < 0) {
dev_err(dev, "Failed to start audio clock\n");
goto disable_clk;
}
}
/* Output the SPI CLKOUT (if clk_div == 0 clock if OFF) */
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_CKOUTDIV_MASK,
DFSDM_CHCFGR1_CKOUTDIV(clk_div));
if (ret < 0)
goto disable_aclk;
/* Global enable of DFSDM interface */
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_DFSDMEN_MASK,
DFSDM_CHCFGR1_DFSDMEN(1));
if (ret < 0)
goto disable_aclk;
}
dev_dbg(dev, "%s: n_active_ch %d\n", __func__,
atomic_read(&priv->n_active_ch));
return 0;
disable_aclk:
clk_disable_unprepare(priv->aclk);
disable_clk:
clk_disable_unprepare(priv->clk);
error_ret:
atomic_dec(&priv->n_active_ch);
return ret;
}
EXPORT_SYMBOL_GPL(stm32_dfsdm_start_dfsdm);
/**
* stm32_dfsdm_stop_dfsdm - stop global DFSDM interface.
*
* Disable interface if n_active_ch is null
* @dfsdm: Handle used to retrieve dfsdm context.
*/
int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm)
{
struct dfsdm_priv *priv = container_of(dfsdm, struct dfsdm_priv, dfsdm);
int ret;
if (atomic_dec_and_test(&priv->n_active_ch)) {
/* Global disable of DFSDM interface */
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_DFSDMEN_MASK,
DFSDM_CHCFGR1_DFSDMEN(0));
if (ret < 0)
return ret;
/* Stop SPI CLKOUT */
ret = regmap_update_bits(dfsdm->regmap, DFSDM_CHCFGR1(0),
DFSDM_CHCFGR1_CKOUTDIV_MASK,
DFSDM_CHCFGR1_CKOUTDIV(0));
if (ret < 0)
return ret;
clk_disable_unprepare(priv->clk);
if (priv->aclk)
clk_disable_unprepare(priv->aclk);
}
dev_dbg(&priv->pdev->dev, "%s: n_active_ch %d\n", __func__,
atomic_read(&priv->n_active_ch));
return 0;
}
EXPORT_SYMBOL_GPL(stm32_dfsdm_stop_dfsdm);
static int stm32_dfsdm_parse_of(struct platform_device *pdev,
struct dfsdm_priv *priv)
{
struct device_node *node = pdev->dev.of_node;
struct resource *res;
unsigned long clk_freq;
unsigned int spi_freq, rem;
int ret;
if (!node)
return -EINVAL;
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
if (!res) {
dev_err(&pdev->dev, "Failed to get memory resource\n");
return -ENODEV;
}
priv->dfsdm.phys_base = res->start;
priv->dfsdm.base = devm_ioremap_resource(&pdev->dev, res);
/*
* "dfsdm" clock is mandatory for DFSDM peripheral clocking.
* "dfsdm" or "audio" clocks can be used as source clock for
* the SPI clock out signal and internal processing, depending
* on use case.
*/
priv->clk = devm_clk_get(&pdev->dev, "dfsdm");
if (IS_ERR(priv->clk)) {
dev_err(&pdev->dev, "No stm32_dfsdm_clk clock found\n");
return -EINVAL;
}
priv->aclk = devm_clk_get(&pdev->dev, "audio");
if (IS_ERR(priv->aclk))
priv->aclk = NULL;
if (priv->aclk)
clk_freq = clk_get_rate(priv->aclk);
else
clk_freq = clk_get_rate(priv->clk);
/* SPI clock out frequency */
ret = of_property_read_u32(pdev->dev.of_node, "spi-max-frequency",
&spi_freq);
if (ret < 0) {
/* No SPI master mode */
return 0;
}
priv->spi_clk_out_div = div_u64_rem(clk_freq, spi_freq, &rem) - 1;
priv->dfsdm.spi_master_freq = spi_freq;
if (rem) {
dev_warn(&pdev->dev, "SPI clock not accurate\n");
dev_warn(&pdev->dev, "%ld = %d * %d + %d\n",
clk_freq, spi_freq, priv->spi_clk_out_div + 1, rem);
}
return 0;
};
static const struct of_device_id stm32_dfsdm_of_match[] = {
{
.compatible = "st,stm32h7-dfsdm",
.data = &stm32h7_dfsdm_data,
},
{}
};
MODULE_DEVICE_TABLE(of, stm32_dfsdm_of_match);
static int stm32_dfsdm_probe(struct platform_device *pdev)
{
struct dfsdm_priv *priv;
const struct of_device_id *of_id;
const struct stm32_dfsdm_dev_data *dev_data;
struct stm32_dfsdm *dfsdm;
int ret;
priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
priv->pdev = pdev;
of_id = of_match_node(stm32_dfsdm_of_match, pdev->dev.of_node);
if (!of_id->data) {
dev_err(&pdev->dev, "Data associated to device is missing\n");
return -EINVAL;
}
dev_data = (const struct stm32_dfsdm_dev_data *)of_id->data;
dfsdm = &priv->dfsdm;
dfsdm->fl_list = devm_kcalloc(&pdev->dev, dev_data->num_filters,
sizeof(*dfsdm->fl_list), GFP_KERNEL);
if (!dfsdm->fl_list)
return -ENOMEM;
dfsdm->num_fls = dev_data->num_filters;
dfsdm->ch_list = devm_kcalloc(&pdev->dev, dev_data->num_channels,
sizeof(*dfsdm->ch_list),
GFP_KERNEL);
if (!dfsdm->ch_list)
return -ENOMEM;
dfsdm->num_chs = dev_data->num_channels;
ret = stm32_dfsdm_parse_of(pdev, priv);
if (ret < 0)
return ret;
dfsdm->regmap = devm_regmap_init_mmio_clk(&pdev->dev, "dfsdm",
dfsdm->base,
&stm32h7_dfsdm_regmap_cfg);
if (IS_ERR(dfsdm->regmap)) {
ret = PTR_ERR(dfsdm->regmap);
dev_err(&pdev->dev, "%s: Failed to allocate regmap: %d\n",
__func__, ret);
return ret;
}
platform_set_drvdata(pdev, dfsdm);
return devm_of_platform_populate(&pdev->dev);
}
static struct platform_driver stm32_dfsdm_driver = {
.probe = stm32_dfsdm_probe,
.driver = {
.name = "stm32-dfsdm",
.of_match_table = stm32_dfsdm_of_match,
},
};
module_platform_driver(stm32_dfsdm_driver);
MODULE_AUTHOR("Arnaud Pouliquen <arnaud.pouliquen@st.com>");
MODULE_DESCRIPTION("STMicroelectronics STM32 dfsdm driver");
MODULE_LICENSE("GPL v2");

310
drivers/iio/adc/stm32-dfsdm.h Normal file
View File

@ -0,0 +1,310 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This file is part of STM32 DFSDM driver
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com>.
*/
#ifndef MDF_STM32_DFSDM__H
#define MDF_STM32_DFSDM__H
#include <linux/bitfield.h>
/*
* STM32 DFSDM - global register map
* ________________________________________________________
* | Offset | Registers block |
* --------------------------------------------------------
* | 0x000 | CHANNEL 0 + COMMON CHANNEL FIELDS |
* --------------------------------------------------------
* | 0x020 | CHANNEL 1 |
* --------------------------------------------------------
* | ... | ..... |
* --------------------------------------------------------
* | 0x0E0 | CHANNEL 7 |
* --------------------------------------------------------
* | 0x100 | FILTER 0 + COMMON FILTER FIELDs |
* --------------------------------------------------------
* | 0x200 | FILTER 1 |
* --------------------------------------------------------
* | 0x300 | FILTER 2 |
* --------------------------------------------------------
* | 0x400 | FILTER 3 |
* --------------------------------------------------------
*/
/*
* Channels register definitions
*/
#define DFSDM_CHCFGR1(y) ((y) * 0x20 + 0x00)
#define DFSDM_CHCFGR2(y) ((y) * 0x20 + 0x04)
#define DFSDM_AWSCDR(y) ((y) * 0x20 + 0x08)
#define DFSDM_CHWDATR(y) ((y) * 0x20 + 0x0C)
#define DFSDM_CHDATINR(y) ((y) * 0x20 + 0x10)
/* CHCFGR1: Channel configuration register 1 */
#define DFSDM_CHCFGR1_SITP_MASK GENMASK(1, 0)
#define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)
#define DFSDM_CHCFGR1_SPICKSEL_MASK GENMASK(3, 2)
#define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)
#define DFSDM_CHCFGR1_SCDEN_MASK BIT(5)
#define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)
#define DFSDM_CHCFGR1_CKABEN_MASK BIT(6)
#define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)
#define DFSDM_CHCFGR1_CHEN_MASK BIT(7)
#define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)
#define DFSDM_CHCFGR1_CHINSEL_MASK BIT(8)
#define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)
#define DFSDM_CHCFGR1_DATMPX_MASK GENMASK(13, 12)
#define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)
#define DFSDM_CHCFGR1_DATPACK_MASK GENMASK(15, 14)
#define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)
#define DFSDM_CHCFGR1_CKOUTDIV_MASK GENMASK(23, 16)
#define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)
#define DFSDM_CHCFGR1_CKOUTSRC_MASK BIT(30)
#define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)
#define DFSDM_CHCFGR1_DFSDMEN_MASK BIT(31)
#define DFSDM_CHCFGR1_DFSDMEN(v) FIELD_PREP(DFSDM_CHCFGR1_DFSDMEN_MASK, v)
/* CHCFGR2: Channel configuration register 2 */
#define DFSDM_CHCFGR2_DTRBS_MASK GENMASK(7, 3)
#define DFSDM_CHCFGR2_DTRBS(v) FIELD_PREP(DFSDM_CHCFGR2_DTRBS_MASK, v)
#define DFSDM_CHCFGR2_OFFSET_MASK GENMASK(31, 8)
#define DFSDM_CHCFGR2_OFFSET(v) FIELD_PREP(DFSDM_CHCFGR2_OFFSET_MASK, v)
/* AWSCDR: Channel analog watchdog and short circuit detector */
#define DFSDM_AWSCDR_SCDT_MASK GENMASK(7, 0)
#define DFSDM_AWSCDR_SCDT(v) FIELD_PREP(DFSDM_AWSCDR_SCDT_MASK, v)
#define DFSDM_AWSCDR_BKSCD_MASK GENMASK(15, 12)
#define DFSDM_AWSCDR_BKSCD(v) FIELD_PREP(DFSDM_AWSCDR_BKSCD_MASK, v)
#define DFSDM_AWSCDR_AWFOSR_MASK GENMASK(20, 16)
#define DFSDM_AWSCDR_AWFOSR(v) FIELD_PREP(DFSDM_AWSCDR_AWFOSR_MASK, v)
#define DFSDM_AWSCDR_AWFORD_MASK GENMASK(23, 22)
#define DFSDM_AWSCDR_AWFORD(v) FIELD_PREP(DFSDM_AWSCDR_AWFORD_MASK, v)
/*
* Filters register definitions
*/
#define DFSDM_FILTER_BASE_ADR 0x100
#define DFSDM_FILTER_REG_MASK 0x7F
#define DFSDM_FILTER_X_BASE_ADR(x) ((x) * 0x80 + DFSDM_FILTER_BASE_ADR)
#define DFSDM_CR1(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x00)
#define DFSDM_CR2(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x04)
#define DFSDM_ISR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x08)
#define DFSDM_ICR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x0C)
#define DFSDM_JCHGR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x10)
#define DFSDM_FCR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x14)
#define DFSDM_JDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x18)
#define DFSDM_RDATAR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x1C)
#define DFSDM_AWHTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x20)
#define DFSDM_AWLTR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x24)
#define DFSDM_AWSR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x28)
#define DFSDM_AWCFR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x2C)
#define DFSDM_EXMAX(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x30)
#define DFSDM_EXMIN(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x34)
#define DFSDM_CNVTIMR(x) (DFSDM_FILTER_X_BASE_ADR(x) + 0x38)
/* CR1 Control register 1 */
#define DFSDM_CR1_DFEN_MASK BIT(0)
#define DFSDM_CR1_DFEN(v) FIELD_PREP(DFSDM_CR1_DFEN_MASK, v)
#define DFSDM_CR1_JSWSTART_MASK BIT(1)
#define DFSDM_CR1_JSWSTART(v) FIELD_PREP(DFSDM_CR1_JSWSTART_MASK, v)
#define DFSDM_CR1_JSYNC_MASK BIT(3)
#define DFSDM_CR1_JSYNC(v) FIELD_PREP(DFSDM_CR1_JSYNC_MASK, v)
#define DFSDM_CR1_JSCAN_MASK BIT(4)
#define DFSDM_CR1_JSCAN(v) FIELD_PREP(DFSDM_CR1_JSCAN_MASK, v)
#define DFSDM_CR1_JDMAEN_MASK BIT(5)
#define DFSDM_CR1_JDMAEN(v) FIELD_PREP(DFSDM_CR1_JDMAEN_MASK, v)
#define DFSDM_CR1_JEXTSEL_MASK GENMASK(12, 8)
#define DFSDM_CR1_JEXTSEL(v) FIELD_PREP(DFSDM_CR1_JEXTSEL_MASK, v)
#define DFSDM_CR1_JEXTEN_MASK GENMASK(14, 13)
#define DFSDM_CR1_JEXTEN(v) FIELD_PREP(DFSDM_CR1_JEXTEN_MASK, v)
#define DFSDM_CR1_RSWSTART_MASK BIT(17)
#define DFSDM_CR1_RSWSTART(v) FIELD_PREP(DFSDM_CR1_RSWSTART_MASK, v)
#define DFSDM_CR1_RCONT_MASK BIT(18)
#define DFSDM_CR1_RCONT(v) FIELD_PREP(DFSDM_CR1_RCONT_MASK, v)
#define DFSDM_CR1_RSYNC_MASK BIT(19)
#define DFSDM_CR1_RSYNC(v) FIELD_PREP(DFSDM_CR1_RSYNC_MASK, v)
#define DFSDM_CR1_RDMAEN_MASK BIT(21)
#define DFSDM_CR1_RDMAEN(v) FIELD_PREP(DFSDM_CR1_RDMAEN_MASK, v)
#define DFSDM_CR1_RCH_MASK GENMASK(26, 24)
#define DFSDM_CR1_RCH(v) FIELD_PREP(DFSDM_CR1_RCH_MASK, v)
#define DFSDM_CR1_FAST_MASK BIT(29)
#define DFSDM_CR1_FAST(v) FIELD_PREP(DFSDM_CR1_FAST_MASK, v)
#define DFSDM_CR1_AWFSEL_MASK BIT(30)
#define DFSDM_CR1_AWFSEL(v) FIELD_PREP(DFSDM_CR1_AWFSEL_MASK, v)
/* CR2: Control register 2 */
#define DFSDM_CR2_IE_MASK GENMASK(6, 0)
#define DFSDM_CR2_IE(v) FIELD_PREP(DFSDM_CR2_IE_MASK, v)
#define DFSDM_CR2_JEOCIE_MASK BIT(0)
#define DFSDM_CR2_JEOCIE(v) FIELD_PREP(DFSDM_CR2_JEOCIE_MASK, v)
#define DFSDM_CR2_REOCIE_MASK BIT(1)
#define DFSDM_CR2_REOCIE(v) FIELD_PREP(DFSDM_CR2_REOCIE_MASK, v)
#define DFSDM_CR2_JOVRIE_MASK BIT(2)
#define DFSDM_CR2_JOVRIE(v) FIELD_PREP(DFSDM_CR2_JOVRIE_MASK, v)
#define DFSDM_CR2_ROVRIE_MASK BIT(3)
#define DFSDM_CR2_ROVRIE(v) FIELD_PREP(DFSDM_CR2_ROVRIE_MASK, v)
#define DFSDM_CR2_AWDIE_MASK BIT(4)
#define DFSDM_CR2_AWDIE(v) FIELD_PREP(DFSDM_CR2_AWDIE_MASK, v)
#define DFSDM_CR2_SCDIE_MASK BIT(5)
#define DFSDM_CR2_SCDIE(v) FIELD_PREP(DFSDM_CR2_SCDIE_MASK, v)
#define DFSDM_CR2_CKABIE_MASK BIT(6)
#define DFSDM_CR2_CKABIE(v) FIELD_PREP(DFSDM_CR2_CKABIE_MASK, v)
#define DFSDM_CR2_EXCH_MASK GENMASK(15, 8)
#define DFSDM_CR2_EXCH(v) FIELD_PREP(DFSDM_CR2_EXCH_MASK, v)
#define DFSDM_CR2_AWDCH_MASK GENMASK(23, 16)
#define DFSDM_CR2_AWDCH(v) FIELD_PREP(DFSDM_CR2_AWDCH_MASK, v)
/* ISR: Interrupt status register */
#define DFSDM_ISR_JEOCF_MASK BIT(0)
#define DFSDM_ISR_JEOCF(v) FIELD_PREP(DFSDM_ISR_JEOCF_MASK, v)
#define DFSDM_ISR_REOCF_MASK BIT(1)
#define DFSDM_ISR_REOCF(v) FIELD_PREP(DFSDM_ISR_REOCF_MASK, v)
#define DFSDM_ISR_JOVRF_MASK BIT(2)
#define DFSDM_ISR_JOVRF(v) FIELD_PREP(DFSDM_ISR_JOVRF_MASK, v)
#define DFSDM_ISR_ROVRF_MASK BIT(3)
#define DFSDM_ISR_ROVRF(v) FIELD_PREP(DFSDM_ISR_ROVRF_MASK, v)
#define DFSDM_ISR_AWDF_MASK BIT(4)
#define DFSDM_ISR_AWDF(v) FIELD_PREP(DFSDM_ISR_AWDF_MASK, v)
#define DFSDM_ISR_JCIP_MASK BIT(13)
#define DFSDM_ISR_JCIP(v) FIELD_PREP(DFSDM_ISR_JCIP_MASK, v)
#define DFSDM_ISR_RCIP_MASK BIT(14)
#define DFSDM_ISR_RCIP(v) FIELD_PREP(DFSDM_ISR_RCIP, v)
#define DFSDM_ISR_CKABF_MASK GENMASK(23, 16)
#define DFSDM_ISR_CKABF(v) FIELD_PREP(DFSDM_ISR_CKABF_MASK, v)
#define DFSDM_ISR_SCDF_MASK GENMASK(31, 24)
#define DFSDM_ISR_SCDF(v) FIELD_PREP(DFSDM_ISR_SCDF_MASK, v)
/* ICR: Interrupt flag clear register */
#define DFSDM_ICR_CLRJOVRF_MASK BIT(2)
#define DFSDM_ICR_CLRJOVRF(v) FIELD_PREP(DFSDM_ICR_CLRJOVRF_MASK, v)
#define DFSDM_ICR_CLRROVRF_MASK BIT(3)
#define DFSDM_ICR_CLRROVRF(v) FIELD_PREP(DFSDM_ICR_CLRROVRF_MASK, v)
#define DFSDM_ICR_CLRCKABF_MASK GENMASK(23, 16)
#define DFSDM_ICR_CLRCKABF(v) FIELD_PREP(DFSDM_ICR_CLRCKABF_MASK, v)
#define DFSDM_ICR_CLRCKABF_CH_MASK(y) BIT(16 + (y))
#define DFSDM_ICR_CLRCKABF_CH(v, y) \
(((v) << (16 + (y))) & DFSDM_ICR_CLRCKABF_CH_MASK(y))
#define DFSDM_ICR_CLRSCDF_MASK GENMASK(31, 24)
#define DFSDM_ICR_CLRSCDF(v) FIELD_PREP(DFSDM_ICR_CLRSCDF_MASK, v)
#define DFSDM_ICR_CLRSCDF_CH_MASK(y) BIT(24 + (y))
#define DFSDM_ICR_CLRSCDF_CH(v, y) \
(((v) << (24 + (y))) & DFSDM_ICR_CLRSCDF_MASK(y))
/* FCR: Filter control register */
#define DFSDM_FCR_IOSR_MASK GENMASK(7, 0)
#define DFSDM_FCR_IOSR(v) FIELD_PREP(DFSDM_FCR_IOSR_MASK, v)
#define DFSDM_FCR_FOSR_MASK GENMASK(25, 16)
#define DFSDM_FCR_FOSR(v) FIELD_PREP(DFSDM_FCR_FOSR_MASK, v)
#define DFSDM_FCR_FORD_MASK GENMASK(31, 29)
#define DFSDM_FCR_FORD(v) FIELD_PREP(DFSDM_FCR_FORD_MASK, v)
/* RDATAR: Filter data register for regular channel */
#define DFSDM_DATAR_CH_MASK GENMASK(2, 0)
#define DFSDM_DATAR_DATA_OFFSET 8
#define DFSDM_DATAR_DATA_MASK GENMASK(31, DFSDM_DATAR_DATA_OFFSET)
/* AWLTR: Filter analog watchdog low threshold register */
#define DFSDM_AWLTR_BKAWL_MASK GENMASK(3, 0)
#define DFSDM_AWLTR_BKAWL(v) FIELD_PREP(DFSDM_AWLTR_BKAWL_MASK, v)
#define DFSDM_AWLTR_AWLT_MASK GENMASK(31, 8)
#define DFSDM_AWLTR_AWLT(v) FIELD_PREP(DFSDM_AWLTR_AWLT_MASK, v)
/* AWHTR: Filter analog watchdog low threshold register */
#define DFSDM_AWHTR_BKAWH_MASK GENMASK(3, 0)
#define DFSDM_AWHTR_BKAWH(v) FIELD_PREP(DFSDM_AWHTR_BKAWH_MASK, v)
#define DFSDM_AWHTR_AWHT_MASK GENMASK(31, 8)
#define DFSDM_AWHTR_AWHT(v) FIELD_PREP(DFSDM_AWHTR_AWHT_MASK, v)
/* AWSR: Filter watchdog status register */
#define DFSDM_AWSR_AWLTF_MASK GENMASK(7, 0)
#define DFSDM_AWSR_AWLTF(v) FIELD_PREP(DFSDM_AWSR_AWLTF_MASK, v)
#define DFSDM_AWSR_AWHTF_MASK GENMASK(15, 8)
#define DFSDM_AWSR_AWHTF(v) FIELD_PREP(DFSDM_AWSR_AWHTF_MASK, v)
/* AWCFR: Filter watchdog status register */
#define DFSDM_AWCFR_AWLTF_MASK GENMASK(7, 0)
#define DFSDM_AWCFR_AWLTF(v) FIELD_PREP(DFSDM_AWCFR_AWLTF_MASK, v)
#define DFSDM_AWCFR_AWHTF_MASK GENMASK(15, 8)
#define DFSDM_AWCFR_AWHTF(v) FIELD_PREP(DFSDM_AWCFR_AWHTF_MASK, v)
/* DFSDM filter order */
enum stm32_dfsdm_sinc_order {
DFSDM_FASTSINC_ORDER, /* FastSinc filter type */
DFSDM_SINC1_ORDER, /* Sinc 1 filter type */
DFSDM_SINC2_ORDER, /* Sinc 2 filter type */
DFSDM_SINC3_ORDER, /* Sinc 3 filter type */
DFSDM_SINC4_ORDER, /* Sinc 4 filter type (N.A. for watchdog) */
DFSDM_SINC5_ORDER, /* Sinc 5 filter type (N.A. for watchdog) */
DFSDM_NB_SINC_ORDER,
};
/**
* struct stm32_dfsdm_filter - structure relative to stm32 FDSDM filter
* @iosr: integrator oversampling
* @fosr: filter oversampling
* @ford: filter order
* @res: output sample resolution
* @sync_mode: filter synchronized with filter 0
* @fast: filter fast mode
*/
struct stm32_dfsdm_filter {
unsigned int iosr;
unsigned int fosr;
enum stm32_dfsdm_sinc_order ford;
u64 res;
unsigned int sync_mode;
unsigned int fast;
};
/**
* struct stm32_dfsdm_channel - structure relative to stm32 FDSDM channel
* @id: id of the channel
* @type: interface type linked to stm32_dfsdm_chan_type
* @src: interface type linked to stm32_dfsdm_chan_src
* @alt_si: alternative serial input interface
*/
struct stm32_dfsdm_channel {
unsigned int id;
unsigned int type;
unsigned int src;
unsigned int alt_si;
};
/**
* struct stm32_dfsdm - stm32 FDSDM driver common data (for all instances)
* @base: control registers base cpu addr
* @phys_base: DFSDM IP register physical address
* @regmap: regmap for register read/write
* @fl_list: filter resources list
* @num_fls: number of filter resources available
* @ch_list: channel resources list
* @num_chs: number of channel resources available
* @spi_master_freq: SPI clock out frequency
*/
struct stm32_dfsdm {
void __iomem *base;
phys_addr_t phys_base;
struct regmap *regmap;
struct stm32_dfsdm_filter *fl_list;
unsigned int num_fls;
struct stm32_dfsdm_channel *ch_list;
unsigned int num_chs;
unsigned int spi_master_freq;
};
/* DFSDM channel serial spi clock source */
enum stm32_dfsdm_spi_clk_src {
DFSDM_CHANNEL_SPI_CLOCK_EXTERNAL,
DFSDM_CHANNEL_SPI_CLOCK_INTERNAL,
DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_FALLING,
DFSDM_CHANNEL_SPI_CLOCK_INTERNAL_DIV2_RISING
};
int stm32_dfsdm_start_dfsdm(struct stm32_dfsdm *dfsdm);
int stm32_dfsdm_stop_dfsdm(struct stm32_dfsdm *dfsdm);
#endif

10
drivers/iio/buffer/Kconfig
View File

@ -29,6 +29,16 @@ config IIO_BUFFER_DMAENGINE
Should be selected by drivers that want to use this functionality. Should be selected by drivers that want to use this functionality.
config IIO_BUFFER_HW_CONSUMER
tristate "Industrial I/O HW buffering"
help
Provides a way to bonding when an IIO device has a direct connection
to another device in hardware. In this case buffers for data transfers
are handled by hardware.
Should be selected by drivers that want to use the generic Hw consumer
interface.
config IIO_KFIFO_BUF config IIO_KFIFO_BUF
tristate "Industrial I/O buffering based on kfifo" tristate "Industrial I/O buffering based on kfifo"
help help

1
drivers/iio/buffer/Makefile
View File

@ -7,5 +7,6 @@
obj-$(CONFIG_IIO_BUFFER_CB) += industrialio-buffer-cb.o obj-$(CONFIG_IIO_BUFFER_CB) += industrialio-buffer-cb.o
obj-$(CONFIG_IIO_BUFFER_DMA) += industrialio-buffer-dma.o obj-$(CONFIG_IIO_BUFFER_DMA) += industrialio-buffer-dma.o
obj-$(CONFIG_IIO_BUFFER_DMAENGINE) += industrialio-buffer-dmaengine.o obj-$(CONFIG_IIO_BUFFER_DMAENGINE) += industrialio-buffer-dmaengine.o
obj-$(CONFIG_IIO_BUFFER_HW_CONSUMER) += industrialio-hw-consumer.o
obj-$(CONFIG_IIO_TRIGGERED_BUFFER) += industrialio-triggered-buffer.o obj-$(CONFIG_IIO_TRIGGERED_BUFFER) += industrialio-triggered-buffer.o
obj-$(CONFIG_IIO_KFIFO_BUF) += kfifo_buf.o obj-$(CONFIG_IIO_KFIFO_BUF) += kfifo_buf.o

11
drivers/iio/buffer/industrialio-buffer-cb.c
View File

@ -104,6 +104,17 @@ error_free_cb_buff:
} }
EXPORT_SYMBOL_GPL(iio_channel_get_all_cb); EXPORT_SYMBOL_GPL(iio_channel_get_all_cb);
int iio_channel_cb_set_buffer_watermark(struct iio_cb_buffer *cb_buff,
size_t watermark)
{
if (!watermark)
return -EINVAL;
cb_buff->buffer.watermark = watermark;
return 0;
}
EXPORT_SYMBOL_GPL(iio_channel_cb_set_buffer_watermark);
int iio_channel_start_all_cb(struct iio_cb_buffer *cb_buff) int iio_channel_start_all_cb(struct iio_cb_buffer *cb_buff)
{ {
return iio_update_buffers(cb_buff->indio_dev, &cb_buff->buffer, return iio_update_buffers(cb_buff->indio_dev, &cb_buff->buffer,

247
drivers/iio/buffer/industrialio-hw-consumer.c Normal file
View File

@ -0,0 +1,247 @@
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright 2017 Analog Devices Inc.
* Author: Lars-Peter Clausen <lars@metafoo.de>
*/
#include <linux/err.h>
#include <linux/export.h>
#include <linux/slab.h>
#include <linux/module.h>
#include <linux/iio/iio.h>
#include <linux/iio/consumer.h>
#include <linux/iio/hw-consumer.h>
#include <linux/iio/buffer_impl.h>
/**
* struct iio_hw_consumer - IIO hw consumer block
* @buffers: hardware buffers list head.
* @channels: IIO provider channels.
*/
struct iio_hw_consumer {
struct list_head buffers;
struct iio_channel *channels;
};
struct hw_consumer_buffer {
struct list_head head;
struct iio_dev *indio_dev;
struct iio_buffer buffer;
long scan_mask[];
};
static struct hw_consumer_buffer *iio_buffer_to_hw_consumer_buffer(
struct iio_buffer *buffer)
{
return container_of(buffer, struct hw_consumer_buffer, buffer);
}
static void iio_hw_buf_release(struct iio_buffer *buffer)
{
struct hw_consumer_buffer *hw_buf =
iio_buffer_to_hw_consumer_buffer(buffer);
kfree(hw_buf);
}
static const struct iio_buffer_access_funcs iio_hw_buf_access = {
.release = &iio_hw_buf_release,
.modes = INDIO_BUFFER_HARDWARE,
};
static struct hw_consumer_buffer *iio_hw_consumer_get_buffer(
struct iio_hw_consumer *hwc, struct iio_dev *indio_dev)
{
size_t mask_size = BITS_TO_LONGS(indio_dev->masklength) * sizeof(long);
struct hw_consumer_buffer *buf;
list_for_each_entry(buf, &hwc->buffers, head) {
if (buf->indio_dev == indio_dev)
return buf;
}
buf = kzalloc(sizeof(*buf) + mask_size, GFP_KERNEL);
if (!buf)
return NULL;
buf->buffer.access = &iio_hw_buf_access;
buf->indio_dev = indio_dev;
buf->buffer.scan_mask = buf->scan_mask;
iio_buffer_init(&buf->buffer);
list_add_tail(&buf->head, &hwc->buffers);
return buf;
}
/**
* iio_hw_consumer_alloc() - Allocate IIO hardware consumer
* @dev: Pointer to consumer device.
*
* Returns a valid iio_hw_consumer on success or a ERR_PTR() on failure.
*/
struct iio_hw_consumer *iio_hw_consumer_alloc(struct device *dev)
{
struct hw_consumer_buffer *buf;
struct iio_hw_consumer *hwc;
struct iio_channel *chan;
int ret;
hwc = kzalloc(sizeof(*hwc), GFP_KERNEL);
if (!hwc)
return ERR_PTR(-ENOMEM);
INIT_LIST_HEAD(&hwc->buffers);
hwc->channels = iio_channel_get_all(dev);
if (IS_ERR(hwc->channels)) {
ret = PTR_ERR(hwc->channels);
goto err_free_hwc;
}
chan = &hwc->channels[0];
while (chan->indio_dev) {
buf = iio_hw_consumer_get_buffer(hwc, chan->indio_dev);
if (!buf) {
ret = -ENOMEM;
goto err_put_buffers;
}
set_bit(chan->channel->scan_index, buf->buffer.scan_mask);
chan++;
}
return hwc;
err_put_buffers:
list_for_each_entry(buf, &hwc->buffers, head)
iio_buffer_put(&buf->buffer);
iio_channel_release_all(hwc->channels);
err_free_hwc:
kfree(hwc);
return ERR_PTR(ret);
}
EXPORT_SYMBOL_GPL(iio_hw_consumer_alloc);
/**
* iio_hw_consumer_free() - Free IIO hardware consumer
* @hwc: hw consumer to free.
*/
void iio_hw_consumer_free(struct iio_hw_consumer *hwc)
{
struct hw_consumer_buffer *buf, *n;
iio_channel_release_all(hwc->channels);
list_for_each_entry_safe(buf, n, &hwc->buffers, head)
iio_buffer_put(&buf->buffer);
kfree(hwc);
}
EXPORT_SYMBOL_GPL(iio_hw_consumer_free);
static void devm_iio_hw_consumer_release(struct device *dev, void *res)
{
iio_hw_consumer_free(*(struct iio_hw_consumer **)res);
}
static int devm_iio_hw_consumer_match(struct device *dev, void *res, void *data)
{
struct iio_hw_consumer **r = res;
if (!r || !*r) {
WARN_ON(!r || !*r);
return 0;
}
return *r == data;
}
/**
* devm_iio_hw_consumer_alloc - Resource-managed iio_hw_consumer_alloc()
* @dev: Pointer to consumer device.
*
* Managed iio_hw_consumer_alloc. iio_hw_consumer allocated with this function
* is automatically freed on driver detach.
*
* If an iio_hw_consumer allocated with this function needs to be freed
* separately, devm_iio_hw_consumer_free() must be used.
*
* returns pointer to allocated iio_hw_consumer on success, NULL on failure.
*/
struct iio_hw_consumer *devm_iio_hw_consumer_alloc(struct device *dev)
{
struct iio_hw_consumer **ptr, *iio_hwc;
ptr = devres_alloc(devm_iio_hw_consumer_release, sizeof(*ptr),
GFP_KERNEL);
if (!ptr)
return NULL;
iio_hwc = iio_hw_consumer_alloc(dev);
if (IS_ERR(iio_hwc)) {
devres_free(ptr);
} else {
*ptr = iio_hwc;
devres_add(dev, ptr);
}
return iio_hwc;
}
EXPORT_SYMBOL_GPL(devm_iio_hw_consumer_alloc);
/**
* devm_iio_hw_consumer_free - Resource-managed iio_hw_consumer_free()
* @dev: Pointer to consumer device.
* @hwc: iio_hw_consumer to free.
*
* Free iio_hw_consumer allocated with devm_iio_hw_consumer_alloc().
*/
void devm_iio_hw_consumer_free(struct device *dev, struct iio_hw_consumer *hwc)
{
int rc;
rc = devres_release(dev, devm_iio_hw_consumer_release,
devm_iio_hw_consumer_match, hwc);
WARN_ON(rc);
}
EXPORT_SYMBOL_GPL(devm_iio_hw_consumer_free);
/**
* iio_hw_consumer_enable() - Enable IIO hardware consumer
* @hwc: iio_hw_consumer to enable.
*
* Returns 0 on success.
*/
int iio_hw_consumer_enable(struct iio_hw_consumer *hwc)
{
struct hw_consumer_buffer *buf;
int ret;
list_for_each_entry(buf, &hwc->buffers, head) {
ret = iio_update_buffers(buf->indio_dev, &buf->buffer, NULL);
if (ret)
goto err_disable_buffers;
}
return 0;
err_disable_buffers:
list_for_each_entry_continue_reverse(buf, &hwc->buffers, head)
iio_update_buffers(buf->indio_dev, NULL, &buf->buffer);
return ret;
}
EXPORT_SYMBOL_GPL(iio_hw_consumer_enable);
/**
* iio_hw_consumer_disable() - Disable IIO hardware consumer
* @hwc: iio_hw_consumer to disable.
*/
void iio_hw_consumer_disable(struct iio_hw_consumer *hwc)
{
struct hw_consumer_buffer *buf;
list_for_each_entry(buf, &hwc->buffers, head)
iio_update_buffers(buf->indio_dev, NULL, &buf->buffer);
}
EXPORT_SYMBOL_GPL(iio_hw_consumer_disable);
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_DESCRIPTION("Hardware consumer buffer the IIO framework");
MODULE_LICENSE("GPL v2");

17
drivers/iio/inkern.c
View File

@ -664,9 +664,8 @@ err_unlock:
} }
EXPORT_SYMBOL_GPL(iio_convert_raw_to_processed); EXPORT_SYMBOL_GPL(iio_convert_raw_to_processed);
static int iio_read_channel_attribute(struct iio_channel *chan, int iio_read_channel_attribute(struct iio_channel *chan, int *val, int *val2,
int *val, int *val2, enum iio_chan_info_enum attribute)
enum iio_chan_info_enum attribute)
{ {
int ret; int ret;
@ -682,6 +681,7 @@ err_unlock:
return ret; return ret;
} }
EXPORT_SYMBOL_GPL(iio_read_channel_attribute);
int iio_read_channel_offset(struct iio_channel *chan, int *val, int *val2) int iio_read_channel_offset(struct iio_channel *chan, int *val, int *val2)
{ {
@ -850,7 +850,8 @@ static int iio_channel_write(struct iio_channel *chan, int val, int val2,
chan->channel, val, val2, info); chan->channel, val, val2, info);
} }
int iio_write_channel_raw(struct iio_channel *chan, int val) int iio_write_channel_attribute(struct iio_channel *chan, int val, int val2,
enum iio_chan_info_enum attribute)
{ {
int ret; int ret;
@ -860,12 +861,18 @@ int iio_write_channel_raw(struct iio_channel *chan, int val)
goto err_unlock; goto err_unlock;
} }
ret = iio_channel_write(chan, val, 0, IIO_CHAN_INFO_RAW); ret = iio_channel_write(chan, val, val2, attribute);
err_unlock: err_unlock:
mutex_unlock(&chan->indio_dev->info_exist_lock); mutex_unlock(&chan->indio_dev->info_exist_lock);
return ret; return ret;
} }
EXPORT_SYMBOL_GPL(iio_write_channel_attribute);
int iio_write_channel_raw(struct iio_channel *chan, int val)
{
return iio_write_channel_attribute(chan, val, 0, IIO_CHAN_INFO_RAW);
}
EXPORT_SYMBOL_GPL(iio_write_channel_raw); EXPORT_SYMBOL_GPL(iio_write_channel_raw);
unsigned int iio_get_channel_ext_info_count(struct iio_channel *chan) unsigned int iio_get_channel_ext_info_count(struct iio_channel *chan)

18
include/linux/iio/adc/stm32-dfsdm-adc.h Normal file
View File

@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* This file discribe the STM32 DFSDM IIO driver API for audio part
*
* Copyright (C) 2017, STMicroelectronics - All Rights Reserved
* Author(s): Arnaud Pouliquen <arnaud.pouliquen@st.com>.
*/
#ifndef STM32_DFSDM_ADC_H
#define STM32_DFSDM_ADC_H
int stm32_dfsdm_get_buff_cb(struct iio_dev *iio_dev,
int (*cb)(const void *data, size_t size,
void *private),
void *private);
int stm32_dfsdm_release_buff_cb(struct iio_dev *iio_dev);
#endif

37
include/linux/iio/consumer.h
View File

@ -133,6 +133,17 @@ struct iio_cb_buffer *iio_channel_get_all_cb(struct device *dev,
int (*cb)(const void *data, int (*cb)(const void *data,
void *private), void *private),
void *private); void *private);
/**
* iio_channel_cb_set_buffer_watermark() - set the buffer watermark.
* @cb_buffer: The callback buffer from whom we want the channel
* information.
* @watermark: buffer watermark in bytes.
*
* This function allows to configure the buffer watermark.
*/
int iio_channel_cb_set_buffer_watermark(struct iio_cb_buffer *cb_buffer,
size_t watermark);
/** /**
* iio_channel_release_all_cb() - release and unregister the callback. * iio_channel_release_all_cb() - release and unregister the callback.
* @cb_buffer: The callback buffer that was allocated. * @cb_buffer: The callback buffer that was allocated.
@ -215,6 +226,32 @@ int iio_read_channel_average_raw(struct iio_channel *chan, int *val);
*/ */
int iio_read_channel_processed(struct iio_channel *chan, int *val); int iio_read_channel_processed(struct iio_channel *chan, int *val);
/**
* iio_write_channel_attribute() - Write values to the device attribute.
* @chan: The channel being queried.
* @val: Value being written.
* @val2: Value being written.val2 use depends on attribute type.
* @attribute: info attribute to be read.
*
* Returns an error code or 0.
*/
int iio_write_channel_attribute(struct iio_channel *chan, int val,
int val2, enum iio_chan_info_enum attribute);
/**
* iio_read_channel_attribute() - Read values from the device attribute.
* @chan: The channel being queried.
* @val: Value being written.
* @val2: Value being written.Val2 use depends on attribute type.
* @attribute: info attribute to be written.
*
* Returns an error code if failed. Else returns a description of what is in val
* and val2, such as IIO_VAL_INT_PLUS_MICRO telling us we have a value of val
* + val2/1e6
*/
int iio_read_channel_attribute(struct iio_channel *chan, int *val,
int *val2, enum iio_chan_info_enum attribute);
/** /**
* iio_write_channel_raw() - write to a given channel * iio_write_channel_raw() - write to a given channel
* @chan: The channel being queried. * @chan: The channel being queried.

21
include/linux/iio/hw-consumer.h Normal file
View File

@ -0,0 +1,21 @@
/* SPDX-License-Identifier: GPL-2.0 */
/*
* Industrial I/O in kernel hardware consumer interface
*
* Copyright 2017 Analog Devices Inc.
* Author: Lars-Peter Clausen <lars@metafoo.de>
*/
#ifndef LINUX_IIO_HW_CONSUMER_H
#define LINUX_IIO_HW_CONSUMER_H
struct iio_hw_consumer;
struct iio_hw_consumer *iio_hw_consumer_alloc(struct device *dev);
void iio_hw_consumer_free(struct iio_hw_consumer *hwc);
struct iio_hw_consumer *devm_iio_hw_consumer_alloc(struct device *dev);
void devm_iio_hw_consumer_free(struct device *dev, struct iio_hw_consumer *hwc);
int iio_hw_consumer_enable(struct iio_hw_consumer *hwc);
void iio_hw_consumer_disable(struct iio_hw_consumer *hwc);
#endif

28
include/linux/iio/iio.h
View File

@ -20,34 +20,6 @@
* Currently assumes nano seconds. * Currently assumes nano seconds.
*/ */
enum iio_chan_info_enum {
IIO_CHAN_INFO_RAW = 0,
IIO_CHAN_INFO_PROCESSED,
IIO_CHAN_INFO_SCALE,
IIO_CHAN_INFO_OFFSET,
IIO_CHAN_INFO_CALIBSCALE,
IIO_CHAN_INFO_CALIBBIAS,
IIO_CHAN_INFO_PEAK,
IIO_CHAN_INFO_PEAK_SCALE,
IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW,
IIO_CHAN_INFO_AVERAGE_RAW,
IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY,
IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY,
IIO_CHAN_INFO_SAMP_FREQ,
IIO_CHAN_INFO_FREQUENCY,
IIO_CHAN_INFO_PHASE,
IIO_CHAN_INFO_HARDWAREGAIN,
IIO_CHAN_INFO_HYSTERESIS,
IIO_CHAN_INFO_INT_TIME,
IIO_CHAN_INFO_ENABLE,
IIO_CHAN_INFO_CALIBHEIGHT,
IIO_CHAN_INFO_CALIBWEIGHT,
IIO_CHAN_INFO_DEBOUNCE_COUNT,
IIO_CHAN_INFO_DEBOUNCE_TIME,
IIO_CHAN_INFO_CALIBEMISSIVITY,
IIO_CHAN_INFO_OVERSAMPLING_RATIO,
};
enum iio_shared_by { enum iio_shared_by {
IIO_SEPARATE, IIO_SEPARATE,
IIO_SHARED_BY_TYPE, IIO_SHARED_BY_TYPE,

28
include/linux/iio/types.h
View File

@ -34,4 +34,32 @@ enum iio_available_type {
IIO_AVAIL_RANGE, IIO_AVAIL_RANGE,
}; };
enum iio_chan_info_enum {
IIO_CHAN_INFO_RAW = 0,
IIO_CHAN_INFO_PROCESSED,
IIO_CHAN_INFO_SCALE,
IIO_CHAN_INFO_OFFSET,
IIO_CHAN_INFO_CALIBSCALE,
IIO_CHAN_INFO_CALIBBIAS,
IIO_CHAN_INFO_PEAK,
IIO_CHAN_INFO_PEAK_SCALE,
IIO_CHAN_INFO_QUADRATURE_CORRECTION_RAW,
IIO_CHAN_INFO_AVERAGE_RAW,
IIO_CHAN_INFO_LOW_PASS_FILTER_3DB_FREQUENCY,
IIO_CHAN_INFO_HIGH_PASS_FILTER_3DB_FREQUENCY,
IIO_CHAN_INFO_SAMP_FREQ,
IIO_CHAN_INFO_FREQUENCY,
IIO_CHAN_INFO_PHASE,
IIO_CHAN_INFO_HARDWAREGAIN,
IIO_CHAN_INFO_HYSTERESIS,
IIO_CHAN_INFO_INT_TIME,
IIO_CHAN_INFO_ENABLE,
IIO_CHAN_INFO_CALIBHEIGHT,
IIO_CHAN_INFO_CALIBWEIGHT,
IIO_CHAN_INFO_DEBOUNCE_COUNT,
IIO_CHAN_INFO_DEBOUNCE_TIME,
IIO_CHAN_INFO_CALIBEMISSIVITY,
IIO_CHAN_INFO_OVERSAMPLING_RATIO,
};
#endif /* _IIO_TYPES_H_ */ #endif /* _IIO_TYPES_H_ */

5
sound/soc/codecs/Kconfig
View File

@ -95,6 +95,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_MAX98925 if I2C select SND_SOC_MAX98925 if I2C
select SND_SOC_MAX98926 if I2C select SND_SOC_MAX98926 if I2C
select SND_SOC_MAX98927 if I2C select SND_SOC_MAX98927 if I2C
select SND_SOC_MAX98373 if I2C
select SND_SOC_MAX9850 if I2C select SND_SOC_MAX9850 if I2C
select SND_SOC_MAX9860 if I2C select SND_SOC_MAX9860 if I2C
select SND_SOC_MAX9768 if I2C select SND_SOC_MAX9768 if I2C
@ -624,6 +625,10 @@ config SND_SOC_MAX98927
tristate "Maxim Integrated MAX98927 Speaker Amplifier" tristate "Maxim Integrated MAX98927 Speaker Amplifier"
depends on I2C depends on I2C
config SND_SOC_MAX98373
tristate "Maxim Integrated MAX98373 Speaker Amplifier"
depends on I2C
config SND_SOC_MAX9850 config SND_SOC_MAX9850
tristate tristate

2
sound/soc/codecs/Makefile
View File

@ -90,6 +90,7 @@ snd-soc-max9867-objs := max9867.o
snd-soc-max98925-objs := max98925.o snd-soc-max98925-objs := max98925.o
snd-soc-max98926-objs := max98926.o snd-soc-max98926-objs := max98926.o
snd-soc-max98927-objs := max98927.o snd-soc-max98927-objs := max98927.o
snd-soc-max98373-objs := max98373.o
snd-soc-max9850-objs := max9850.o snd-soc-max9850-objs := max9850.o
snd-soc-max9860-objs := max9860.o snd-soc-max9860-objs := max9860.o
snd-soc-mc13783-objs := mc13783.o snd-soc-mc13783-objs := mc13783.o
@ -332,6 +333,7 @@ obj-$(CONFIG_SND_SOC_MAX9867) += snd-soc-max9867.o
obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o obj-$(CONFIG_SND_SOC_MAX98925) += snd-soc-max98925.o
obj-$(CONFIG_SND_SOC_MAX98926) += snd-soc-max98926.o obj-$(CONFIG_SND_SOC_MAX98926) += snd-soc-max98926.o
obj-$(CONFIG_SND_SOC_MAX98927) += snd-soc-max98927.o obj-$(CONFIG_SND_SOC_MAX98927) += snd-soc-max98927.o
obj-$(CONFIG_SND_SOC_MAX98373) += snd-soc-max98373.o
obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o obj-$(CONFIG_SND_SOC_MAX9850) += snd-soc-max9850.o
obj-$(CONFIG_SND_SOC_MAX9860) += snd-soc-max9860.o obj-$(CONFIG_SND_SOC_MAX9860) += snd-soc-max9860.o
obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o obj-$(CONFIG_SND_SOC_MC13783) += snd-soc-mc13783.o

2
sound/soc/codecs/hdac_hdmi.c
View File

@ -2186,6 +2186,8 @@ static const struct hda_device_id hdmi_list[] = {
HDA_CODEC_EXT_ENTRY(0x80862809, 0x100000, "Skylake HDMI", 0), HDA_CODEC_EXT_ENTRY(0x80862809, 0x100000, "Skylake HDMI", 0),
HDA_CODEC_EXT_ENTRY(0x8086280a, 0x100000, "Broxton HDMI", 0), HDA_CODEC_EXT_ENTRY(0x8086280a, 0x100000, "Broxton HDMI", 0),
HDA_CODEC_EXT_ENTRY(0x8086280b, 0x100000, "Kabylake HDMI", 0), HDA_CODEC_EXT_ENTRY(0x8086280b, 0x100000, "Kabylake HDMI", 0),
HDA_CODEC_EXT_ENTRY(0x8086280c, 0x100000, "Cannonlake HDMI",
&intel_glk_drv_data),
HDA_CODEC_EXT_ENTRY(0x8086280d, 0x100000, "Geminilake HDMI", HDA_CODEC_EXT_ENTRY(0x8086280d, 0x100000, "Geminilake HDMI",
&intel_glk_drv_data), &intel_glk_drv_data),
{} {}

976
sound/soc/codecs/max98373.c Normal file
View File

@ -0,0 +1,976 @@
/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2017, Maxim Integrated */
#include <linux/acpi.h>
#include <linux/i2c.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/cdev.h>
#include <sound/pcm.h>
#include <sound/pcm_params.h>
#include <sound/soc.h>
#include <linux/gpio.h>
#include <linux/of_gpio.h>
#include <sound/tlv.h>
#include "max98373.h"
static struct reg_default max98373_reg[] = {
{MAX98373_R2000_SW_RESET, 0x00},
{MAX98373_R2001_INT_RAW1, 0x00},
{MAX98373_R2002_INT_RAW2, 0x00},
{MAX98373_R2003_INT_RAW3, 0x00},
{MAX98373_R2004_INT_STATE1, 0x00},
{MAX98373_R2005_INT_STATE2, 0x00},
{MAX98373_R2006_INT_STATE3, 0x00},
{MAX98373_R2007_INT_FLAG1, 0x00},
{MAX98373_R2008_INT_FLAG2, 0x00},
{MAX98373_R2009_INT_FLAG3, 0x00},
{MAX98373_R200A_INT_EN1, 0x00},
{MAX98373_R200B_INT_EN2, 0x00},
{MAX98373_R200C_INT_EN3, 0x00},
{MAX98373_R200D_INT_FLAG_CLR1, 0x00},
{MAX98373_R200E_INT_FLAG_CLR2, 0x00},
{MAX98373_R200F_INT_FLAG_CLR3, 0x00},
{MAX98373_R2010_IRQ_CTRL, 0x00},
{MAX98373_R2014_THERM_WARN_THRESH, 0x10},
{MAX98373_R2015_THERM_SHDN_THRESH, 0x27},
{MAX98373_R2016_THERM_HYSTERESIS, 0x01},
{MAX98373_R2017_THERM_FOLDBACK_SET, 0xC0},
{MAX98373_R2018_THERM_FOLDBACK_EN, 0x00},
{MAX98373_R201E_PIN_DRIVE_STRENGTH, 0x55},
{MAX98373_R2020_PCM_TX_HIZ_EN_1, 0xFE},
{MAX98373_R2021_PCM_TX_HIZ_EN_2, 0xFF},
{MAX98373_R2022_PCM_TX_SRC_1, 0x00},
{MAX98373_R2023_PCM_TX_SRC_2, 0x00},
{MAX98373_R2024_PCM_DATA_FMT_CFG, 0xC0},
{MAX98373_R2025_AUDIO_IF_MODE, 0x00},
{MAX98373_R2026_PCM_CLOCK_RATIO, 0x04},
{MAX98373_R2027_PCM_SR_SETUP_1, 0x08},
{MAX98373_R2028_PCM_SR_SETUP_2, 0x88},
{MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1, 0x00},
{MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2, 0x00},
{MAX98373_R202B_PCM_RX_EN, 0x00},
{MAX98373_R202C_PCM_TX_EN, 0x00},
{MAX98373_R202E_ICC_RX_CH_EN_1, 0x00},
{MAX98373_R202F_ICC_RX_CH_EN_2, 0x00},
{MAX98373_R2030_ICC_TX_HIZ_EN_1, 0xFF},
{MAX98373_R2031_ICC_TX_HIZ_EN_2, 0xFF},
{MAX98373_R2032_ICC_LINK_EN_CFG, 0x30},
{MAX98373_R2034_ICC_TX_CNTL, 0x00},
{MAX98373_R2035_ICC_TX_EN, 0x00},
{MAX98373_R2036_SOUNDWIRE_CTRL, 0x05},
{MAX98373_R203D_AMP_DIG_VOL_CTRL, 0x00},
{MAX98373_R203E_AMP_PATH_GAIN, 0x08},
{MAX98373_R203F_AMP_DSP_CFG, 0x02},
{MAX98373_R2040_TONE_GEN_CFG, 0x00},
{MAX98373_R2041_AMP_CFG, 0x03},
{MAX98373_R2042_AMP_EDGE_RATE_CFG, 0x00},
{MAX98373_R2043_AMP_EN, 0x00},
{MAX98373_R2046_IV_SENSE_ADC_DSP_CFG, 0x04},
{MAX98373_R2047_IV_SENSE_ADC_EN, 0x00},
{MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0x00},
{MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG, 0x00},
{MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG, 0x00},
{MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0x00},
{MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0x00},
{MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0x00},
{MAX98373_R2090_BDE_LVL_HOLD, 0x00},
{MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0x00},
{MAX98373_R2092_BDE_CLIPPER_MODE, 0x00},
{MAX98373_R2097_BDE_L1_THRESH, 0x00},
{MAX98373_R2098_BDE_L2_THRESH, 0x00},
{MAX98373_R2099_BDE_L3_THRESH, 0x00},
{MAX98373_R209A_BDE_L4_THRESH, 0x00},
{MAX98373_R209B_BDE_THRESH_HYST, 0x00},
{MAX98373_R20A8_BDE_L1_CFG_1, 0x00},
{MAX98373_R20A9_BDE_L1_CFG_2, 0x00},
{MAX98373_R20AA_BDE_L1_CFG_3, 0x00},
{MAX98373_R20AB_BDE_L2_CFG_1, 0x00},
{MAX98373_R20AC_BDE_L2_CFG_2, 0x00},
{MAX98373_R20AD_BDE_L2_CFG_3, 0x00},
{MAX98373_R20AE_BDE_L3_CFG_1, 0x00},
{MAX98373_R20AF_BDE_L3_CFG_2, 0x00},
{MAX98373_R20B0_BDE_L3_CFG_3, 0x00},
{MAX98373_R20B1_BDE_L4_CFG_1, 0x00},
{MAX98373_R20B2_BDE_L4_CFG_2, 0x00},
{MAX98373_R20B3_BDE_L4_CFG_3, 0x00},
{MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE, 0x00},
{MAX98373_R20B5_BDE_EN, 0x00},
{MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0x00},
{MAX98373_R20D1_DHT_CFG, 0x01},
{MAX98373_R20D2_DHT_ATTACK_CFG, 0x02},
{MAX98373_R20D3_DHT_RELEASE_CFG, 0x03},
{MAX98373_R20D4_DHT_EN, 0x00},
{MAX98373_R20E0_LIMITER_THRESH_CFG, 0x00},
{MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0x00},
{MAX98373_R20E2_LIMITER_EN, 0x00},
{MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG, 0x00},
{MAX98373_R20FF_GLOBAL_SHDN, 0x00},
{MAX98373_R21FF_REV_ID, 0x42},
};
static int max98373_dai_set_fmt(struct snd_soc_dai *codec_dai, unsigned int fmt)
{
struct snd_soc_codec *codec = codec_dai->codec;
struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
unsigned int format = 0;
unsigned int invert = 0;
dev_dbg(codec->dev, "%s: fmt 0x%08X\n", __func__, fmt);
switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
case SND_SOC_DAIFMT_NB_NF:
break;
case SND_SOC_DAIFMT_IB_NF:
invert = MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE;
break;
default:
dev_err(codec->dev, "DAI invert mode unsupported\n");
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2026_PCM_CLOCK_RATIO,
MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE,
invert);
/* interface format */
switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
case SND_SOC_DAIFMT_I2S:
format = MAX98373_PCM_FORMAT_I2S;
break;
case SND_SOC_DAIFMT_LEFT_J:
format = MAX98373_PCM_FORMAT_LJ;
break;
case SND_SOC_DAIFMT_DSP_A:
format = MAX98373_PCM_FORMAT_TDM_MODE1;
break;
case SND_SOC_DAIFMT_DSP_B:
format = MAX98373_PCM_FORMAT_TDM_MODE0;
break;
default:
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_MODE_CFG_FORMAT_MASK,
format << MAX98373_PCM_MODE_CFG_FORMAT_SHIFT);
return 0;
}
/* BCLKs per LRCLK */
static const int bclk_sel_table[] = {
32, 48, 64, 96, 128, 192, 256, 384, 512, 320,
};
static int max98373_get_bclk_sel(int bclk)
{
int i;
/* match BCLKs per LRCLK */
for (i = 0; i < ARRAY_SIZE(bclk_sel_table); i++) {
if (bclk_sel_table[i] == bclk)
return i + 2;
}
return 0;
}
static int max98373_set_clock(struct snd_soc_codec *codec,
struct snd_pcm_hw_params *params)
{
struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
/* BCLK/LRCLK ratio calculation */
int blr_clk_ratio = params_channels(params) * max98373->ch_size;
int value;
if (!max98373->tdm_mode) {
/* BCLK configuration */
value = max98373_get_bclk_sel(blr_clk_ratio);
if (!value) {
dev_err(codec->dev, "format unsupported %d\n",
params_format(params));
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2026_PCM_CLOCK_RATIO,
MAX98373_PCM_CLK_SETUP_BSEL_MASK,
value);
}
return 0;
}
static int max98373_dai_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
{
struct snd_soc_codec *codec = dai->codec;
struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
unsigned int sampling_rate = 0;
unsigned int chan_sz = 0;
/* pcm mode configuration */
switch (snd_pcm_format_width(params_format(params))) {
case 16:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(codec->dev, "format unsupported %d\n",
params_format(params));
goto err;
}
max98373->ch_size = snd_pcm_format_width(params_format(params));
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
dev_dbg(codec->dev, "format supported %d",
params_format(params));
/* sampling rate configuration */
switch (params_rate(params)) {
case 8000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_8000;
break;
case 11025:
sampling_rate = MAX98373_PCM_SR_SET1_SR_11025;
break;
case 12000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_12000;
break;
case 16000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_16000;
break;
case 22050:
sampling_rate = MAX98373_PCM_SR_SET1_SR_22050;
break;
case 24000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_24000;
break;
case 32000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_32000;
break;
case 44100:
sampling_rate = MAX98373_PCM_SR_SET1_SR_44100;
break;
case 48000:
sampling_rate = MAX98373_PCM_SR_SET1_SR_48000;
break;
default:
dev_err(codec->dev, "rate %d not supported\n",
params_rate(params));
goto err;
}
/* set DAI_SR to correct LRCLK frequency */
regmap_update_bits(max98373->regmap,
MAX98373_R2027_PCM_SR_SETUP_1,
MAX98373_PCM_SR_SET1_SR_MASK,
sampling_rate);
regmap_update_bits(max98373->regmap,
MAX98373_R2028_PCM_SR_SETUP_2,
MAX98373_PCM_SR_SET2_SR_MASK,
sampling_rate << MAX98373_PCM_SR_SET2_SR_SHIFT);
/* set sampling rate of IV */
if (max98373->interleave_mode &&
sampling_rate > MAX98373_PCM_SR_SET1_SR_16000)
regmap_update_bits(max98373->regmap,
MAX98373_R2028_PCM_SR_SETUP_2,
MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
sampling_rate - 3);
else
regmap_update_bits(max98373->regmap,
MAX98373_R2028_PCM_SR_SETUP_2,
MAX98373_PCM_SR_SET2_IVADC_SR_MASK,
sampling_rate);
return max98373_set_clock(codec, params);
err:
return -EINVAL;
}
static int max98373_dai_tdm_slot(struct snd_soc_dai *dai,
unsigned int tx_mask, unsigned int rx_mask,
int slots, int slot_width)
{
struct snd_soc_codec *codec = dai->codec;
struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
int bsel = 0;
unsigned int chan_sz = 0;
unsigned int mask;
int x, slot_found;
if (!tx_mask && !rx_mask && !slots && !slot_width)
max98373->tdm_mode = false;
else
max98373->tdm_mode = true;
/* BCLK configuration */
bsel = max98373_get_bclk_sel(slots * slot_width);
if (bsel == 0) {
dev_err(codec->dev, "BCLK %d not supported\n",
slots * slot_width);
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2026_PCM_CLOCK_RATIO,
MAX98373_PCM_CLK_SETUP_BSEL_MASK,
bsel);
/* Channel size configuration */
switch (slot_width) {
case 16:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_16;
break;
case 24:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_24;
break;
case 32:
chan_sz = MAX98373_PCM_MODE_CFG_CHANSZ_32;
break;
default:
dev_err(codec->dev, "format unsupported %d\n",
slot_width);
return -EINVAL;
}
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_MODE_CFG_CHANSZ_MASK, chan_sz);
/* Rx slot configuration */
slot_found = 0;
mask = rx_mask;
for (x = 0 ; x < 16 ; x++, mask >>= 1) {
if (mask & 0x1) {
if (slot_found == 0)
regmap_update_bits(max98373->regmap,
MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
MAX98373_PCM_TO_SPK_CH0_SRC_MASK, x);
else
regmap_write(max98373->regmap,
MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
x);
slot_found++;
if (slot_found > 1)
break;
}
}
/* Tx slot Hi-Z configuration */
regmap_write(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
~tx_mask & 0xFF);
regmap_write(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
(~tx_mask & 0xFF00) >> 8);
return 0;
}
#define MAX98373_RATES SNDRV_PCM_RATE_8000_96000
#define MAX98373_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S32_LE)
static const struct snd_soc_dai_ops max98373_dai_ops = {
.set_fmt = max98373_dai_set_fmt,
.hw_params = max98373_dai_hw_params,
.set_tdm_slot = max98373_dai_tdm_slot,
};
static int max98373_dac_event(struct snd_soc_dapm_widget *w,
struct snd_kcontrol *kcontrol, int event)
{
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm);
struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
switch (event) {
case SND_SOC_DAPM_POST_PMU:
regmap_update_bits(max98373->regmap,
MAX98373_R20FF_GLOBAL_SHDN,
MAX98373_GLOBAL_EN_MASK, 1);
break;
case SND_SOC_DAPM_POST_PMD:
regmap_update_bits(max98373->regmap,
MAX98373_R20FF_GLOBAL_SHDN,
MAX98373_GLOBAL_EN_MASK, 0);
max98373->tdm_mode = 0;
break;
default:
return 0;
}
return 0;
}
static const char * const max98373_switch_text[] = {
"Left", "Right", "LeftRight"};
static const struct soc_enum dai_sel_enum =
SOC_ENUM_SINGLE(MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT,
3, max98373_switch_text);
static const struct snd_kcontrol_new max98373_dai_controls =
SOC_DAPM_ENUM("DAI Sel", dai_sel_enum);
static const struct snd_kcontrol_new max98373_vi_control =
SOC_DAPM_SINGLE("Switch", MAX98373_R202C_PCM_TX_EN, 0, 1, 0);
static const struct snd_kcontrol_new max98373_spkfb_control =
SOC_DAPM_SINGLE("Switch", MAX98373_R2043_AMP_EN, 1, 1, 0);
static const struct snd_soc_dapm_widget max98373_dapm_widgets[] = {
SND_SOC_DAPM_DAC_E("Amp Enable", "HiFi Playback",
MAX98373_R202B_PCM_RX_EN, 0, 0, max98373_dac_event,
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD),
SND_SOC_DAPM_MUX("DAI Sel Mux", SND_SOC_NOPM, 0, 0,
&max98373_dai_controls),
SND_SOC_DAPM_OUTPUT("BE_OUT"),
SND_SOC_DAPM_AIF_OUT("Voltage Sense", "HiFi Capture", 0,
MAX98373_R2047_IV_SENSE_ADC_EN, 0, 0),
SND_SOC_DAPM_AIF_OUT("Current Sense", "HiFi Capture", 0,
MAX98373_R2047_IV_SENSE_ADC_EN, 1, 0),
SND_SOC_DAPM_AIF_OUT("Speaker FB Sense", "HiFi Capture", 0,
SND_SOC_NOPM, 0, 0),
SND_SOC_DAPM_SWITCH("VI Sense", SND_SOC_NOPM, 0, 0,
&max98373_vi_control),
SND_SOC_DAPM_SWITCH("SpkFB Sense", SND_SOC_NOPM, 0, 0,
&max98373_spkfb_control),
SND_SOC_DAPM_SIGGEN("VMON"),
SND_SOC_DAPM_SIGGEN("IMON"),
SND_SOC_DAPM_SIGGEN("FBMON"),
};
static DECLARE_TLV_DB_SCALE(max98373_digital_tlv, 0, -50, 0);
static const DECLARE_TLV_DB_RANGE(max98373_spk_tlv,
0, 8, TLV_DB_SCALE_ITEM(0, 50, 0),
9, 10, TLV_DB_SCALE_ITEM(500, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_spkgain_max_tlv,
0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_dht_step_size_tlv,
0, 1, TLV_DB_SCALE_ITEM(25, 25, 0),
2, 4, TLV_DB_SCALE_ITEM(100, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_dht_spkgain_min_tlv,
0, 9, TLV_DB_SCALE_ITEM(800, 100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_dht_rotation_point_tlv,
0, 1, TLV_DB_SCALE_ITEM(-50, -50, 0),
2, 7, TLV_DB_SCALE_ITEM(-200, -100, 0),
8, 9, TLV_DB_SCALE_ITEM(-1000, -200, 0),
10, 11, TLV_DB_SCALE_ITEM(-1500, -300, 0),
12, 13, TLV_DB_SCALE_ITEM(-2000, -200, 0),
14, 15, TLV_DB_SCALE_ITEM(-2500, -500, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_limiter_thresh_tlv,
0, 15, TLV_DB_SCALE_ITEM(0, -100, 0),
);
static const DECLARE_TLV_DB_RANGE(max98373_bde_gain_tlv,
0, 60, TLV_DB_SCALE_ITEM(0, -25, 0),
);
static bool max98373_readable_register(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98373_R2001_INT_RAW1 ... MAX98373_R200C_INT_EN3:
case MAX98373_R2010_IRQ_CTRL:
case MAX98373_R2014_THERM_WARN_THRESH
... MAX98373_R2018_THERM_FOLDBACK_EN:
case MAX98373_R201E_PIN_DRIVE_STRENGTH
... MAX98373_R2036_SOUNDWIRE_CTRL:
case MAX98373_R203D_AMP_DIG_VOL_CTRL ... MAX98373_R2043_AMP_EN:
case MAX98373_R2046_IV_SENSE_ADC_DSP_CFG
... MAX98373_R2047_IV_SENSE_ADC_EN:
case MAX98373_R2051_MEAS_ADC_SAMPLING_RATE
... MAX98373_R2056_MEAS_ADC_PVDD_CH_EN:
case MAX98373_R2090_BDE_LVL_HOLD ... MAX98373_R2092_BDE_CLIPPER_MODE:
case MAX98373_R2097_BDE_L1_THRESH
... MAX98373_R209B_BDE_THRESH_HYST:
case MAX98373_R20A8_BDE_L1_CFG_1 ... MAX98373_R20B3_BDE_L4_CFG_3:
case MAX98373_R20B5_BDE_EN ... MAX98373_R20B6_BDE_CUR_STATE_READBACK:
case MAX98373_R20D1_DHT_CFG ... MAX98373_R20D4_DHT_EN:
case MAX98373_R20E0_LIMITER_THRESH_CFG ... MAX98373_R20E2_LIMITER_EN:
case MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG
... MAX98373_R20FF_GLOBAL_SHDN:
case MAX98373_R21FF_REV_ID:
return true;
default:
return false;
}
};
static bool max98373_volatile_reg(struct device *dev, unsigned int reg)
{
switch (reg) {
case MAX98373_R2000_SW_RESET ... MAX98373_R2009_INT_FLAG3:
case MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK:
case MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK:
case MAX98373_R20B6_BDE_CUR_STATE_READBACK:
case MAX98373_R21FF_REV_ID:
return true;
default:
return false;
}
}
static const char * const max98373_output_voltage_lvl_text[] = {
"5.43V", "6.09V", "6.83V", "7.67V", "8.60V",
"9.65V", "10.83V", "12.15V", "13.63V", "15.29V"
};
static SOC_ENUM_SINGLE_DECL(max98373_out_volt_enum,
MAX98373_R203E_AMP_PATH_GAIN, 0,
max98373_output_voltage_lvl_text);
static const char * const max98373_dht_attack_rate_text[] = {
"17.5us", "35us", "70us", "140us",
"280us", "560us", "1120us", "2240us"
};
static SOC_ENUM_SINGLE_DECL(max98373_dht_attack_rate_enum,
MAX98373_R20D2_DHT_ATTACK_CFG, 0,
max98373_dht_attack_rate_text);
static const char * const max98373_dht_release_rate_text[] = {
"45ms", "225ms", "450ms", "1150ms",
"2250ms", "3100ms", "4500ms", "6750ms"
};
static SOC_ENUM_SINGLE_DECL(max98373_dht_release_rate_enum,
MAX98373_R20D3_DHT_RELEASE_CFG, 0,
max98373_dht_release_rate_text);
static const char * const max98373_limiter_attack_rate_text[] = {
"10us", "20us", "40us", "80us",
"160us", "320us", "640us", "1.28ms",
"2.56ms", "5.12ms", "10.24ms", "20.48ms",
"40.96ms", "81.92ms", "16.384ms", "32.768ms"
};
static SOC_ENUM_SINGLE_DECL(max98373_limiter_attack_rate_enum,
MAX98373_R20E1_LIMITER_ATK_REL_RATES, 4,
max98373_limiter_attack_rate_text);
static const char * const max98373_limiter_release_rate_text[] = {
"40us", "80us", "160us", "320us",
"640us", "1.28ms", "2.56ms", "5.120ms",
"10.24ms", "20.48ms", "40.96ms", "81.92ms",
"163.84ms", "327.68ms", "655.36ms", "1310.72ms"
};
static SOC_ENUM_SINGLE_DECL(max98373_limiter_release_rate_enum,
MAX98373_R20E1_LIMITER_ATK_REL_RATES, 0,
max98373_limiter_release_rate_text);
static const char * const max98373_ADC_samplerate_text[] = {
"333kHz", "192kHz", "64kHz", "48kHz"
};
static SOC_ENUM_SINGLE_DECL(max98373_adc_samplerate_enum,
MAX98373_R2051_MEAS_ADC_SAMPLING_RATE, 0,
max98373_ADC_samplerate_text);
static const struct snd_kcontrol_new max98373_snd_controls[] = {
SOC_SINGLE("Digital Vol Sel Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
SOC_SINGLE("Volume Location Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_VOL_SEL_SHIFT, 1, 0),
SOC_SINGLE("Ramp Up Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT, 1, 0),
SOC_SINGLE("Ramp Down Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT, 1, 0),
SOC_SINGLE("CLK Monitor Switch", MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG,
MAX98373_CLOCK_MON_SHIFT, 1, 0),
SOC_SINGLE("Dither Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_DSP_CFG_DITH_SHIFT, 1, 0),
SOC_SINGLE("DC Blocker Switch", MAX98373_R203F_AMP_DSP_CFG,
MAX98373_AMP_DSP_CFG_DCBLK_SHIFT, 1, 0),
SOC_SINGLE_TLV("Digital Volume", MAX98373_R203D_AMP_DIG_VOL_CTRL,
0, 0x7F, 0, max98373_digital_tlv),
SOC_SINGLE_TLV("Speaker Volume", MAX98373_R203E_AMP_PATH_GAIN,
MAX98373_SPK_DIGI_GAIN_SHIFT, 10, 0, max98373_spk_tlv),
SOC_SINGLE_TLV("FS Max Volume", MAX98373_R203E_AMP_PATH_GAIN,
MAX98373_FS_GAIN_MAX_SHIFT, 9, 0, max98373_spkgain_max_tlv),
SOC_ENUM("Output Voltage", max98373_out_volt_enum),
/* Dynamic Headroom Tracking */
SOC_SINGLE("DHT Switch", MAX98373_R20D4_DHT_EN,
MAX98373_DHT_EN_SHIFT, 1, 0),
SOC_SINGLE_TLV("DHT Min Volume", MAX98373_R20D1_DHT_CFG,
MAX98373_DHT_SPK_GAIN_MIN_SHIFT, 9, 0, max98373_dht_spkgain_min_tlv),
SOC_SINGLE_TLV("DHT Rot Pnt Volume", MAX98373_R20D1_DHT_CFG,
MAX98373_DHT_ROT_PNT_SHIFT, 15, 0, max98373_dht_rotation_point_tlv),
SOC_SINGLE_TLV("DHT Attack Step Volume", MAX98373_R20D2_DHT_ATTACK_CFG,
MAX98373_DHT_ATTACK_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
SOC_SINGLE_TLV("DHT Release Step Volume", MAX98373_R20D3_DHT_RELEASE_CFG,
MAX98373_DHT_RELEASE_STEP_SHIFT, 4, 0, max98373_dht_step_size_tlv),
SOC_ENUM("DHT Attack Rate", max98373_dht_attack_rate_enum),
SOC_ENUM("DHT Release Rate", max98373_dht_release_rate_enum),
/* ADC configuration */
SOC_SINGLE("ADC PVDD CH Switch", MAX98373_R2056_MEAS_ADC_PVDD_CH_EN, 0, 1, 0),
SOC_SINGLE("ADC PVDD FLT Switch", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
MAX98373_FLT_EN_SHIFT, 1, 0),
SOC_SINGLE("ADC TEMP FLT Switch", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
MAX98373_FLT_EN_SHIFT, 1, 0),
SOC_SINGLE("ADC PVDD", MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK, 0, 0xFF, 0),
SOC_SINGLE("ADC TEMP", MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK, 0, 0xFF, 0),
SOC_SINGLE("ADC PVDD FLT Coeff", MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG,
0, 0x3, 0),
SOC_SINGLE("ADC TEMP FLT Coeff", MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG,
0, 0x3, 0),
SOC_ENUM("ADC SampleRate", max98373_adc_samplerate_enum),
/* Brownout Detection Engine */
SOC_SINGLE("BDE Switch", MAX98373_R20B5_BDE_EN, MAX98373_BDE_EN_SHIFT, 1, 0),
SOC_SINGLE("BDE LVL4 Mute Switch", MAX98373_R20B2_BDE_L4_CFG_2,
MAX98373_LVL4_MUTE_EN_SHIFT, 1, 0),
SOC_SINGLE("BDE LVL4 Hold Switch", MAX98373_R20B2_BDE_L4_CFG_2,
MAX98373_LVL4_HOLD_EN_SHIFT, 1, 0),
SOC_SINGLE("BDE LVL1 Thresh", MAX98373_R2097_BDE_L1_THRESH, 0, 0xFF, 0),
SOC_SINGLE("BDE LVL2 Thresh", MAX98373_R2098_BDE_L2_THRESH, 0, 0xFF, 0),
SOC_SINGLE("BDE LVL3 Thresh", MAX98373_R2099_BDE_L3_THRESH, 0, 0xFF, 0),
SOC_SINGLE("BDE LVL4 Thresh", MAX98373_R209A_BDE_L4_THRESH, 0, 0xFF, 0),
SOC_SINGLE("BDE Active Level", MAX98373_R20B6_BDE_CUR_STATE_READBACK, 0, 8, 0),
SOC_SINGLE("BDE Clip Mode Switch", MAX98373_R2092_BDE_CLIPPER_MODE, 0, 1, 0),
SOC_SINGLE("BDE Thresh Hysteresis", MAX98373_R209B_BDE_THRESH_HYST, 0, 0xFF, 0),
SOC_SINGLE("BDE Hold Time", MAX98373_R2090_BDE_LVL_HOLD, 0, 0xFF, 0),
SOC_SINGLE("BDE Attack Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 4, 0xF, 0),
SOC_SINGLE("BDE Release Rate", MAX98373_R2091_BDE_GAIN_ATK_REL_RATE, 0, 0xF, 0),
SOC_SINGLE_TLV("BDE LVL1 Clip Thresh Volume", MAX98373_R20A9_BDE_L1_CFG_2,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL2 Clip Thresh Volume", MAX98373_R20AC_BDE_L2_CFG_2,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL3 Clip Thresh Volume", MAX98373_R20AF_BDE_L3_CFG_2,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL4 Clip Thresh Volume", MAX98373_R20B2_BDE_L4_CFG_2,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL1 Clip Reduction Volume", MAX98373_R20AA_BDE_L1_CFG_3,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL2 Clip Reduction Volume", MAX98373_R20AD_BDE_L2_CFG_3,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL3 Clip Reduction Volume", MAX98373_R20B0_BDE_L3_CFG_3,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL4 Clip Reduction Volume", MAX98373_R20B3_BDE_L4_CFG_3,
0, 0x3C, 0, max98373_bde_gain_tlv),
SOC_SINGLE_TLV("BDE LVL1 Limiter Thresh Volume", MAX98373_R20A8_BDE_L1_CFG_1,
0, 0xF, 0, max98373_limiter_thresh_tlv),
SOC_SINGLE_TLV("BDE LVL2 Limiter Thresh Volume", MAX98373_R20AB_BDE_L2_CFG_1,
0, 0xF, 0, max98373_limiter_thresh_tlv),
SOC_SINGLE_TLV("BDE LVL3 Limiter Thresh Volume", MAX98373_R20AE_BDE_L3_CFG_1,
0, 0xF, 0, max98373_limiter_thresh_tlv),
SOC_SINGLE_TLV("BDE LVL4 Limiter Thresh Volume", MAX98373_R20B1_BDE_L4_CFG_1,
0, 0xF, 0, max98373_limiter_thresh_tlv),
/* Limiter */
SOC_SINGLE("Limiter Switch", MAX98373_R20E2_LIMITER_EN,
MAX98373_LIMITER_EN_SHIFT, 1, 0),
SOC_SINGLE("Limiter Src Switch", MAX98373_R20E0_LIMITER_THRESH_CFG,
MAX98373_LIMITER_THRESH_SRC_SHIFT, 1, 0),
SOC_SINGLE_TLV("Limiter Thresh Volume", MAX98373_R20E0_LIMITER_THRESH_CFG,
MAX98373_LIMITER_THRESH_SHIFT, 15, 0, max98373_limiter_thresh_tlv),
SOC_ENUM("Limiter Attack Rate", max98373_limiter_attack_rate_enum),
SOC_ENUM("Limiter Release Rate", max98373_limiter_release_rate_enum),
};
static const struct snd_soc_dapm_route max98373_audio_map[] = {
/* Plabyack */
{"DAI Sel Mux", "Left", "Amp Enable"},
{"DAI Sel Mux", "Right", "Amp Enable"},
{"DAI Sel Mux", "LeftRight", "Amp Enable"},
{"BE_OUT", NULL, "DAI Sel Mux"},
/* Capture */
{ "VI Sense", "Switch", "VMON" },
{ "VI Sense", "Switch", "IMON" },
{ "SpkFB Sense", "Switch", "FBMON" },
{ "Voltage Sense", NULL, "VI Sense" },
{ "Current Sense", NULL, "VI Sense" },
{ "Speaker FB Sense", NULL, "SpkFB Sense" },
};
static struct snd_soc_dai_driver max98373_dai[] = {
{
.name = "max98373-aif1",
.playback = {
.stream_name = "HiFi Playback",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98373_RATES,
.formats = MAX98373_FORMATS,
},
.capture = {
.stream_name = "HiFi Capture",
.channels_min = 1,
.channels_max = 2,
.rates = MAX98373_RATES,
.formats = MAX98373_FORMATS,
},
.ops = &max98373_dai_ops,
}
};
static int max98373_probe(struct snd_soc_codec *codec)
{
struct max98373_priv *max98373 = snd_soc_codec_get_drvdata(codec);
codec->control_data = max98373->regmap;
/* Software Reset */
regmap_write(max98373->regmap,
MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET);
/* IV default slot configuration */
regmap_write(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
0xFF);
regmap_write(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
0xFF);
/* L/R mix configuration */
regmap_write(max98373->regmap,
MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1,
0x80);
regmap_write(max98373->regmap,
MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2,
0x1);
/* Set inital volume (0dB) */
regmap_write(max98373->regmap,
MAX98373_R203D_AMP_DIG_VOL_CTRL,
0x00);
regmap_write(max98373->regmap,
MAX98373_R203E_AMP_PATH_GAIN,
0x00);
/* Enable DC blocker */
regmap_write(max98373->regmap,
MAX98373_R203F_AMP_DSP_CFG,
0x3);
/* Enable IMON VMON DC blocker */
regmap_write(max98373->regmap,
MAX98373_R2046_IV_SENSE_ADC_DSP_CFG,
0x7);
/* voltage, current slot configuration */
regmap_write(max98373->regmap,
MAX98373_R2022_PCM_TX_SRC_1,
(max98373->i_slot << MAX98373_PCM_TX_CH_SRC_A_I_SHIFT |
max98373->v_slot) & 0xFF);
if (max98373->v_slot < 8)
regmap_update_bits(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
1 << max98373->v_slot, 0);
else
regmap_update_bits(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
1 << (max98373->v_slot - 8), 0);
if (max98373->i_slot < 8)
regmap_update_bits(max98373->regmap,
MAX98373_R2020_PCM_TX_HIZ_EN_1,
1 << max98373->i_slot, 0);
else
regmap_update_bits(max98373->regmap,
MAX98373_R2021_PCM_TX_HIZ_EN_2,
1 << (max98373->i_slot - 8), 0);
/* speaker feedback slot configuration */
regmap_write(max98373->regmap,
MAX98373_R2023_PCM_TX_SRC_2,
max98373->spkfb_slot & 0xFF);
/* Set interleave mode */
if (max98373->interleave_mode)
regmap_update_bits(max98373->regmap,
MAX98373_R2024_PCM_DATA_FMT_CFG,
MAX98373_PCM_TX_CH_INTERLEAVE_MASK,
MAX98373_PCM_TX_CH_INTERLEAVE_MASK);
/* Speaker enable */
regmap_update_bits(max98373->regmap,
MAX98373_R2043_AMP_EN,
MAX98373_SPK_EN_MASK, 1);
return 0;
}
#ifdef CONFIG_PM_SLEEP
static int max98373_suspend(struct device *dev)
{
struct max98373_priv *max98373 = dev_get_drvdata(dev);
regcache_cache_only(max98373->regmap, true);
regcache_mark_dirty(max98373->regmap);
return 0;
}
static int max98373_resume(struct device *dev)
{
struct max98373_priv *max98373 = dev_get_drvdata(dev);
regmap_write(max98373->regmap,
MAX98373_R2000_SW_RESET, MAX98373_SOFT_RESET);
regcache_cache_only(max98373->regmap, false);
regcache_sync(max98373->regmap);
return 0;
}
#endif
static const struct dev_pm_ops max98373_pm = {
SET_SYSTEM_SLEEP_PM_OPS(max98373_suspend, max98373_resume)
};
static const struct snd_soc_codec_driver soc_codec_dev_max98373 = {
.probe = max98373_probe,
.component_driver = {
.controls = max98373_snd_controls,
.num_controls = ARRAY_SIZE(max98373_snd_controls),
.dapm_widgets = max98373_dapm_widgets,
.num_dapm_widgets = ARRAY_SIZE(max98373_dapm_widgets),
.dapm_routes = max98373_audio_map,
.num_dapm_routes = ARRAY_SIZE(max98373_audio_map),
},
};
static const struct regmap_config max98373_regmap = {
.reg_bits = 16,
.val_bits = 8,
.max_register = MAX98373_R21FF_REV_ID,
.reg_defaults = max98373_reg,
.num_reg_defaults = ARRAY_SIZE(max98373_reg),
.readable_reg = max98373_readable_register,
.volatile_reg = max98373_volatile_reg,
.cache_type = REGCACHE_RBTREE,
};
static void max98373_slot_config(struct i2c_client *i2c,
struct max98373_priv *max98373)
{
int value;
struct device *dev = &i2c->dev;
if (!device_property_read_u32(dev, "maxim,vmon-slot-no", &value))
max98373->v_slot = value & 0xF;
else
max98373->v_slot = 0;
if (!device_property_read_u32(dev, "maxim,imon-slot-no", &value))
max98373->i_slot = value & 0xF;
else
max98373->i_slot = 1;
if (!device_property_read_u32(dev, "maxim,spkfb-slot-no", &value))
max98373->spkfb_slot = value & 0xF;
else
max98373->spkfb_slot = 2;
}
static int max98373_i2c_probe(struct i2c_client *i2c,
const struct i2c_device_id *id)
{
int ret = 0;
int reg = 0;
struct max98373_priv *max98373 = NULL;
max98373 = devm_kzalloc(&i2c->dev, sizeof(*max98373), GFP_KERNEL);
if (!max98373) {
ret = -ENOMEM;
return ret;
}
i2c_set_clientdata(i2c, max98373);
/* update interleave mode info */
if (device_property_read_bool(&i2c->dev, "maxim,interleave_mode"))
max98373->interleave_mode = 1;
else
max98373->interleave_mode = 0;
/* regmap initialization */
max98373->regmap
= devm_regmap_init_i2c(i2c, &max98373_regmap);
if (IS_ERR(max98373->regmap)) {
ret = PTR_ERR(max98373->regmap);
dev_err(&i2c->dev,
"Failed to allocate regmap: %d\n", ret);
return ret;
}
/* Check Revision ID */
ret = regmap_read(max98373->regmap,
MAX98373_R21FF_REV_ID, &reg);
if (ret < 0) {
dev_err(&i2c->dev,
"Failed to read: 0x%02X\n", MAX98373_R21FF_REV_ID);
return ret;
}
dev_info(&i2c->dev, "MAX98373 revisionID: 0x%02X\n", reg);
/* voltage/current slot configuration */
max98373_slot_config(i2c, max98373);
/* codec registeration */
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_max98373,
max98373_dai, ARRAY_SIZE(max98373_dai));
if (ret < 0)
dev_err(&i2c->dev, "Failed to register codec: %d\n", ret);
return ret;
}
static int max98373_i2c_remove(struct i2c_client *client)
{
snd_soc_unregister_codec(&client->dev);
return 0;
}
static const struct i2c_device_id max98373_i2c_id[] = {
{ "max98373", 0},
{ },
};
MODULE_DEVICE_TABLE(i2c, max98373_i2c_id);
#if defined(CONFIG_OF)
static const struct of_device_id max98373_of_match[] = {
{ .compatible = "maxim,max98373", },
{ }
};
MODULE_DEVICE_TABLE(of, max98373_of_match);
#endif
#ifdef CONFIG_ACPI
static const struct acpi_device_id max98373_acpi_match[] = {
{ "MX98373", 0 },
{},
};
MODULE_DEVICE_TABLE(acpi, max98373_acpi_match);
#endif
static struct i2c_driver max98373_i2c_driver = {
.driver = {
.name = "max98373",
.of_match_table = of_match_ptr(max98373_of_match),
.acpi_match_table = ACPI_PTR(max98373_acpi_match),
.pm = &max98373_pm,
},
.probe = max98373_i2c_probe,
.remove = max98373_i2c_remove,
.id_table = max98373_i2c_id,
};
module_i2c_driver(max98373_i2c_driver)
MODULE_DESCRIPTION("ALSA SoC MAX98373 driver");
MODULE_AUTHOR("Ryan Lee <ryans.lee@maximintegrated.com>");
MODULE_LICENSE("GPL");

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/* SPDX-License-Identifier: GPL-2.0 */
/* Copyright (c) 2017, Maxim Integrated */
#ifndef _MAX98373_H
#define _MAX98373_H
#define MAX98373_R2000_SW_RESET 0x2000
#define MAX98373_R2001_INT_RAW1 0x2001
#define MAX98373_R2002_INT_RAW2 0x2002
#define MAX98373_R2003_INT_RAW3 0x2003
#define MAX98373_R2004_INT_STATE1 0x2004
#define MAX98373_R2005_INT_STATE2 0x2005
#define MAX98373_R2006_INT_STATE3 0x2006
#define MAX98373_R2007_INT_FLAG1 0x2007
#define MAX98373_R2008_INT_FLAG2 0x2008
#define MAX98373_R2009_INT_FLAG3 0x2009
#define MAX98373_R200A_INT_EN1 0x200A
#define MAX98373_R200B_INT_EN2 0x200B
#define MAX98373_R200C_INT_EN3 0x200C
#define MAX98373_R200D_INT_FLAG_CLR1 0x200D
#define MAX98373_R200E_INT_FLAG_CLR2 0x200E
#define MAX98373_R200F_INT_FLAG_CLR3 0x200F
#define MAX98373_R2010_IRQ_CTRL 0x2010
#define MAX98373_R2014_THERM_WARN_THRESH 0x2014
#define MAX98373_R2015_THERM_SHDN_THRESH 0x2015
#define MAX98373_R2016_THERM_HYSTERESIS 0x2016
#define MAX98373_R2017_THERM_FOLDBACK_SET 0x2017
#define MAX98373_R2018_THERM_FOLDBACK_EN 0x2018
#define MAX98373_R201E_PIN_DRIVE_STRENGTH 0x201E
#define MAX98373_R2020_PCM_TX_HIZ_EN_1 0x2020
#define MAX98373_R2021_PCM_TX_HIZ_EN_2 0x2021
#define MAX98373_R2022_PCM_TX_SRC_1 0x2022
#define MAX98373_R2023_PCM_TX_SRC_2 0x2023
#define MAX98373_R2024_PCM_DATA_FMT_CFG 0x2024
#define MAX98373_R2025_AUDIO_IF_MODE 0x2025
#define MAX98373_R2026_PCM_CLOCK_RATIO 0x2026
#define MAX98373_R2027_PCM_SR_SETUP_1 0x2027
#define MAX98373_R2028_PCM_SR_SETUP_2 0x2028
#define MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1 0x2029
#define MAX98373_R202A_PCM_TO_SPK_MONO_MIX_2 0x202A
#define MAX98373_R202B_PCM_RX_EN 0x202B
#define MAX98373_R202C_PCM_TX_EN 0x202C
#define MAX98373_R202E_ICC_RX_CH_EN_1 0x202E
#define MAX98373_R202F_ICC_RX_CH_EN_2 0x202F
#define MAX98373_R2030_ICC_TX_HIZ_EN_1 0x2030
#define MAX98373_R2031_ICC_TX_HIZ_EN_2 0x2031
#define MAX98373_R2032_ICC_LINK_EN_CFG 0x2032
#define MAX98373_R2034_ICC_TX_CNTL 0x2034
#define MAX98373_R2035_ICC_TX_EN 0x2035
#define MAX98373_R2036_SOUNDWIRE_CTRL 0x2036
#define MAX98373_R203D_AMP_DIG_VOL_CTRL 0x203D
#define MAX98373_R203E_AMP_PATH_GAIN 0x203E
#define MAX98373_R203F_AMP_DSP_CFG 0x203F
#define MAX98373_R2040_TONE_GEN_CFG 0x2040
#define MAX98373_R2041_AMP_CFG 0x2041
#define MAX98373_R2042_AMP_EDGE_RATE_CFG 0x2042
#define MAX98373_R2043_AMP_EN 0x2043
#define MAX98373_R2046_IV_SENSE_ADC_DSP_CFG 0x2046
#define MAX98373_R2047_IV_SENSE_ADC_EN 0x2047
#define MAX98373_R2051_MEAS_ADC_SAMPLING_RATE 0x2051
#define MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG 0x2052
#define MAX98373_R2053_MEAS_ADC_THERM_FLT_CFG 0x2053
#define MAX98373_R2054_MEAS_ADC_PVDD_CH_READBACK 0x2054
#define MAX98373_R2055_MEAS_ADC_THERM_CH_READBACK 0x2055
#define MAX98373_R2056_MEAS_ADC_PVDD_CH_EN 0x2056
#define MAX98373_R2090_BDE_LVL_HOLD 0x2090
#define MAX98373_R2091_BDE_GAIN_ATK_REL_RATE 0x2091
#define MAX98373_R2092_BDE_CLIPPER_MODE 0x2092
#define MAX98373_R2097_BDE_L1_THRESH 0x2097
#define MAX98373_R2098_BDE_L2_THRESH 0x2098
#define MAX98373_R2099_BDE_L3_THRESH 0x2099
#define MAX98373_R209A_BDE_L4_THRESH 0x209A
#define MAX98373_R209B_BDE_THRESH_HYST 0x209B
#define MAX98373_R20A8_BDE_L1_CFG_1 0x20A8
#define MAX98373_R20A9_BDE_L1_CFG_2 0x20A9
#define MAX98373_R20AA_BDE_L1_CFG_3 0x20AA
#define MAX98373_R20AB_BDE_L2_CFG_1 0x20AB
#define MAX98373_R20AC_BDE_L2_CFG_2 0x20AC
#define MAX98373_R20AD_BDE_L2_CFG_3 0x20AD
#define MAX98373_R20AE_BDE_L3_CFG_1 0x20AE
#define MAX98373_R20AF_BDE_L3_CFG_2 0x20AF
#define MAX98373_R20B0_BDE_L3_CFG_3 0x20B0
#define MAX98373_R20B1_BDE_L4_CFG_1 0x20B1
#define MAX98373_R20B2_BDE_L4_CFG_2 0x20B2
#define MAX98373_R20B3_BDE_L4_CFG_3 0x20B3
#define MAX98373_R20B4_BDE_INFINITE_HOLD_RELEASE 0x20B4
#define MAX98373_R20B5_BDE_EN 0x20B5
#define MAX98373_R20B6_BDE_CUR_STATE_READBACK 0x20B6
#define MAX98373_R20D1_DHT_CFG 0x20D1
#define MAX98373_R20D2_DHT_ATTACK_CFG 0x20D2
#define MAX98373_R20D3_DHT_RELEASE_CFG 0x20D3
#define MAX98373_R20D4_DHT_EN 0x20D4
#define MAX98373_R20E0_LIMITER_THRESH_CFG 0x20E0
#define MAX98373_R20E1_LIMITER_ATK_REL_RATES 0x20E1
#define MAX98373_R20E2_LIMITER_EN 0x20E2
#define MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG 0x20FE
#define MAX98373_R20FF_GLOBAL_SHDN 0x20FF
#define MAX98373_R21FF_REV_ID 0x21FF
/* MAX98373_R2022_PCM_TX_SRC_1 */
#define MAX98373_PCM_TX_CH_SRC_A_V_SHIFT (0)
#define MAX98373_PCM_TX_CH_SRC_A_I_SHIFT (4)
/* MAX98373_R2024_PCM_DATA_FMT_CFG */
#define MAX98373_PCM_MODE_CFG_FORMAT_MASK (0x7 << 3)
#define MAX98373_PCM_MODE_CFG_FORMAT_SHIFT (3)
#define MAX98373_PCM_TX_CH_INTERLEAVE_MASK (0x1 << 2)
#define MAX98373_PCM_FORMAT_I2S (0x0 << 0)
#define MAX98373_PCM_FORMAT_LJ (0x1 << 0)
#define MAX98373_PCM_FORMAT_TDM_MODE0 (0x3 << 0)
#define MAX98373_PCM_FORMAT_TDM_MODE1 (0x4 << 0)
#define MAX98373_PCM_FORMAT_TDM_MODE2 (0x5 << 0)
#define MAX98373_PCM_MODE_CFG_CHANSZ_MASK (0x3 << 6)
#define MAX98373_PCM_MODE_CFG_CHANSZ_16 (0x1 << 6)
#define MAX98373_PCM_MODE_CFG_CHANSZ_24 (0x2 << 6)
#define MAX98373_PCM_MODE_CFG_CHANSZ_32 (0x3 << 6)
/* MAX98373_R2026_PCM_CLOCK_RATIO */
#define MAX98373_PCM_MODE_CFG_PCM_BCLKEDGE (0x1 << 4)
#define MAX98373_PCM_CLK_SETUP_BSEL_MASK (0xF << 0)
/* MAX98373_R2027_PCM_SR_SETUP_1 */
#define MAX98373_PCM_SR_SET1_SR_MASK (0xF << 0)
#define MAX98373_PCM_SR_SET1_SR_8000 (0x0 << 0)
#define MAX98373_PCM_SR_SET1_SR_11025 (0x1 << 0)
#define MAX98373_PCM_SR_SET1_SR_12000 (0x2 << 0)
#define MAX98373_PCM_SR_SET1_SR_16000 (0x3 << 0)
#define MAX98373_PCM_SR_SET1_SR_22050 (0x4 << 0)
#define MAX98373_PCM_SR_SET1_SR_24000 (0x5 << 0)
#define MAX98373_PCM_SR_SET1_SR_32000 (0x6 << 0)
#define MAX98373_PCM_SR_SET1_SR_44100 (0x7 << 0)
#define MAX98373_PCM_SR_SET1_SR_48000 (0x8 << 0)
/* MAX98373_R2028_PCM_SR_SETUP_2 */
#define MAX98373_PCM_SR_SET2_SR_MASK (0xF << 4)
#define MAX98373_PCM_SR_SET2_SR_SHIFT (4)
#define MAX98373_PCM_SR_SET2_IVADC_SR_MASK (0xF << 0)
/* MAX98373_R2029_PCM_TO_SPK_MONO_MIX_1 */
#define MAX98373_PCM_TO_SPK_MONOMIX_CFG_MASK (0x3 << 6)
#define MAX98373_PCM_TO_SPK_MONOMIX_CFG_SHIFT (6)
#define MAX98373_PCM_TO_SPK_CH0_SRC_MASK (0xF << 0)
/* MAX98373_R203E_AMP_PATH_GAIN */
#define MAX98373_SPK_DIGI_GAIN_MASK (0xF << 4)
#define MAX98373_SPK_DIGI_GAIN_SHIFT (4)
#define MAX98373_FS_GAIN_MAX_MASK (0xF << 0)
#define MAX98373_FS_GAIN_MAX_SHIFT (0)
/* MAX98373_R203F_AMP_DSP_CFG */
#define MAX98373_AMP_DSP_CFG_DCBLK_SHIFT (0)
#define MAX98373_AMP_DSP_CFG_DITH_SHIFT (1)
#define MAX98373_AMP_DSP_CFG_RMP_UP_SHIFT (2)
#define MAX98373_AMP_DSP_CFG_RMP_DN_SHIFT (3)
#define MAX98373_AMP_DSP_CFG_DAC_INV_SHIFT (5)
#define MAX98373_AMP_VOL_SEL_SHIFT (7)
/* MAX98373_R2043_AMP_EN */
#define MAX98373_SPKFB_EN_MASK (0x1 << 1)
#define MAX98373_SPK_EN_MASK (0x1 << 0)
#define MAX98373_SPKFB_EN_SHIFT (1)
/*MAX98373_R2052_MEAS_ADC_PVDD_FLT_CFG */
#define MAX98373_FLT_EN_SHIFT (4)
/* MAX98373_R20B2_BDE_L4_CFG_2 */
#define MAX98373_LVL4_MUTE_EN_SHIFT (7)
#define MAX98373_LVL4_HOLD_EN_SHIFT (6)
/* MAX98373_R20B5_BDE_EN */
#define MAX98373_BDE_EN_SHIFT (0)
/* MAX98373_R20D1_DHT_CFG */
#define MAX98373_DHT_SPK_GAIN_MIN_SHIFT (4)
#define MAX98373_DHT_ROT_PNT_SHIFT (0)
/* MAX98373_R20D2_DHT_ATTACK_CFG */
#define MAX98373_DHT_ATTACK_STEP_SHIFT (3)
#define MAX98373_DHT_ATTACK_RATE_SHIFT (0)
/* MAX98373_R20D3_DHT_RELEASE_CFG */
#define MAX98373_DHT_RELEASE_STEP_SHIFT (3)
#define MAX98373_DHT_RELEASE_RATE_SHIFT (0)
/* MAX98373_R20D4_DHT_EN */
#define MAX98373_DHT_EN_SHIFT (0)
/* MAX98373_R20E0_LIMITER_THRESH_CFG */
#define MAX98373_LIMITER_THRESH_SHIFT (2)
#define MAX98373_LIMITER_THRESH_SRC_SHIFT (0)
/* MAX98373_R20E2_LIMITER_EN */
#define MAX98373_LIMITER_EN_SHIFT (0)
/* MAX98373_R20FE_DEVICE_AUTO_RESTART_CFG */
#define MAX98373_CLOCK_MON_SHIFT (0)
/* MAX98373_R20FF_GLOBAL_SHDN */
#define MAX98373_GLOBAL_EN_MASK (0x1 << 0)
/* MAX98373_R2000_SW_RESET */
#define MAX98373_SOFT_RESET (0x1 << 0)
struct max98373_priv {
struct regmap *regmap;
unsigned int v_slot;
unsigned int i_slot;
unsigned int spkfb_slot;
bool interleave_mode;
unsigned int ch_size;
bool tdm_mode;
};
#endif

1
sound/soc/hisilicon/hi6210-i2s.c
View File

@ -36,7 +36,6 @@
#include <linux/of_irq.h> #include <linux/of_irq.h>
#include <linux/mfd/syscon.h> #include <linux/mfd/syscon.h>
#include <linux/reset-controller.h> #include <linux/reset-controller.h>
#include <linux/clk.h>
#include "hi6210-i2s.h" #include "hi6210-i2s.h"