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ARM: OMAP2+: first set of hwmod fixes and additions for v4.6
A few fixes for OMAP hwmod data. SSI hwmod data for the OMAP 3730, and some fixes for the DRA7xx hwmod data. These shouldn't interfere or impact anything else. Basic build, boot, and PM test logs are available here: http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.6/20160214161224/ -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJWxL3qAAoJEMePsQ0LvSpLN0EP/RIVPdWTdXFXVlYHLf6SMmIs UxACv5uIEbj1kj3VgMNYIKgPLV57rmotoHpSv5oDxg0f53sfj0qcm4MwVkVOxb+2 NkrDqMu5k+l/LSmILCJ1CbttiTxCrfaBESPEt8sPnXSzkGeRJDYQzfS5ZGM7C2qg ms+WQc60rUizSrQgywAn2SRt4Hu/IMxh06UJubnqoUn3TNQa0HPA8IIXKbvEJTxR o65R4Kq4ObjmaPYMNsEYqqhtnY9uDqXWeJrb2wnyXRLVMYv4O50OV7O29wcvJiQ9 HmilOZ1vA2CyqZOflIPt4ovNcngD3dc2wJ5CPEfrUGcr2dji9H/pZjDlAKatnRz+ Xg73Zw8aCd+Rs+Xqk13GpZs3PlsWyNsdTOCuGPOW2BkHIDyMmgWjdRaMx+aYZLMG XSFiEEoMFa3V6U1JpTNI3M6xiME6HDwj8efw1m+oJVYe3V7KsoqfFD02xn6Z0/Qk qupqj1WMPFOq4vorah9NosEQl9ERmZVASySQ5kah0+na3bYmboTV/SlV4oUHtD7H 4ML3WQ82S0v+9GVzux2BT9YZfwUX8T+QZHYhOjLsxgZHajUx128IAJdLuf3fVPm+ u/liLBvnaG0Raj/oKbE/QanP65kf8GTbL8qF7D+Lfj3WloNRq79w6/oc7UtHW0jC HCNTnLg8ynkFcTId9adW =BCT2 -----END PGP SIGNATURE----- Merge tag 'for-v4.6/omap-hwmod-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into omap-for-v4.6/fixes-not-urgent ARM: OMAP2+: first set of hwmod fixes and additions for v4.6 A few fixes for OMAP hwmod data. SSI hwmod data for the OMAP 3730, and some fixes for the DRA7xx hwmod data. These shouldn't interfere or impact anything else. Basic build, boot, and PM test logs are available here: http://www.pwsan.com/omap/testlogs/omap-hwmod-a-for-v4.6/20160214161224/
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commit
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@ -3583,14 +3583,14 @@ static struct omap_hwmod_class_sysconfig omap34xx_ssi_sysc = {
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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static struct omap_hwmod_class omap34xx_ssi_hwmod_class = {
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static struct omap_hwmod_class omap3xxx_ssi_hwmod_class = {
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.name = "ssi",
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.sysc = &omap34xx_ssi_sysc,
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};
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static struct omap_hwmod omap34xx_ssi_hwmod = {
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static struct omap_hwmod omap3xxx_ssi_hwmod = {
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.name = "ssi",
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.class = &omap34xx_ssi_hwmod_class,
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.class = &omap3xxx_ssi_hwmod_class,
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.clkdm_name = "core_l4_clkdm",
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.main_clk = "ssi_ssr_fck",
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.prcm = {
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@ -3605,9 +3605,9 @@ static struct omap_hwmod omap34xx_ssi_hwmod = {
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};
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/* L4 CORE -> SSI */
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static struct omap_hwmod_ocp_if omap34xx_l4_core__ssi = {
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static struct omap_hwmod_ocp_if omap3xxx_l4_core__ssi = {
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.master = &omap3xxx_l4_core_hwmod,
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.slave = &omap34xx_ssi_hwmod,
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.slave = &omap3xxx_ssi_hwmod,
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.clk = "ssi_ick",
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.user = OCP_USER_MPU | OCP_USER_SDMA,
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};
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@ -3760,7 +3760,7 @@ static struct omap_hwmod_ocp_if *omap34xx_hwmod_ocp_ifs[] __initdata = {
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&omap3xxx_sad2d__l3,
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&omap3xxx_l4_core__mmu_isp,
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&omap3xxx_l3_main__mmu_iva,
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&omap34xx_l4_core__ssi,
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&omap3xxx_l4_core__ssi,
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NULL
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};
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@ -3784,6 +3784,7 @@ static struct omap_hwmod_ocp_if *omap36xx_hwmod_ocp_ifs[] __initdata = {
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&omap3xxx_sad2d__l3,
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&omap3xxx_l4_core__mmu_isp,
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&omap3xxx_l3_main__mmu_iva,
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&omap3xxx_l4_core__ssi,
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NULL
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};
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@ -1482,8 +1482,7 @@ static struct omap_hwmod_class_sysconfig dra7xx_ocp2scp_sysc = {
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.syss_offs = 0x0014,
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.sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE |
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SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART |
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SIDLE_SMART_WKUP),
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.idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART),
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.sysc_fields = &omap_hwmod_sysc_type1,
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};
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@ -1532,29 +1531,44 @@ static struct omap_hwmod_class dra7xx_pciess_hwmod_class = {
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};
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/* pcie1 */
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static struct omap_hwmod_rst_info dra7xx_pciess1_resets[] = {
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{ .name = "pcie", .rst_shift = 0 },
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};
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static struct omap_hwmod dra7xx_pciess1_hwmod = {
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.name = "pcie1",
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.class = &dra7xx_pciess_hwmod_class,
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.clkdm_name = "pcie_clkdm",
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.rst_lines = dra7xx_pciess1_resets,
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.rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess1_resets),
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.main_clk = "l4_root_clk_div",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS1_CLKCTRL_OFFSET,
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.rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L3INIT_PCIESS1_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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},
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};
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/* pcie2 */
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static struct omap_hwmod_rst_info dra7xx_pciess2_resets[] = {
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{ .name = "pcie", .rst_shift = 1 },
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};
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/* pcie2 */
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static struct omap_hwmod dra7xx_pciess2_hwmod = {
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.name = "pcie2",
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.class = &dra7xx_pciess_hwmod_class,
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.clkdm_name = "pcie_clkdm",
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.rst_lines = dra7xx_pciess2_resets,
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.rst_lines_cnt = ARRAY_SIZE(dra7xx_pciess2_resets),
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.main_clk = "l4_root_clk_div",
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.prcm = {
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.omap4 = {
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.clkctrl_offs = DRA7XX_CM_L3INIT_PCIESS2_CLKCTRL_OFFSET,
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.rstctrl_offs = DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET,
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.context_offs = DRA7XX_RM_L3INIT_PCIESS2_CONTEXT_OFFSET,
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.modulemode = MODULEMODE_SWCTRL,
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},
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@ -360,6 +360,7 @@
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/* PRM.L3INIT_PRM register offsets */
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#define DRA7XX_PM_L3INIT_PWRSTCTRL_OFFSET 0x0000
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#define DRA7XX_PM_L3INIT_PWRSTST_OFFSET 0x0004
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#define DRA7XX_RM_L3INIT_PCIESS_RSTCTRL_OFFSET 0x0010
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#define DRA7XX_PM_L3INIT_MMC1_WKDEP_OFFSET 0x0028
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#define DRA7XX_RM_L3INIT_MMC1_CONTEXT_OFFSET 0x002c
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#define DRA7XX_PM_L3INIT_MMC2_WKDEP_OFFSET 0x0030
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