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scsi: mpt3sas: Don't change the DMA coherent mask after allocations
The DMA layer does not allow changing the DMA coherent mask after there are outstanding allocations. Link: https://lore.kernel.org/r/1587626596-1044-2-git-send-email-suganath-prabu.subramani@broadcom.com Reported-by: Abdul Haleem <abdhalee@linux.vnet.ibm.com> Signed-off-by: Christoph Hellwig <hch@lst.de> Signed-off-by: Suganath Prabu <suganath-prabu.subramani@broadcom.com> Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
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@ -2806,58 +2806,38 @@ _base_build_sg_ieee(struct MPT3SAS_ADAPTER *ioc, void *psge,
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static int
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_base_config_dma_addressing(struct MPT3SAS_ADAPTER *ioc, struct pci_dev *pdev)
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{
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u64 required_mask, coherent_mask;
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struct sysinfo s;
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int dma_mask;
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if (ioc->is_mcpu_endpoint ||
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sizeof(dma_addr_t) == 4 ||
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dma_get_required_mask(&pdev->dev) <= 32)
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dma_mask = 32;
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/* Set 63 bit DMA mask for all SAS3 and SAS35 controllers */
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int dma_mask = (ioc->hba_mpi_version_belonged > MPI2_VERSION) ? 63 : 64;
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if (ioc->is_mcpu_endpoint)
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goto try_32bit;
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required_mask = dma_get_required_mask(&pdev->dev);
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if (sizeof(dma_addr_t) == 4 || required_mask == 32)
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goto try_32bit;
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if (ioc->dma_mask)
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coherent_mask = DMA_BIT_MASK(dma_mask);
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else if (ioc->hba_mpi_version_belonged > MPI2_VERSION)
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dma_mask = 63;
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else
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coherent_mask = DMA_BIT_MASK(32);
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dma_mask = 64;
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if (dma_set_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)) ||
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dma_set_coherent_mask(&pdev->dev, coherent_mask))
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goto try_32bit;
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ioc->base_add_sg_single = &_base_add_sg_single_64;
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ioc->sge_size = sizeof(Mpi2SGESimple64_t);
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ioc->dma_mask = dma_mask;
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goto out;
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try_32bit:
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if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
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dma_set_coherent_mask(&pdev->dev, DMA_BIT_MASK(dma_mask)))
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return -ENODEV;
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ioc->base_add_sg_single = &_base_add_sg_single_32;
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ioc->sge_size = sizeof(Mpi2SGESimple32_t);
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ioc->dma_mask = 32;
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out:
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if (dma_mask > 32) {
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ioc->base_add_sg_single = &_base_add_sg_single_64;
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ioc->sge_size = sizeof(Mpi2SGESimple64_t);
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} else {
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ioc->base_add_sg_single = &_base_add_sg_single_32;
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ioc->sge_size = sizeof(Mpi2SGESimple32_t);
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}
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si_meminfo(&s);
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ioc_info(ioc, "%d BIT PCI BUS DMA ADDRESSING SUPPORTED, total mem (%ld kB)\n",
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ioc->dma_mask, convert_to_kb(s.totalram));
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dma_mask, convert_to_kb(s.totalram));
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return 0;
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}
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static int
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_base_change_consistent_dma_mask(struct MPT3SAS_ADAPTER *ioc,
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struct pci_dev *pdev)
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{
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if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(ioc->dma_mask))) {
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if (pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32)))
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return -ENODEV;
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}
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return 0;
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}
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/**
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* _base_check_enable_msix - checks MSIX capabable.
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* @ioc: per adapter object
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@ -5169,14 +5149,6 @@ _base_allocate_memory_pools(struct MPT3SAS_ADAPTER *ioc)
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total_sz += sz;
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} while (ioc->rdpq_array_enable && (++i < ioc->reply_queue_count));
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if (ioc->dma_mask > 32) {
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if (_base_change_consistent_dma_mask(ioc, ioc->pdev) != 0) {
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ioc_warn(ioc, "no suitable consistent DMA mask for %s\n",
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pci_name(ioc->pdev));
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goto out;
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}
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}
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ioc->scsiio_depth = ioc->hba_queue_depth -
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ioc->hi_priority_depth - ioc->internal_depth;
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@ -7158,7 +7130,6 @@ mpt3sas_base_attach(struct MPT3SAS_ADAPTER *ioc)
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ioc->smp_affinity_enable = smp_affinity_enable;
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ioc->rdpq_array_enable_assigned = 0;
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ioc->dma_mask = 0;
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if (ioc->is_aero_ioc)
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ioc->base_readl = &_base_readl_aero;
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else
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@ -1026,7 +1026,6 @@ typedef void (*MPT3SAS_FLUSH_RUNNING_CMDS)(struct MPT3SAS_ADAPTER *ioc);
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* @ir_firmware: IR firmware present
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* @bars: bitmask of BAR's that must be configured
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* @mask_interrupts: ignore interrupt
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* @dma_mask: used to set the consistent dma mask
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* @pci_access_mutex: Mutex to synchronize ioctl, sysfs show path and
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* pci resource handling
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* @fault_reset_work_q_name: fw fault work queue
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@ -1205,7 +1204,6 @@ struct MPT3SAS_ADAPTER {
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u8 ir_firmware;
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int bars;
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u8 mask_interrupts;
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int dma_mask;
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/* fw fault handler */
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char fault_reset_work_q_name[20];
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