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iio: dac: ti-dac7612: Fix alignment for DMA safety

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____cacheline_aligned is an insufficient guarantee for non-coherent DMA
on platforms with 128 byte cachelines above L1.  Switch to the updated
IIO_DMA_MINALIGN definition.

Updated help text to 'may' require buffers to be in their own cacheline.

Fixes: 977724d205 ("iio:dac:ti-dac7612: Add driver for Texas Instruments DAC7612")
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Cc: Ricardo Ribalda <ribalda@kernel.org>
Acked-by: Nuno Sá <nuno.sa@analog.com>
Link: https://lore.kernel.org/r/20220508175712.647246-65-jic23@kernel.org
This commit is contained in:
Jonathan Cameron 2022-05-08 18:56:44 +01:00
parent 3637c49ed5
commit b9ac08b328
1 changed files with 2 additions and 2 deletions
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4
drivers/iio/dac/ti-dac7612.c
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@ -31,10 +31,10 @@ struct dac7612 {
struct mutex lock;
/*
* DMA (thus cache coherency maintenance) requires the
* DMA (thus cache coherency maintenance) may require the
* transfer buffers to live in their own cache lines.
*/
uint8_t data[2] ____cacheline_aligned;
uint8_t data[2] __aligned(IIO_DMA_MINALIGN);
};
static int dac7612_cmd_single(struct dac7612 *priv, int channel, u16 val)