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drm/amd/pm: correct the pcie link state check for SMU13

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Update the driver implementations to fit those data exposed
by PMFW.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org # 6.1.x
This commit is contained in:
Evan Quan 2023-04-07 17:12:15 +08:00 committed by Alex Deucher
parent 85e0689eb6
commit b9a24d8bd5
3 changed files with 10 additions and 4 deletions
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6
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
View File

@ -61,6 +61,12 @@
#define CTF_OFFSET_HOTSPOT 5
#define CTF_OFFSET_MEM 5
static const int pmfw_decoded_link_speed[5] = {1, 2, 3, 4, 5};
static const int pmfw_decoded_link_width[7] = {0, 1, 2, 4, 8, 12, 16};
#define DECODE_GEN_SPEED(gen_speed_idx) (pmfw_decoded_link_speed[gen_speed_idx])
#define DECODE_LANE_WIDTH(lane_width_idx) (pmfw_decoded_link_width[lane_width_idx])
struct smu_13_0_max_sustainable_clocks {
uint32_t display_clock;
uint32_t phy_clock;

4
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
View File

@ -1144,8 +1144,8 @@ static int smu_v13_0_0_print_clk_levels(struct smu_context *smu,
(pcie_table->pcie_lane[i] == 5) ? "x12" :
(pcie_table->pcie_lane[i] == 6) ? "x16" : "",
pcie_table->clk_freq[i],
((gen_speed - 1) == pcie_table->pcie_gen[i]) &&
(lane_width == link_width[pcie_table->pcie_lane[i]]) ?
(gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
(lane_width == DECODE_LANE_WIDTH(link_width[pcie_table->pcie_lane[i]])) ?
"*" : "");
break;

4
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
View File

@ -1133,8 +1133,8 @@ static int smu_v13_0_7_print_clk_levels(struct smu_context *smu,
(pcie_table->pcie_lane[i] == 5) ? "x12" :
(pcie_table->pcie_lane[i] == 6) ? "x16" : "",
pcie_table->clk_freq[i],
(gen_speed == pcie_table->pcie_gen[i]) &&
(lane_width == pcie_table->pcie_lane[i]) ?
(gen_speed == DECODE_GEN_SPEED(pcie_table->pcie_gen[i])) &&
(lane_width == DECODE_LANE_WIDTH(pcie_table->pcie_lane[i])) ?
"*" : "");
break;