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powerpc: Fix atomic_xxx_return barrier semantics
The Documentation/memory-barriers.txt document requires that atomic operations that return a value act as a memory barrier both before and after the actual atomic operation. Our current implementation doesn't guarantee this. More specifically, while a load following the isync can not be issued before stwcx. has completed, that completion doesn't architecturally means that the result of stwcx. is visible to other processors (or any previous stores for that matter) (typically, the other processors L1 caches can still hold the old value). This has caused an actual crash in RCU torture testing on Power 7 This fixes it by changing those atomic ops to use new macros instead of RELEASE/ACQUIRE barriers, called ATOMIC_ENTRY and ATMOIC_EXIT barriers, which are then defined respectively to lwsync and sync. I haven't had a chance to measure the performance impact (or rather what I measured with kernel compiles is in the noise, I yet have to find a more precise benchmark) Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org> Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
This commit is contained in:
Benjamin Herrenschmidt
parent
a9a8f77ac7
commit
b97021f855
@ -49,13 +49,13 @@ static __inline__ int atomic_add_return(int a, atomic_t *v)
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int t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %0,0,%2 # atomic_add_return\n\
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add %0,%1,%0\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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@ -85,13 +85,13 @@ static __inline__ int atomic_sub_return(int a, atomic_t *v)
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int t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %0,0,%2 # atomic_sub_return\n\
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subf %0,%1,%0\n"
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%2 \n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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@ -119,13 +119,13 @@ static __inline__ int atomic_inc_return(atomic_t *v)
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int t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %0,0,%1 # atomic_inc_return\n\
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addic %0,%0,1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1 \n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "xer", "memory");
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@ -163,13 +163,13 @@ static __inline__ int atomic_dec_return(atomic_t *v)
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int t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %0,0,%1 # atomic_dec_return\n\
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addic %0,%0,-1\n"
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "xer", "memory");
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@ -194,7 +194,7 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
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int t;
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__asm__ __volatile__ (
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %0,0,%1 # __atomic_add_unless\n\
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cmpw 0,%0,%3 \n\
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beq- 2f \n\
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@ -202,7 +202,7 @@ static __inline__ int __atomic_add_unless(atomic_t *v, int a, int u)
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PPC405_ERR77(0,%2)
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" stwcx. %0,0,%1 \n\
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bne- 1b \n"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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" subf %0,%2,%0 \n\
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2:"
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: "=&r" (t)
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@ -226,7 +226,7 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
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int t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %0,0,%1 # atomic_dec_if_positive\n\
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cmpwi %0,1\n\
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addi %0,%0,-1\n\
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@ -234,7 +234,7 @@ static __inline__ int atomic_dec_if_positive(atomic_t *v)
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PPC405_ERR77(0,%1)
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" stwcx. %0,0,%1\n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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"\n\
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2:" : "=&b" (t)
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: "r" (&v->counter)
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@ -285,12 +285,12 @@ static __inline__ long atomic64_add_return(long a, atomic64_t *v)
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long t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: ldarx %0,0,%2 # atomic64_add_return\n\
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add %0,%1,%0\n\
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stdcx. %0,0,%2 \n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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@ -319,12 +319,12 @@ static __inline__ long atomic64_sub_return(long a, atomic64_t *v)
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long t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: ldarx %0,0,%2 # atomic64_sub_return\n\
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subf %0,%1,%0\n\
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stdcx. %0,0,%2 \n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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: "=&r" (t)
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: "r" (a), "r" (&v->counter)
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: "cc", "memory");
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@ -351,12 +351,12 @@ static __inline__ long atomic64_inc_return(atomic64_t *v)
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long t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: ldarx %0,0,%1 # atomic64_inc_return\n\
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addic %0,%0,1\n\
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stdcx. %0,0,%1 \n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "xer", "memory");
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@ -393,12 +393,12 @@ static __inline__ long atomic64_dec_return(atomic64_t *v)
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long t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: ldarx %0,0,%1 # atomic64_dec_return\n\
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addic %0,%0,-1\n\
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stdcx. %0,0,%1\n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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: "=&r" (t)
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: "r" (&v->counter)
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: "cc", "xer", "memory");
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@ -418,13 +418,13 @@ static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
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long t;
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__asm__ __volatile__(
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: ldarx %0,0,%1 # atomic64_dec_if_positive\n\
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addic. %0,%0,-1\n\
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blt- 2f\n\
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stdcx. %0,0,%1\n\
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bne- 1b"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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"\n\
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2:" : "=&r" (t)
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: "r" (&v->counter)
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@ -450,14 +450,14 @@ static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
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long t;
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__asm__ __volatile__ (
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: ldarx %0,0,%1 # __atomic_add_unless\n\
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cmpd 0,%0,%3 \n\
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beq- 2f \n\
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add %0,%2,%0 \n"
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" stdcx. %0,0,%1 \n\
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bne- 1b \n"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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" subf %0,%2,%0 \n\
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2:"
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: "=&r" (t)
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@ -124,14 +124,14 @@ static __inline__ unsigned long fn( \
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return (old & mask); \
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}
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DEFINE_TESTOP(test_and_set_bits, or, PPC_RELEASE_BARRIER,
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PPC_ACQUIRE_BARRIER, 0)
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DEFINE_TESTOP(test_and_set_bits, or, PPC_ATOMIC_ENTRY_BARRIER,
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PPC_ATOMIC_EXIT_BARRIER, 0)
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DEFINE_TESTOP(test_and_set_bits_lock, or, "",
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PPC_ACQUIRE_BARRIER, 1)
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DEFINE_TESTOP(test_and_clear_bits, andc, PPC_RELEASE_BARRIER,
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PPC_ACQUIRE_BARRIER, 0)
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DEFINE_TESTOP(test_and_change_bits, xor, PPC_RELEASE_BARRIER,
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PPC_ACQUIRE_BARRIER, 0)
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DEFINE_TESTOP(test_and_clear_bits, andc, PPC_ATOMIC_ENTRY_BARRIER,
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PPC_ATOMIC_EXIT_BARRIER, 0)
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DEFINE_TESTOP(test_and_change_bits, xor, PPC_ATOMIC_ENTRY_BARRIER,
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PPC_ATOMIC_EXIT_BARRIER, 0)
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static __inline__ int test_and_set_bit(unsigned long nr,
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volatile unsigned long *addr)
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@ -11,12 +11,13 @@
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \
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__asm__ __volatile ( \
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PPC_RELEASE_BARRIER \
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PPC_ATOMIC_ENTRY_BARRIER \
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"1: lwarx %0,0,%2\n" \
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insn \
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PPC405_ERR77(0, %2) \
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"2: stwcx. %1,0,%2\n" \
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"bne- 1b\n" \
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PPC_ATOMIC_EXIT_BARRIER \
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"li %1,0\n" \
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"3: .section .fixup,\"ax\"\n" \
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"4: li %1,%3\n" \
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@ -92,14 +93,14 @@ futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr,
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return -EFAULT;
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__asm__ __volatile__ (
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PPC_RELEASE_BARRIER
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PPC_ATOMIC_ENTRY_BARRIER
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"1: lwarx %1,0,%3 # futex_atomic_cmpxchg_inatomic\n\
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cmpw 0,%1,%4\n\
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bne- 3f\n"
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PPC405_ERR77(0,%3)
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"2: stwcx. %5,0,%3\n\
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bne- 1b\n"
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PPC_ACQUIRE_BARRIER
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PPC_ATOMIC_EXIT_BARRIER
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"3: .section .fixup,\"ax\"\n\
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4: li %0,%6\n\
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b 3b\n\
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@ -42,11 +42,15 @@ static inline void isync(void)
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START_LWSYNC_SECTION(97); \
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isync; \
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MAKE_LWSYNC_SECTION_ENTRY(97, __lwsync_fixup);
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#define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER)
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#define PPC_RELEASE_BARRIER stringify_in_c(LWSYNC) "\n"
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#define PPC_ACQUIRE_BARRIER "\n" stringify_in_c(__PPC_ACQUIRE_BARRIER)
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#define PPC_RELEASE_BARRIER stringify_in_c(LWSYNC) "\n"
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#define PPC_ATOMIC_ENTRY_BARRIER "\n" stringify_in_c(LWSYNC) "\n"
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#define PPC_ATOMIC_EXIT_BARRIER "\n" stringify_in_c(sync) "\n"
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#else
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#define PPC_ACQUIRE_BARRIER
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#define PPC_RELEASE_BARRIER
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#define PPC_ATOMIC_ENTRY_BARRIER
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#define PPC_ATOMIC_EXIT_BARRIER
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#endif
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#endif /* __KERNEL__ */
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