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drm/msm/mdp5: Allocate CTL0/1 for dual DSI single FLUSH
This change takes advantage of a HW feature that synchronize flush operation on CTL1 to CTL0, to keep dual DSI pipes in sync. Signed-off-by: Hai Li <hali@codeaurora.org> Signed-off-by: Rob Clark <robdclark@gmail.com>
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@ -17,7 +17,7 @@
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/*
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* CTL - MDP Control Pool Manager
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*
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* Controls are shared between all CRTCs.
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* Controls are shared between all display interfaces.
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*
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* They are intended to be used for data path configuration.
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* The top level register programming describes the complete data path for
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@ -27,12 +27,11 @@
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*
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* In certain use cases (high-resolution dual pipe), one single CTL can be
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* shared across multiple CRTCs.
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*
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* Because the number of CTLs can be less than the number of CRTCs,
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* CTLs are dynamically allocated from a pool of CTLs, only once a CRTC is
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* requested by the client (in mdp5_crtc_mode_set()).
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*/
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#define CTL_STAT_BUSY 0x1
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#define CTL_STAT_BOOKED 0x2
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struct op_mode {
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struct mdp5_interface intf;
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@ -46,8 +45,8 @@ struct mdp5_ctl {
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u32 id;
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int lm;
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/* whether this CTL has been allocated or not: */
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bool busy;
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/* CTL status bitmask */
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u32 status;
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/* Operation Mode Configuration for the Pipeline */
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struct op_mode pipeline;
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@ -60,6 +59,11 @@ struct mdp5_ctl {
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u32 pending_ctl_trigger;
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bool cursor_on;
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/* True if the current CTL has FLUSH bits pending for single FLUSH. */
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bool flush_pending;
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struct mdp5_ctl *pair; /* Paired CTL to be flushed together */
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};
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struct mdp5_ctl_manager {
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@ -72,6 +76,10 @@ struct mdp5_ctl_manager {
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/* to filter out non-present bits in the current hardware config */
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u32 flush_hw_mask;
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/* status for single FLUSH */
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bool single_flush_supported;
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u32 single_flush_pending_mask;
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/* pool of CTLs + lock to protect resource allocation (ctls[i].busy) */
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spinlock_t pool_lock;
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struct mdp5_ctl ctls[MAX_CTL];
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@ -443,6 +451,31 @@ static u32 fix_sw_flush(struct mdp5_ctl *ctl, u32 flush_mask)
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return sw_mask;
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}
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static void fix_for_single_flush(struct mdp5_ctl *ctl, u32 *flush_mask,
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u32 *flush_id)
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{
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struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
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if (ctl->pair) {
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DBG("CTL %d FLUSH pending mask %x", ctl->id, *flush_mask);
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ctl->flush_pending = true;
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ctl_mgr->single_flush_pending_mask |= (*flush_mask);
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*flush_mask = 0;
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if (ctl->pair->flush_pending) {
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*flush_id = min_t(u32, ctl->id, ctl->pair->id);
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*flush_mask = ctl_mgr->single_flush_pending_mask;
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ctl->flush_pending = false;
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ctl->pair->flush_pending = false;
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ctl_mgr->single_flush_pending_mask = 0;
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DBG("Single FLUSH mask %x,ID %d", *flush_mask,
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*flush_id);
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}
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}
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}
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/**
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* mdp5_ctl_commit() - Register Flush
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*
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@ -464,6 +497,8 @@ u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask)
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struct mdp5_ctl_manager *ctl_mgr = ctl->ctlm;
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struct op_mode *pipeline = &ctl->pipeline;
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unsigned long flags;
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u32 flush_id = ctl->id;
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u32 curr_ctl_flush_mask;
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pipeline->start_mask &= ~flush_mask;
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@ -479,9 +514,13 @@ u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask)
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flush_mask &= ctl_mgr->flush_hw_mask;
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curr_ctl_flush_mask = flush_mask;
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fix_for_single_flush(ctl, &flush_mask, &flush_id);
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if (flush_mask) {
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spin_lock_irqsave(&ctl->hw_lock, flags);
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ctl_write(ctl, REG_MDP5_CTL_FLUSH(ctl->id), flush_mask);
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ctl_write(ctl, REG_MDP5_CTL_FLUSH(flush_id), flush_mask);
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spin_unlock_irqrestore(&ctl->hw_lock, flags);
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}
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@ -490,7 +529,7 @@ u32 mdp5_ctl_commit(struct mdp5_ctl *ctl, u32 flush_mask)
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refill_start_mask(ctl);
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}
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return flush_mask;
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return curr_ctl_flush_mask;
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}
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u32 mdp5_ctl_get_commit_status(struct mdp5_ctl *ctl)
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@ -503,33 +542,80 @@ int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl)
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return WARN_ON(!ctl) ? -EINVAL : ctl->id;
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}
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/*
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* mdp5_ctl_pair() - Associate 2 booked CTLs for single FLUSH
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*/
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int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable)
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{
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struct mdp5_ctl_manager *ctl_mgr = ctlx->ctlm;
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struct mdp5_kms *mdp5_kms = get_kms(ctl_mgr);
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/* do nothing silently if hw doesn't support */
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if (!ctl_mgr->single_flush_supported)
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return 0;
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if (!enable) {
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ctlx->pair = NULL;
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ctly->pair = NULL;
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mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0), 0);
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return 0;
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} else if ((ctlx->pair != NULL) || (ctly->pair != NULL)) {
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dev_err(ctl_mgr->dev->dev, "CTLs already paired\n");
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return -EINVAL;
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} else if (!(ctlx->status & ctly->status & CTL_STAT_BOOKED)) {
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dev_err(ctl_mgr->dev->dev, "Only pair booked CTLs\n");
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return -EINVAL;
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}
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ctlx->pair = ctly;
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ctly->pair = ctlx;
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mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0),
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MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN);
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return 0;
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}
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/*
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* mdp5_ctl_request() - CTL allocation
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*
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* @return first free CTL
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* Try to return booked CTL for @intf_num is 1 or 2, unbooked for other INTFs.
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* If no CTL is available in preferred category, allocate from the other one.
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*
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* @return fail if no CTL is available.
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*/
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struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctl_mgr,
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int intf_num)
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{
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struct mdp5_ctl *ctl = NULL;
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const u32 checkm = CTL_STAT_BUSY | CTL_STAT_BOOKED;
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u32 match = ((intf_num == 1) || (intf_num == 2)) ? CTL_STAT_BOOKED : 0;
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unsigned long flags;
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int c;
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spin_lock_irqsave(&ctl_mgr->pool_lock, flags);
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/* search the preferred */
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for (c = 0; c < ctl_mgr->nctl; c++)
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if (!ctl_mgr->ctls[c].busy)
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break;
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if ((ctl_mgr->ctls[c].status & checkm) == match)
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goto found;
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if (unlikely(c >= ctl_mgr->nctl)) {
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dev_err(ctl_mgr->dev->dev, "No more CTL available!");
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goto unlock;
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}
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dev_warn(ctl_mgr->dev->dev,
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"fall back to the other CTL category for INTF %d!\n", intf_num);
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match ^= CTL_STAT_BOOKED;
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for (c = 0; c < ctl_mgr->nctl; c++)
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if ((ctl_mgr->ctls[c].status & checkm) == match)
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goto found;
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dev_err(ctl_mgr->dev->dev, "No more CTL available!");
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goto unlock;
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found:
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ctl = &ctl_mgr->ctls[c];
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ctl->pipeline.intf.num = intf_num;
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ctl->lm = -1;
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ctl->busy = true;
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ctl->status |= CTL_STAT_BUSY;
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ctl->pending_ctl_trigger = 0;
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DBG("CTL %d allocated", ctl->id);
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@ -558,9 +644,11 @@ void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctl_mgr)
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}
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struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
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void __iomem *mmio_base, const struct mdp5_cfg_hw *hw_cfg)
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void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd)
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{
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struct mdp5_ctl_manager *ctl_mgr;
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const struct mdp5_cfg_hw *hw_cfg = mdp5_cfg_get_hw_config(cfg_hnd);
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int rev = mdp5_cfg_get_hw_rev(cfg_hnd);
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const struct mdp5_ctl_block *ctl_cfg = &hw_cfg->ctl;
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unsigned long flags;
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int c, ret;
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@ -594,14 +682,28 @@ struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
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if (WARN_ON(!ctl_cfg->base[c])) {
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dev_err(dev->dev, "CTL_%d: base is null!\n", c);
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ret = -EINVAL;
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spin_unlock_irqrestore(&ctl_mgr->pool_lock, flags);
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goto fail;
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}
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ctl->ctlm = ctl_mgr;
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ctl->id = c;
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ctl->reg_offset = ctl_cfg->base[c];
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ctl->busy = false;
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ctl->status = 0;
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spin_lock_init(&ctl->hw_lock);
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}
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/*
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* In Dual DSI case, CTL0 and CTL1 are always assigned to two DSI
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* interfaces to support single FLUSH feature (Flush CTL0 and CTL1 when
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* only write into CTL0's FLUSH register) to keep two DSI pipes in sync.
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* Single FLUSH is supported from hw rev v3.0.
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*/
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if (rev >= 3) {
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ctl_mgr->single_flush_supported = true;
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/* Reserve CTL0/1 for INTF1/2 */
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ctl_mgr->ctls[0].status |= CTL_STAT_BOOKED;
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ctl_mgr->ctls[1].status |= CTL_STAT_BOOKED;
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}
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spin_unlock_irqrestore(&ctl_mgr->pool_lock, flags);
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DBG("Pool of %d CTLs created.", ctl_mgr->nctl);
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@ -23,7 +23,7 @@
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*/
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struct mdp5_ctl_manager;
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struct mdp5_ctl_manager *mdp5_ctlm_init(struct drm_device *dev,
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void __iomem *mmio_base, const struct mdp5_cfg_hw *hw_cfg);
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void __iomem *mmio_base, struct mdp5_cfg_handler *cfg_hnd);
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void mdp5_ctlm_hw_reset(struct mdp5_ctl_manager *ctlm);
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void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctlm);
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@ -33,6 +33,7 @@ void mdp5_ctlm_destroy(struct mdp5_ctl_manager *ctlm);
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* which is then used to call the other mdp5_ctl_*(ctl, ...) functions.
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*/
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struct mdp5_ctl *mdp5_ctlm_request(struct mdp5_ctl_manager *ctlm, int intf_num);
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int mdp5_ctl_get_ctl_id(struct mdp5_ctl *ctl);
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struct mdp5_interface;
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@ -41,6 +42,7 @@ int mdp5_ctl_set_pipeline(struct mdp5_ctl *ctl, struct mdp5_interface *intf,
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int mdp5_ctl_set_encoder_state(struct mdp5_ctl *ctl, bool enabled);
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int mdp5_ctl_set_cursor(struct mdp5_ctl *ctl, int cursor_id, bool enable);
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int mdp5_ctl_pair(struct mdp5_ctl *ctlx, struct mdp5_ctl *ctly, bool enable);
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/*
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* mdp5_ctl_blend() - Blend multiple layers on a Layer Mixer (LM)
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@ -297,6 +297,7 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
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struct drm_encoder *slave_encoder)
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{
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struct mdp5_encoder *mdp5_encoder = to_mdp5_encoder(encoder);
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struct mdp5_encoder *mdp5_slave_enc = to_mdp5_encoder(slave_encoder);
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struct mdp5_kms *mdp5_kms;
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int intf_num;
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u32 data = 0;
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@ -319,12 +320,13 @@ int mdp5_encoder_set_split_display(struct drm_encoder *encoder,
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/* Make sure clocks are on when connectors calling this function. */
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mdp5_enable(mdp5_kms);
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mdp5_write(mdp5_kms, REG_MDP5_MDP_SPARE_0(0),
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MDP5_MDP_SPARE_0_SPLIT_DPL_SINGLE_FLUSH_EN);
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/* Dumb Panel, Sync mode */
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mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_UPPER(0), 0);
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mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_LOWER(0), data);
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mdp5_write(mdp5_kms, REG_MDP5_MDP_SPLIT_DPL_EN(0), 1);
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mdp5_ctl_pair(mdp5_encoder->ctl, mdp5_slave_enc->ctl, true);
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mdp5_disable(mdp5_kms);
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return 0;
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@ -543,7 +543,7 @@ struct msm_kms *mdp5_kms_init(struct drm_device *dev)
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goto fail;
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}
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mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, config->hw);
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mdp5_kms->ctlm = mdp5_ctlm_init(dev, mdp5_kms->mmio, mdp5_kms->cfg);
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if (IS_ERR(mdp5_kms->ctlm)) {
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ret = PTR_ERR(mdp5_kms->ctlm);
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mdp5_kms->ctlm = NULL;
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