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iwlwifi: pcie: handle switching killer Qu B0 NICs to C0
We need to use a different firmware for C0 versions of killer Qu NICs. Add structures for them and handle them in the if block that detects C0 revisions. Additionally, instead of having an inclusive check for QnJ devices, make the selection exclusive, so that switching to QnJ is the exception, not the default. This prevents us from having to add all the non-QnJ cards to an exclusion list. To do so, only go into the QnJ block if the device has an RF ID type HR and HW revision QnJ. Cc: stable@vger.kernel.org # 5.2 Signed-off-by: Luca Coelho <luciano.coelho@intel.com> Link: https://lore.kernel.org/r/20190821171732.2266-1-luca@coelho.fi Signed-off-by: Johannes Berg <johannes.berg@intel.com>
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@ -556,6 +556,30 @@ const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0 = {
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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};
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const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0 = {
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.name = "Killer(R) Wi-Fi 6 AX1650i 160MHz Wireless Network Adapter (201NGW)",
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.fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
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IWL_DEVICE_22500,
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/*
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* This device doesn't support receiving BlockAck with a large bitmap
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* so we need to restrict the size of transmitted aggregation to the
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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};
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const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0 = {
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.name = "Killer(R) Wi-Fi 6 AX1650s 160MHz Wireless Network Adapter (201D2W)",
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.fw_name_pre = IWL_QU_C_HR_B_FW_PRE,
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IWL_DEVICE_22500,
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/*
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* This device doesn't support receiving BlockAck with a large bitmap
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* so we need to restrict the size of transmitted aggregation to the
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* HT size; mac80211 would otherwise pick the HE max (256) by default.
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*/
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.max_tx_agg_size = IEEE80211_MAX_AMPDU_BUF_HT,
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};
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const struct iwl_cfg iwl22000_2ax_cfg_jf = {
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.name = "Intel(R) Dual Band Wireless AX 22000",
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.fw_name_pre = IWL_QU_B_JF_B_FW_PRE,
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@ -577,6 +577,8 @@ extern const struct iwl_cfg iwl_ax1650i_cfg_quz_hr;
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extern const struct iwl_cfg iwl_ax1650s_cfg_quz_hr;
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extern const struct iwl_cfg killer1650s_2ax_cfg_qu_b0_hr_b0;
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extern const struct iwl_cfg killer1650i_2ax_cfg_qu_b0_hr_b0;
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extern const struct iwl_cfg killer1650s_2ax_cfg_qu_c0_hr_b0;
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extern const struct iwl_cfg killer1650i_2ax_cfg_qu_c0_hr_b0;
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extern const struct iwl_cfg killer1650x_2ax_cfg;
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extern const struct iwl_cfg killer1650w_2ax_cfg;
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extern const struct iwl_cfg iwl9461_2ac_cfg_qu_b0_jf_b0;
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@ -1062,6 +1062,10 @@ static int iwl_pci_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
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iwl_trans->cfg = &iwl9560_2ac_cfg_qu_c0_jf_b0;
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else if (iwl_trans->cfg == &iwl9560_2ac_160_cfg_qu_b0_jf_b0)
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iwl_trans->cfg = &iwl9560_2ac_160_cfg_qu_c0_jf_b0;
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else if (iwl_trans->cfg == &killer1650s_2ax_cfg_qu_b0_hr_b0)
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iwl_trans->cfg = &killer1650s_2ax_cfg_qu_c0_hr_b0;
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else if (iwl_trans->cfg == &killer1650i_2ax_cfg_qu_b0_hr_b0)
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iwl_trans->cfg = &killer1650i_2ax_cfg_qu_c0_hr_b0;
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}
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/* same thing for QuZ... */
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@ -3602,12 +3602,7 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
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}
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} else if (CSR_HW_RF_ID_TYPE_CHIP_ID(trans->hw_rf_id) ==
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CSR_HW_RF_ID_TYPE_CHIP_ID(CSR_HW_RF_ID_TYPE_HR) &&
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((trans->cfg != &iwl_ax200_cfg_cc &&
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trans->cfg != &iwl_ax201_cfg_qu_hr &&
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trans->cfg != &killer1650x_2ax_cfg &&
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trans->cfg != &killer1650w_2ax_cfg &&
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trans->cfg != &iwl_ax201_cfg_quz_hr) ||
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trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0)) {
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trans->hw_rev == CSR_HW_REV_TYPE_QNJ_B0) {
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u32 hw_status;
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hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
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