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drm fixes for 6.0-rc5

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edid:
 - Fix EDID 1.4 range-descriptor parsing
 
 ttm:
 - Fix ghost-object bulk moves
 
 i915:
 - Fix MIPI sequence block copy from BIOS' table
 - Fix PCODE min freq setup when GuC's SLPC is in use
 - Implement Workaround for eDP
 - Fix has_flat_ccs selection for DG1
 
 amdgpu:
 - Firmware header fix
 - SMU 13.x fix
 - Debugfs memory leak fix
 - NBIO 7.7 fix
 - Firmware memory leak fix
 
 amdkfd:
 - Debug output fix
 
 panfrost:
 - Fix devfreq OPP
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Merge tag 'drm-fixes-2022-09-10' of git://anongit.freedesktop.org/drm/drm

Pull drm fixes from Dave Airlie:
 "From a train in the Irish countryside, regular drm fixes for 6.0-rc5.

  This is mostly amdgpu/amdkfd and i915 fixes, then one panfrost, one
  ttm and one edid fix. Nothing too major going on. Hopefully a quiet
  week next week for LPC.

  edid:
   - Fix EDID 1.4 range-descriptor parsing

  ttm:
   - Fix ghost-object bulk moves

  i915:
   - Fix MIPI sequence block copy from BIOS' table
   - Fix PCODE min freq setup when GuC's SLPC is in use
   - Implement Workaround for eDP
   - Fix has_flat_ccs selection for DG1

  amdgpu:
   - Firmware header fix
   - SMU 13.x fix
   - Debugfs memory leak fix
   - NBIO 7.7 fix
   - Firmware memory leak fix

  amdkfd:
   - Debug output fix

  panfrost:
   - Fix devfreq OPP"

* tag 'drm-fixes-2022-09-10' of git://anongit.freedesktop.org/drm/drm:
  drm/panfrost: devfreq: set opp to the recommended one to configure regulator
  drm/ttm: cleanup the resource of ghost objects after locking them
  drm/amdgpu: prevent toc firmware memory leak
  drm/amdgpu: correct doorbell range/size value for CSDMA_DOORBELL_RANGE
  drm/amdkfd: print address in hex format rather than decimal
  drm/amd/display: fix memory leak when using debugfs_lookup()
  drm/amd/pm: add missing SetMGpuFanBoostLimitRpm mapping for SMU 13.0.7
  drm/amd/amdgpu: add rlc_firmware_header_v2_4 to amdgpu_firmware_header
  drm/i915: consider HAS_FLAT_CCS() in needs_ccs_pages
  drm/i915: Implement WaEdpLinkRateDataReload
  drm/i915/slpc: Let's fix the PCODE min freq table setup for SLPC
  drm/i915/bios: Copy the whole MIPI sequence block
  drm/ttm: update bulk move object of ghost BO
  drm/edid: Handle EDID 1.4 range descriptor h/vfreq offsets
This commit is contained in:
Linus Torvalds 2022-09-09 14:35:22 -04:00
commit b7e00d6f55
19 changed files with 149 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.c
View File

@ -1728,7 +1728,7 @@ int amdgpu_amdkfd_gpuvm_alloc_memory_of_gpu(
add_kgd_mem_to_kfd_bo_list(*mem, avm->process_info, user_addr);
if (user_addr) {
pr_debug("creating userptr BO for user_addr = %llu\n", user_addr);
pr_debug("creating userptr BO for user_addr = %llx\n", user_addr);
ret = init_user_pages(*mem, user_addr, criu_resume);
if (ret)
goto allocate_init_user_pages_failed;

7
drivers/gpu/drm/amd/amdgpu/amdgpu_psp.c
View File

@ -486,11 +486,14 @@ static int psp_sw_fini(void *handle)
release_firmware(psp->ta_fw);
psp->ta_fw = NULL;
}
if (adev->psp.cap_fw) {
if (psp->cap_fw) {
release_firmware(psp->cap_fw);
psp->cap_fw = NULL;
}
if (psp->toc_fw) {
release_firmware(psp->toc_fw);
psp->toc_fw = NULL;
}
if (adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 0) ||
adev->ip_versions[MP0_HWIP][0] == IP_VERSION(11, 0, 7))
psp_sysfs_fini(adev);

1
drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.h
View File

@ -390,6 +390,7 @@ union amdgpu_firmware_header {
struct rlc_firmware_header_v2_1 rlc_v2_1;
struct rlc_firmware_header_v2_2 rlc_v2_2;
struct rlc_firmware_header_v2_3 rlc_v2_3;
struct rlc_firmware_header_v2_4 rlc_v2_4;
struct sdma_firmware_header_v1_0 sdma;
struct sdma_firmware_header_v1_1 sdma_v1_1;
struct sdma_firmware_header_v2_0 sdma_v2_0;

6
drivers/gpu/drm/amd/amdgpu/nbio_v7_7.c
View File

@ -68,12 +68,6 @@ static void nbio_v7_7_sdma_doorbell_range(struct amdgpu_device *adev, int instan
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC0_BIF_CSDMA_DOORBELL_RANGE,
SIZE, doorbell_size);
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC0_BIF_SDMA0_DOORBELL_RANGE,
OFFSET, doorbell_index);
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC0_BIF_SDMA0_DOORBELL_RANGE,
SIZE, doorbell_size);
} else {
doorbell_range = REG_SET_FIELD(doorbell_range,
GDC0_BIF_SDMA0_DOORBELL_RANGE,

1
drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_debugfs.c
View File

@ -3288,6 +3288,7 @@ void crtc_debugfs_init(struct drm_crtc *crtc)
&crc_win_y_end_fops);
debugfs_create_file_unsafe("crc_win_update", 0644, dir, crtc,
&crc_win_update_fops);
dput(dir);
#endif
debugfs_create_file("amdgpu_current_bpc", 0644, crtc->debugfs_entry,
crtc, &amdgpu_current_bpc_fops);

1
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_7_ppt.c
View File

@ -120,6 +120,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_7_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
MSG_MAP(Mode1Reset, PPSMC_MSG_Mode1Reset, 0),
MSG_MAP(PrepareMp1ForUnload, PPSMC_MSG_PrepareMp1ForUnload, 0),
MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
};
static struct cmn2asic_mapping smu_v13_0_7_clk_map[SMU_CLK_COUNT] = {

4
drivers/gpu/drm/drm_debugfs.c
View File

@ -377,8 +377,8 @@ static int vrr_range_show(struct seq_file *m, void *data)
if (connector->status != connector_status_connected)
return -ENODEV;
seq_printf(m, "Min: %u\n", (u8)connector->display_info.monitor_range.min_vfreq);
seq_printf(m, "Max: %u\n", (u8)connector->display_info.monitor_range.max_vfreq);
seq_printf(m, "Min: %u\n", connector->display_info.monitor_range.min_vfreq);
seq_printf(m, "Max: %u\n", connector->display_info.monitor_range.max_vfreq);
return 0;
}

24
drivers/gpu/drm/drm_edid.c
View File

@ -5971,12 +5971,14 @@ static void drm_parse_cea_ext(struct drm_connector *connector,
}
static
void get_monitor_range(const struct detailed_timing *timing,
void *info_monitor_range)
void get_monitor_range(const struct detailed_timing *timing, void *c)
{
struct drm_monitor_range_info *monitor_range = info_monitor_range;
struct detailed_mode_closure *closure = c;
struct drm_display_info *info = &closure->connector->display_info;
struct drm_monitor_range_info *monitor_range = &info->monitor_range;
const struct detailed_non_pixel *data = &timing->data.other_data;
const struct detailed_data_monitor_range *range = &data->data.range;
const struct edid *edid = closure->drm_edid->edid;
if (!is_display_descriptor(timing, EDID_DETAIL_MONITOR_RANGE))
return;
@ -5992,18 +5994,28 @@ void get_monitor_range(const struct detailed_timing *timing,
monitor_range->min_vfreq = range->min_vfreq;
monitor_range->max_vfreq = range->max_vfreq;
if (edid->revision >= 4) {
if (data->pad2 & DRM_EDID_RANGE_OFFSET_MIN_VFREQ)
monitor_range->min_vfreq += 255;
if (data->pad2 & DRM_EDID_RANGE_OFFSET_MAX_VFREQ)
monitor_range->max_vfreq += 255;
}
}
static void drm_get_monitor_range(struct drm_connector *connector,
const struct drm_edid *drm_edid)
{
struct drm_display_info *info = &connector->display_info;
const struct drm_display_info *info = &connector->display_info;
struct detailed_mode_closure closure = {
.connector = connector,
.drm_edid = drm_edid,
};
if (!version_greater(drm_edid, 1, 1))
return;
drm_for_each_detailed_block(drm_edid, get_monitor_range,
&info->monitor_range);
drm_for_each_detailed_block(drm_edid, get_monitor_range, &closure);
DRM_DEBUG_KMS("Supported Monitor Refresh rate range is %d Hz - %d Hz\n",
info->monitor_range.min_vfreq,

7
drivers/gpu/drm/i915/display/intel_bios.c
View File

@ -479,6 +479,13 @@ init_bdb_block(struct drm_i915_private *i915,
block_size = get_blocksize(block);
/*
* Version number and new block size are considered
* part of the header for MIPI sequenece block v3+.
*/
if (section_id == BDB_MIPI_SEQUENCE && *(const u8 *)block >= 3)
block_size += 5;
entry = kzalloc(struct_size(entry, data, max(min_size, block_size) + 3),
GFP_KERNEL);
if (!entry) {

22
drivers/gpu/drm/i915/display/intel_dp_link_training.c
View File

@ -671,6 +671,28 @@ intel_dp_prepare_link_train(struct intel_dp *intel_dp,
intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
&link_bw, &rate_select);
/*
* WaEdpLinkRateDataReload
*
* Parade PS8461E MUX (used on varius TGL+ laptops) needs
* to snoop the link rates reported by the sink when we
* use LINK_RATE_SET in order to operate in jitter cleaning
* mode (as opposed to redriver mode). Unfortunately it
* loses track of the snooped link rates when powered down,
* so we need to make it re-snoop often. Without this high
* link rates are not stable.
*/
if (!link_bw) {
struct intel_connector *connector = intel_dp->attached_connector;
__le16 sink_rates[DP_MAX_SUPPORTED_RATES];
drm_dbg_kms(&i915->drm, "[CONNECTOR:%d:%s] Reloading eDP link rates\n",
connector->base.base.id, connector->base.name);
drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES,
sink_rates, sizeof(sink_rates));
}
if (link_bw)
drm_dbg_kms(&i915->drm,
"[ENCODER:%d:%s] Using LINK_BW_SET value %02x\n",

3
drivers/gpu/drm/i915/gem/i915_gem_object.c
View File

@ -723,6 +723,9 @@ bool i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj)
bool lmem_placement = false;
int i;
if (!HAS_FLAT_CCS(to_i915(obj->base.dev)))
return false;
for (i = 0; i < obj->mm.n_placements; i++) {
/* Compression is not allowed for the objects with smem placement */
if (obj->mm.placements[i]->type == INTEL_MEMORY_SYSTEM)

2
drivers/gpu/drm/i915/gem/i915_gem_ttm.c
View File

@ -297,7 +297,7 @@ static struct ttm_tt *i915_ttm_tt_create(struct ttm_buffer_object *bo,
i915_tt->is_shmem = true;
}
if (HAS_FLAT_CCS(i915) && i915_gem_object_needs_ccs_pages(obj))
if (i915_gem_object_needs_ccs_pages(obj))
ccs_pages = DIV_ROUND_UP(DIV_ROUND_UP(bo->base.size,
NUM_BYTES_PER_CCS_BYTE),
PAGE_SIZE);

19
drivers/gpu/drm/i915/gt/intel_llc.c
View File

@ -12,6 +12,7 @@
#include "intel_llc.h"
#include "intel_mchbar_regs.h"
#include "intel_pcode.h"
#include "intel_rps.h"
struct ia_constants {
unsigned int min_gpu_freq;
@ -55,9 +56,6 @@ static bool get_ia_constants(struct intel_llc *llc,
if (!HAS_LLC(i915) || IS_DGFX(i915))
return false;
if (rps->max_freq <= rps->min_freq)
return false;
consts->max_ia_freq = cpu_max_MHz();
consts->min_ring_freq =
@ -65,13 +63,8 @@ static bool get_ia_constants(struct intel_llc *llc,
/* convert DDR frequency from units of 266.6MHz to bandwidth */
consts->min_ring_freq = mult_frac(consts->min_ring_freq, 8, 3);
consts->min_gpu_freq = rps->min_freq;
consts->max_gpu_freq = rps->max_freq;
if (GRAPHICS_VER(i915) >= 9) {
/* Convert GT frequency to 50 HZ units */
consts->min_gpu_freq /= GEN9_FREQ_SCALER;
consts->max_gpu_freq /= GEN9_FREQ_SCALER;
}
consts->min_gpu_freq = intel_rps_get_min_raw_freq(rps);
consts->max_gpu_freq = intel_rps_get_max_raw_freq(rps);
return true;
}
@ -130,6 +123,12 @@ static void gen6_update_ring_freq(struct intel_llc *llc)
if (!get_ia_constants(llc, &consts))
return;
/*
* Although this is unlikely on any platform during initialization,
* let's ensure we don't get accidentally into infinite loop
*/
if (consts.max_gpu_freq <= consts.min_gpu_freq)
return;
/*
* For each potential GPU frequency, load a ring frequency we'd like
* to use for memory access. We do this by specifying the IA frequency

50
drivers/gpu/drm/i915/gt/intel_rps.c
View File

@ -2126,6 +2126,31 @@ u32 intel_rps_get_max_frequency(struct intel_rps *rps)
return intel_gpu_freq(rps, rps->max_freq_softlimit);
}
/**
* intel_rps_get_max_raw_freq - returns the max frequency in some raw format.
* @rps: the intel_rps structure
*
* Returns the max frequency in a raw format. In newer platforms raw is in
* units of 50 MHz.
*/
u32 intel_rps_get_max_raw_freq(struct intel_rps *rps)
{
struct intel_guc_slpc *slpc = rps_to_slpc(rps);
u32 freq;
if (rps_uses_slpc(rps)) {
return DIV_ROUND_CLOSEST(slpc->rp0_freq,
GT_FREQUENCY_MULTIPLIER);
} else {
freq = rps->max_freq;
if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) {
/* Convert GT frequency to 50 MHz units */
freq /= GEN9_FREQ_SCALER;
}
return freq;
}
}
u32 intel_rps_get_rp0_frequency(struct intel_rps *rps)
{
struct intel_guc_slpc *slpc = rps_to_slpc(rps);
@ -2214,6 +2239,31 @@ u32 intel_rps_get_min_frequency(struct intel_rps *rps)
return intel_gpu_freq(rps, rps->min_freq_softlimit);
}
/**
* intel_rps_get_min_raw_freq - returns the min frequency in some raw format.
* @rps: the intel_rps structure
*
* Returns the min frequency in a raw format. In newer platforms raw is in
* units of 50 MHz.
*/
u32 intel_rps_get_min_raw_freq(struct intel_rps *rps)
{
struct intel_guc_slpc *slpc = rps_to_slpc(rps);
u32 freq;
if (rps_uses_slpc(rps)) {
return DIV_ROUND_CLOSEST(slpc->min_freq,
GT_FREQUENCY_MULTIPLIER);
} else {
freq = rps->min_freq;
if (GRAPHICS_VER(rps_to_i915(rps)) >= 9) {
/* Convert GT frequency to 50 MHz units */
freq /= GEN9_FREQ_SCALER;
}
return freq;
}
}
static int set_min_freq(struct intel_rps *rps, u32 val)
{
int ret = 0;

2
drivers/gpu/drm/i915/gt/intel_rps.h
View File

@ -37,8 +37,10 @@ u32 intel_rps_get_cagf(struct intel_rps *rps, u32 rpstat1);
u32 intel_rps_read_actual_frequency(struct intel_rps *rps);
u32 intel_rps_get_requested_frequency(struct intel_rps *rps);
u32 intel_rps_get_min_frequency(struct intel_rps *rps);
u32 intel_rps_get_min_raw_freq(struct intel_rps *rps);
int intel_rps_set_min_frequency(struct intel_rps *rps, u32 val);
u32 intel_rps_get_max_frequency(struct intel_rps *rps);
u32 intel_rps_get_max_raw_freq(struct intel_rps *rps);
int intel_rps_set_max_frequency(struct intel_rps *rps, u32 val);
u32 intel_rps_get_rp0_frequency(struct intel_rps *rps);
u32 intel_rps_get_rp1_frequency(struct intel_rps *rps);

11
drivers/gpu/drm/panfrost/panfrost_devfreq.c
View File

@ -131,6 +131,17 @@ int panfrost_devfreq_init(struct panfrost_device *pfdev)
return PTR_ERR(opp);
panfrost_devfreq_profile.initial_freq = cur_freq;
/*
* Set the recommend OPP this will enable and configure the regulator
* if any and will avoid a switch off by regulator_late_cleanup()
*/
ret = dev_pm_opp_set_opp(dev, opp);
if (ret) {
DRM_DEV_ERROR(dev, "Couldn't set recommended OPP\n");
return ret;
}
dev_pm_opp_put(opp);
/*

13
drivers/gpu/drm/ttm/ttm_bo_util.c
View File

@ -236,16 +236,19 @@ static int ttm_buffer_object_transfer(struct ttm_buffer_object *bo,
if (bo->type != ttm_bo_type_sg)
fbo->base.base.resv = &fbo->base.base._resv;
if (fbo->base.resource) {
ttm_resource_set_bo(fbo->base.resource, &fbo->base);
bo->resource = NULL;
}
dma_resv_init(&fbo->base.base._resv);
fbo->base.base.dev = NULL;
ret = dma_resv_trylock(&fbo->base.base._resv);
WARN_ON(!ret);
if (fbo->base.resource) {
ttm_resource_set_bo(fbo->base.resource, &fbo->base);
bo->resource = NULL;
ttm_bo_set_bulk_move(&fbo->base, NULL);
} else {
fbo->base.bulk_move = NULL;
}
ret = dma_resv_reserve_fences(&fbo->base.base._resv, 1);
if (ret) {
kfree(fbo);

4
include/drm/drm_connector.h
View File

@ -319,8 +319,8 @@ enum drm_panel_orientation {
* EDID's detailed monitor range
*/
struct drm_monitor_range_info {
u8 min_vfreq;
u8 max_vfreq;
u16 min_vfreq;
u16 max_vfreq;
};
/**

5
include/drm/drm_edid.h
View File

@ -92,6 +92,11 @@ struct detailed_data_string {
u8 str[13];
} __attribute__((packed));
#define DRM_EDID_RANGE_OFFSET_MIN_VFREQ (1 << 0) /* 1.4 */
#define DRM_EDID_RANGE_OFFSET_MAX_VFREQ (1 << 1) /* 1.4 */
#define DRM_EDID_RANGE_OFFSET_MIN_HFREQ (1 << 2) /* 1.4 */
#define DRM_EDID_RANGE_OFFSET_MAX_HFREQ (1 << 3) /* 1.4 */
#define DRM_EDID_DEFAULT_GTF_SUPPORT_FLAG 0x00
#define DRM_EDID_RANGE_LIMITS_ONLY_FLAG 0x01
#define DRM_EDID_SECONDARY_GTF_SUPPORT_FLAG 0x02